1 /* 2 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /////////////////////////////////////////////////////////////////////////////////////////////// 20 // 21 // wcss_seq_hwiobase.h : automatically generated by Autoseq 3.8 11/13/2019 22 // User Name:sanjdas 23 // 24 // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. 25 // 26 /////////////////////////////////////////////////////////////////////////////////////////////// 27 28 #ifndef __WCSS_SEQ_BASE_H__ 29 #define __WCSS_SEQ_BASE_H__ 30 31 #ifdef SCALE_INCLUDES 32 #include "HALhwio.h" 33 #else 34 #include "msmhwio.h" 35 #endif 36 37 #ifndef SOC_WCSS_BASE_ADDR 38 #if defined(WCSS_BASE) 39 #if ( WCSS_BASE != 0x0 ) 40 #error WCSS_BASE incorrectly redefined! 41 #endif 42 #endif 43 44 #define SOC_WCSS_BASE_ADDR 0x0 45 #else 46 #if ( SOC_WCSS_BASE_ADDR != 0x0 ) 47 #error SOC_WCSS_BASE_ADDR incorrectly redefined! 48 #endif 49 #endif 50 51 /////////////////////////////////////////////////////////////////////////////////////////////// 52 // Instance Relative Offsets from Block wcss 53 /////////////////////////////////////////////////////////////////////////////////////////////// 54 55 #define SEQ_WCSS_UMAC_NOC_OFFSET 0x00140000 56 #define SEQ_WCSS_PHYA_OFFSET 0x00300000 57 #define SEQ_WCSS_PHYA_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00300000 58 #define SEQ_WCSS_PHYA_WFAX_PCSS_REG_MAP_OFFSET 0x00380000 59 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00380400 60 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00380800 61 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00380c00 62 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00381000 63 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00381400 64 #define SEQ_WCSS_PHYA_WFAX_PCSS_DUAL_TIMER_REG_MAP_OFFSET 0x00381800 65 #define SEQ_WCSS_PHYA_WFAX_PCSS_WATCHDOG_REG_MAP_OFFSET 0x00381c00 66 #define SEQ_WCSS_PHYA_WFAX_PCSS_XDMAC5_REG_MAP_OFFSET 0x00382c00 67 #define SEQ_WCSS_PHYA_WFAX_PCSS_XDMAC6_REG_MAP_OFFSET 0x00383000 68 #define SEQ_WCSS_PHYA_WFAX_NOC_REG_MAP_OFFSET 0x00388000 69 #define SEQ_WCSS_PHYA_WFAX_TXFD_REG_MAP_OFFSET 0x00390000 70 #define SEQ_WCSS_PHYA_WFAX_RXTD_REG_MAP_OFFSET 0x003a0000 71 #define SEQ_WCSS_PHYA_WFAX_TXTD_REG_MAP_OFFSET 0x003b0000 72 #define SEQ_WCSS_PHYA_WFAX_TXBF_REG_MAP_OFFSET 0x003c0000 73 #define SEQ_WCSS_PHYA_WFAX_DEMFRONT_0_REG_MAP_OFFSET 0x00400000 74 #define SEQ_WCSS_PHYA_WFAX_PHYRF_REG_MAP_OFFSET 0x00480000 75 #define SEQ_WCSS_PHYA_WFAX_ROBE_REG_MAP_OFFSET 0x004b0000 76 #define SEQ_WCSS_PHYA_WFAX_DEMFRONT_1_REG_MAP_OFFSET 0x00500000 77 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_OFFSET 0x005c0000 78 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_OFFSET 0x005c0000 79 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_SYSCTRL_OFFSET 0x005cf000 80 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_TLMM_OFFSET 0x005cf400 81 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x005cf800 82 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AON_1P8_REG_OFFSET 0x005cfc00 83 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TLMM_OFFSET 0x005c0000 84 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TRC_OFFSET 0x005c0200 85 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_COEX_LTE_REG_OFFSET 0x005c5000 86 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_OFFSET 0x005d1000 87 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x005c7000 88 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_SECURITY_CONTROL_CORE_OFFSET 0x005c9b00 89 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_RAW_FUSE_OFFSET 0x005c7000 90 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET 0x005cb000 91 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x005d4000 92 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_CAL_OFFSET 0x005d42f0 93 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x005d4000 94 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_XFEM_OFFSET 0x005d4240 95 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET 0x005d42c0 96 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x005d4300 97 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x005d4400 98 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET 0x005d4480 99 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x005d4800 100 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x005d4c00 101 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_OFFSET 0x005d5000 102 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x005d5400 103 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x005d6000 104 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x005d6040 105 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x005d6100 106 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x005d6140 107 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x005d6180 108 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x005d61c0 109 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x005d6280 110 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x005d6800 111 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x005d6840 112 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x005d6900 113 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x005d6940 114 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x005d6980 115 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x005d69c0 116 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x005d6a80 117 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_BS_OFFSET 0x005d7000 118 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_CLBS_OFFSET 0x005d7040 119 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_BIST_OFFSET 0x005d7100 120 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_PC_OFFSET 0x005d7140 121 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_KVCO_OFFSET 0x005d7180 122 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_AC_OFFSET 0x005d71c0 123 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_LO_OFFSET 0x005d7280 124 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_OFFSET 0x005da000 125 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET 0x005dc000 126 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_MTOP_OFFSET 0x005dc000 127 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXBB_OFFSET 0x005dc800 128 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXFE_CH0_OFFSET 0x005dcc00 129 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXFE_CH1_OFFSET 0x005dd000 130 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x005de800 131 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_OFFSET 0x005de980 132 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x005de9c0 133 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_MISC_OFFSET 0x005deac0 134 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXBB_CH0_OFFSET 0x005dec00 135 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXBB_CH1_OFFSET 0x005dee00 136 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXFE_CH0_OFFSET 0x005df000 137 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXFE_CH1_OFFSET 0x005df200 138 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x005dfc00 139 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x005dfc40 140 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x005dfc80 141 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x005dfcc0 142 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x005e0000 143 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x005e0000 144 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x005e1000 145 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x005e1300 146 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x005e2000 147 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x005e4000 148 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x005e8000 149 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x005e8400 150 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x005e8800 151 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x005e9000 152 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x005e9300 153 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x005ea000 154 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_CH0_OFFSET 0x005ea400 155 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_CH0_OFFSET 0x005ea580 156 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_CH0_OFFSET 0x005ea5c0 157 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_CH0_OFFSET 0x005ea6c0 158 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_CH0_OFFSET 0x005ea734 159 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_CH0_OFFSET 0x005ea740 160 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_CH0_OFFSET 0x005ea800 161 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_CH0_OFFSET 0x005ea840 162 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_CH0_OFFSET 0x005ea880 163 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_CH0_OFFSET 0x005ea8c0 164 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_CH0_OFFSET 0x005ea900 165 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_CH0_OFFSET 0x005ea99c 166 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x005ec000 167 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH1_OFFSET 0x005f0000 168 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x005f1000 169 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x005f1300 170 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x005f2000 171 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x005f4000 172 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET 0x005f8000 173 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x005f8400 174 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x005f8800 175 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x005f9000 176 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x005f9300 177 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x005fa000 178 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_CH1_OFFSET 0x005fa400 179 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_CH1_OFFSET 0x005fa580 180 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_CH1_OFFSET 0x005fa5c0 181 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_CH1_OFFSET 0x005fa6c0 182 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_CH1_OFFSET 0x005fa734 183 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_CH1_OFFSET 0x005fa740 184 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_CH1_OFFSET 0x005fa800 185 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_CH1_OFFSET 0x005fa840 186 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_CH1_OFFSET 0x005fa880 187 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_CH1_OFFSET 0x005fa8c0 188 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_CH1_OFFSET 0x005fa900 189 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_CH1_OFFSET 0x005fa99c 190 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH1_OFFSET 0x005fc000 191 #define SEQ_WCSS_UMAC_OFFSET 0x00a00000 192 #define SEQ_WCSS_UMAC_CXC_TOP_REG_OFFSET 0x00a20000 193 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00a20000 194 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00a22000 195 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00a24000 196 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00a26000 197 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00a28000 198 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x00a2a000 199 #define SEQ_WCSS_UMAC_MAC_TRACER_REG_OFFSET 0x00a30000 200 #define SEQ_WCSS_UMAC_WBM_REG_OFFSET 0x00a34000 201 #define SEQ_WCSS_UMAC_REO_REG_OFFSET 0x00a38000 202 #define SEQ_WCSS_UMAC_TQM_REG_OFFSET 0x00a3c000 203 #define SEQ_WCSS_UMAC_MAC_UMCMN_REG_OFFSET 0x00a40000 204 #define SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET 0x00a44000 205 #define SEQ_WCSS_UMAC_MAC_CMN_PARSER_CE_REG_OFFSET 0x00a47000 206 #define SEQ_WCSS_WMAC0_OFFSET 0x00a80000 207 #define SEQ_WCSS_WMAC0_MAC_PDG_REG_OFFSET 0x00a80000 208 #define SEQ_WCSS_WMAC0_MAC_TXDMA_REG_OFFSET 0x00a83000 209 #define SEQ_WCSS_WMAC0_MAC_RXDMA_REG_OFFSET 0x00a86000 210 #define SEQ_WCSS_WMAC0_MAC_MCMN_REG_OFFSET 0x00a89000 211 #define SEQ_WCSS_WMAC0_MAC_RXPCU_REG_OFFSET 0x00a8c000 212 #define SEQ_WCSS_WMAC0_MAC_TXPCU_REG_OFFSET 0x00a8f000 213 #define SEQ_WCSS_WMAC0_MAC_AMPI_REG_OFFSET 0x00a92000 214 #define SEQ_WCSS_WMAC0_MAC_RXOLE_REG_OFFSET 0x00a95000 215 #define SEQ_WCSS_WMAC0_MAC_RXOLE_PARSER_REG_OFFSET 0x00a98000 216 #define SEQ_WCSS_WMAC0_MAC_CCE_REG_OFFSET 0x00a9b000 217 #define SEQ_WCSS_WMAC0_MAC_TXOLE_REG_OFFSET 0x00a9e000 218 #define SEQ_WCSS_WMAC0_MAC_TXOLE_PARSER_REG_OFFSET 0x00aa1000 219 #define SEQ_WCSS_WMAC0_MAC_RRI_REG_OFFSET 0x00aa4000 220 #define SEQ_WCSS_WMAC0_MAC_CRYPTO_REG_OFFSET 0x00aa7000 221 #define SEQ_WCSS_WMAC0_MAC_HWSCH_REG_OFFSET 0x00aaa000 222 #define SEQ_WCSS_WMAC0_MAC_MXI_REG_OFFSET 0x00ab0000 223 #define SEQ_WCSS_WMAC0_MAC_SFM_REG_OFFSET 0x00ab3000 224 #define SEQ_WCSS_APB_TSLV_OFFSET 0x00b40000 225 #define SEQ_WCSS_TOP_CMN_OFFSET 0x00b50000 226 #define SEQ_WCSS_WCMN_CORE_OFFSET 0x00b58000 227 #define SEQ_WCSS_WFSS_PMM_OFFSET 0x00b60000 228 #define SEQ_WCSS_PMM_TOP_OFFSET 0x00b70000 229 #define SEQ_WCSS_DBG_OFFSET 0x00b90000 230 #define SEQ_WCSS_DBG_WCSS_DBG_DAPROM_OFFSET 0x00b90000 231 #define SEQ_WCSS_DBG_CSR_WCSS_DBG_CSR_OFFSET 0x00b91000 232 #define SEQ_WCSS_DBG_TSGEN_CXTSGEN_OFFSET 0x00b92000 233 #define SEQ_WCSS_DBG_CTIDBG_QC_CTI_32T_8CH_OFFSET 0x00b94000 234 #define SEQ_WCSS_DBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00b95000 235 #define SEQ_WCSS_DBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00b96000 236 #define SEQ_WCSS_DBG_EVENT_MACEVENT_OFFSET 0x00bb0000 237 #define SEQ_WCSS_DBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb1000 238 #define SEQ_WCSS_DBG_TLV_MACTLV_OFFSET 0x00bb2000 239 #define SEQ_WCSS_DBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb3000 240 #define SEQ_WCSS_DBG_TBUS_MACTBUS_OFFSET 0x00bb4000 241 #define SEQ_WCSS_DBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb5000 242 #define SEQ_WCSS_DBG_CTIMAC_QC_CTI_12T_8CH_OFFSET 0x00bb6000 243 #define SEQ_WCSS_DBG_WCSS_DBG_TSTMP_INJCTR_OFFSET 0x00bb8000 244 #define SEQ_WCSS_DBG_TPDM_OFFSET 0x00bb9000 245 #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00bb9280 246 #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00bb9000 247 #define SEQ_WCSS_DBG_TPDA_OFFSET 0x00bba000 248 #define SEQ_WCSS_DBG_CXATBFUNNEL_128W8SP_OFFSET 0x00bbb000 249 #define SEQ_WCSS_DBG_TMC_CXTMC_F128W32K_OFFSET 0x00bbc000 250 #define SEQ_WCSS_DBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET 0x00bbe000 251 #define SEQ_WCSS_DBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET 0x00bbf000 252 #define SEQ_WCSS_DBG_OUTDMUX_ATB_DEMUX_OFFSET 0x00bc0000 253 #define SEQ_WCSS_DBG_TRCCNTRS_OFFSET 0x00bc1000 254 #define SEQ_WCSS_DBG_TLV_TPDM_ATB128_CMB64_OFFSET 0x00bc2000 255 #define SEQ_WCSS_DBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00bc2280 256 #define SEQ_WCSS_DBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00bc2000 257 #define SEQ_WCSS_DBG_MISC_TPDM_ATB128_CMB64_OFFSET 0x00bc3000 258 #define SEQ_WCSS_DBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00bc3280 259 #define SEQ_WCSS_DBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00bc3000 260 #define SEQ_WCSS_DBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET 0x00bc4000 261 #define SEQ_WCSS_DBG_CTITGU_QC_CTI_4T_8CH_OFFSET 0x00bc5000 262 #define SEQ_WCSS_DBG_PHYADMUX_ATB_DEMUX_OFFSET 0x00bc6000 263 #define SEQ_WCSS_DBG_MISCFUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bc8000 264 #define SEQ_WCSS_DBG_UNOC_UMAC_NOC_OFFSET 0x00bd0000 265 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_OFFSET 0x00be0000 266 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_PHYA_NOC_OFFSET 0x00be0000 267 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00be4000 268 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00be5000 269 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00be6000 270 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_ITM_OFFSET 0x00be8000 271 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_DWT_OFFSET 0x00be9000 272 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_FPB_OFFSET 0x00bea000 273 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_SCS_OFFSET 0x00beb000 274 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_M3_ETM_OFFSET 0x00bec000 275 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x00bed000 276 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_CPU0_M3_AHB_AP_OFFSET 0x00bee000 277 #define SEQ_WCSS_DBG_BUS_TIMEOUT_OFFSET 0x00c31000 278 #define SEQ_WCSS_RET_AHB_OFFSET 0x00c90000 279 #define SEQ_WCSS_WAHB_TSLV_OFFSET 0x00ca0000 280 #define SEQ_WCSS_CC_OFFSET 0x00cb0000 281 #define SEQ_WCSS_UMAC_ACMT_OFFSET 0x00cc0000 282 283 284 /////////////////////////////////////////////////////////////////////////////////////////////// 285 // Instance Relative Offsets from Block wfax_top 286 /////////////////////////////////////////////////////////////////////////////////////////////// 287 288 #define SEQ_WFAX_TOP_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00000000 289 #define SEQ_WFAX_TOP_WFAX_PCSS_REG_MAP_OFFSET 0x00080000 290 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00080400 291 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00080800 292 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00080c00 293 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00081000 294 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00081400 295 #define SEQ_WFAX_TOP_WFAX_PCSS_DUAL_TIMER_REG_MAP_OFFSET 0x00081800 296 #define SEQ_WFAX_TOP_WFAX_PCSS_WATCHDOG_REG_MAP_OFFSET 0x00081c00 297 #define SEQ_WFAX_TOP_WFAX_PCSS_XDMAC5_REG_MAP_OFFSET 0x00082c00 298 #define SEQ_WFAX_TOP_WFAX_PCSS_XDMAC6_REG_MAP_OFFSET 0x00083000 299 #define SEQ_WFAX_TOP_WFAX_NOC_REG_MAP_OFFSET 0x00088000 300 #define SEQ_WFAX_TOP_WFAX_TXFD_REG_MAP_OFFSET 0x00090000 301 #define SEQ_WFAX_TOP_WFAX_RXTD_REG_MAP_OFFSET 0x000a0000 302 #define SEQ_WFAX_TOP_WFAX_TXTD_REG_MAP_OFFSET 0x000b0000 303 #define SEQ_WFAX_TOP_WFAX_TXBF_REG_MAP_OFFSET 0x000c0000 304 #define SEQ_WFAX_TOP_WFAX_DEMFRONT_0_REG_MAP_OFFSET 0x00100000 305 #define SEQ_WFAX_TOP_WFAX_PHYRF_REG_MAP_OFFSET 0x00180000 306 #define SEQ_WFAX_TOP_WFAX_ROBE_REG_MAP_OFFSET 0x001b0000 307 #define SEQ_WFAX_TOP_WFAX_DEMFRONT_1_REG_MAP_OFFSET 0x00200000 308 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_OFFSET 0x002c0000 309 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_OFFSET 0x002c0000 310 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_SYSCTRL_OFFSET 0x002cf000 311 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_TLMM_OFFSET 0x002cf400 312 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x002cf800 313 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AON_1P8_REG_OFFSET 0x002cfc00 314 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TLMM_OFFSET 0x002c0000 315 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TRC_OFFSET 0x002c0200 316 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_COEX_LTE_REG_OFFSET 0x002c5000 317 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_OFFSET 0x002d1000 318 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x002c7000 319 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_SECURITY_CONTROL_CORE_OFFSET 0x002c9b00 320 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_RAW_FUSE_OFFSET 0x002c7000 321 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET 0x002cb000 322 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x002d4000 323 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_CAL_OFFSET 0x002d42f0 324 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x002d4000 325 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_XFEM_OFFSET 0x002d4240 326 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET 0x002d42c0 327 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x002d4300 328 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x002d4400 329 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET 0x002d4480 330 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x002d4800 331 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x002d4c00 332 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_OFFSET 0x002d5000 333 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x002d5400 334 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x002d6000 335 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x002d6040 336 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x002d6100 337 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x002d6140 338 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x002d6180 339 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x002d61c0 340 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x002d6280 341 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x002d6800 342 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x002d6840 343 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x002d6900 344 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x002d6940 345 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x002d6980 346 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x002d69c0 347 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x002d6a80 348 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_BS_OFFSET 0x002d7000 349 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_CLBS_OFFSET 0x002d7040 350 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_BIST_OFFSET 0x002d7100 351 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_PC_OFFSET 0x002d7140 352 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_KVCO_OFFSET 0x002d7180 353 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_AC_OFFSET 0x002d71c0 354 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_LO_OFFSET 0x002d7280 355 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_OFFSET 0x002da000 356 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET 0x002dc000 357 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_MTOP_OFFSET 0x002dc000 358 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXBB_OFFSET 0x002dc800 359 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXFE_CH0_OFFSET 0x002dcc00 360 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXFE_CH1_OFFSET 0x002dd000 361 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x002de800 362 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_OFFSET 0x002de980 363 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x002de9c0 364 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_MISC_OFFSET 0x002deac0 365 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXBB_CH0_OFFSET 0x002dec00 366 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXBB_CH1_OFFSET 0x002dee00 367 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXFE_CH0_OFFSET 0x002df000 368 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXFE_CH1_OFFSET 0x002df200 369 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x002dfc00 370 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x002dfc40 371 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x002dfc80 372 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x002dfcc0 373 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x002e0000 374 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x002e0000 375 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x002e1000 376 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x002e1300 377 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x002e2000 378 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x002e4000 379 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x002e8000 380 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x002e8400 381 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x002e8800 382 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x002e9000 383 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x002e9300 384 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x002ea000 385 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_CH0_OFFSET 0x002ea400 386 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_CH0_OFFSET 0x002ea580 387 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_CH0_OFFSET 0x002ea5c0 388 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_CH0_OFFSET 0x002ea6c0 389 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_CH0_OFFSET 0x002ea734 390 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_CH0_OFFSET 0x002ea740 391 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_CH0_OFFSET 0x002ea800 392 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_CH0_OFFSET 0x002ea840 393 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_CH0_OFFSET 0x002ea880 394 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_CH0_OFFSET 0x002ea8c0 395 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_CH0_OFFSET 0x002ea900 396 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_CH0_OFFSET 0x002ea99c 397 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x002ec000 398 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH1_OFFSET 0x002f0000 399 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x002f1000 400 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x002f1300 401 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x002f2000 402 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x002f4000 403 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET 0x002f8000 404 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x002f8400 405 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x002f8800 406 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x002f9000 407 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x002f9300 408 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x002fa000 409 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_CH1_OFFSET 0x002fa400 410 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_CH1_OFFSET 0x002fa580 411 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_CH1_OFFSET 0x002fa5c0 412 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_CH1_OFFSET 0x002fa6c0 413 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_CH1_OFFSET 0x002fa734 414 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_CH1_OFFSET 0x002fa740 415 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_CH1_OFFSET 0x002fa800 416 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_CH1_OFFSET 0x002fa840 417 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_CH1_OFFSET 0x002fa880 418 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_CH1_OFFSET 0x002fa8c0 419 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_CH1_OFFSET 0x002fa900 420 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_CH1_OFFSET 0x002fa99c 421 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH1_OFFSET 0x002fc000 422 423 424 /////////////////////////////////////////////////////////////////////////////////////////////// 425 // Instance Relative Offsets from Block rfa_from_wsi 426 /////////////////////////////////////////////////////////////////////////////////////////////// 427 428 #define SEQ_RFA_FROM_WSI_RFA_SOC_OFFSET 0x00000000 429 #define SEQ_RFA_FROM_WSI_RFA_SOC_AO_SYSCTRL_OFFSET 0x0000f000 430 #define SEQ_RFA_FROM_WSI_RFA_SOC_AO_TLMM_OFFSET 0x0000f400 431 #define SEQ_RFA_FROM_WSI_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x0000f800 432 #define SEQ_RFA_FROM_WSI_RFA_SOC_AON_1P8_REG_OFFSET 0x0000fc00 433 #define SEQ_RFA_FROM_WSI_RFA_SOC_HZ_TLMM_OFFSET 0x00000000 434 #define SEQ_RFA_FROM_WSI_RFA_SOC_HZ_TRC_OFFSET 0x00000200 435 #define SEQ_RFA_FROM_WSI_RFA_SOC_HZ_COEX_LTE_REG_OFFSET 0x00005000 436 #define SEQ_RFA_FROM_WSI_RFA_SOC_PMU_OFFSET 0x00011000 437 #define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x00007000 438 #define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_BT_SECURITY_CONTROL_CORE_OFFSET 0x00009b00 439 #define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_RAW_FUSE_OFFSET 0x00007000 440 #define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET 0x0000b000 441 #define SEQ_RFA_FROM_WSI_RFA_CMN_OFFSET 0x00014000 442 #define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_CAL_OFFSET 0x000142f0 443 #define SEQ_RFA_FROM_WSI_RFA_CMN_AON_OFFSET 0x00014000 444 #define SEQ_RFA_FROM_WSI_RFA_CMN_AON_XFEM_OFFSET 0x00014240 445 #define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_OFFSET 0x000142c0 446 #define SEQ_RFA_FROM_WSI_RFA_CMN_RFFE_M_OFFSET 0x00014300 447 #define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00014400 448 #define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_OTP_OFFSET 0x00014480 449 #define SEQ_RFA_FROM_WSI_RFA_CMN_CLKGEN_OFFSET 0x00014800 450 #define SEQ_RFA_FROM_WSI_RFA_CMN_BTFMPLL_OFFSET 0x00014c00 451 #define SEQ_RFA_FROM_WSI_RFA_CMN_BBPLL_OFFSET 0x00015000 452 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x00015400 453 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00016000 454 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00016040 455 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00016100 456 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00016140 457 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00016180 458 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000161c0 459 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00016280 460 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00016800 461 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00016840 462 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x00016900 463 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x00016940 464 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00016980 465 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x000169c0 466 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x00016a80 467 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_BS_OFFSET 0x00017000 468 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_CLBS_OFFSET 0x00017040 469 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_BIST_OFFSET 0x00017100 470 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_PC_OFFSET 0x00017140 471 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_KVCO_OFFSET 0x00017180 472 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_AC_OFFSET 0x000171c0 473 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_LO_OFFSET 0x00017280 474 #define SEQ_RFA_FROM_WSI_RFA_CMN_PMU_TEST_OFFSET 0x0001a000 475 #define SEQ_RFA_FROM_WSI_RFA_BT_OFFSET 0x0001c000 476 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_MTOP_OFFSET 0x0001c000 477 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_TXBB_OFFSET 0x0001c800 478 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_TXFE_CH0_OFFSET 0x0001cc00 479 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_TXFE_CH1_OFFSET 0x0001d000 480 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x0001e800 481 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_OFFSET 0x0001e980 482 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x0001e9c0 483 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_MISC_OFFSET 0x0001eac0 484 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_RXBB_CH0_OFFSET 0x0001ec00 485 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_RXBB_CH1_OFFSET 0x0001ee00 486 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_RXFE_CH0_OFFSET 0x0001f000 487 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_RXFE_CH1_OFFSET 0x0001f200 488 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BS_OFFSET 0x0001fc00 489 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BIST_OFFSET 0x0001fc40 490 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_PC_OFFSET 0x0001fc80 491 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_AC_OFFSET 0x0001fcc0 492 #define SEQ_RFA_FROM_WSI_RFA_WL_OFFSET 0x00020000 493 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_2G_CH0_OFFSET 0x00020000 494 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x00021000 495 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x00021300 496 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x00022000 497 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x00024000 498 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_5G_CH0_OFFSET 0x00028000 499 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH0_OFFSET 0x00028400 500 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH0_OFFSET 0x00028800 501 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x00029000 502 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x00029300 503 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x0002a000 504 #define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_CH0_OFFSET 0x0002a400 505 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_CH0_OFFSET 0x0002a580 506 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_DIG_CORRECTION_CH0_OFFSET 0x0002a5c0 507 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_MISC_CH0_OFFSET 0x0002a6c0 508 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_BBCLKGEN_CH0_OFFSET 0x0002a734 509 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_CH0_OFFSET 0x0002a740 510 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_EVEN_CH0_OFFSET 0x0002a800 511 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_ODD_CH0_OFFSET 0x0002a840 512 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_CH0_OFFSET 0x0002a880 513 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_ODD_CH0_OFFSET 0x0002a8c0 514 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_RO_CH0_OFFSET 0x0002a900 515 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_BBCLKGEN_CH0_OFFSET 0x0002a99c 516 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x0002c000 517 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_2G_CH1_OFFSET 0x00030000 518 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x00031000 519 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x00031300 520 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x00032000 521 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x00034000 522 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_5G_CH1_OFFSET 0x00038000 523 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH1_OFFSET 0x00038400 524 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH1_OFFSET 0x00038800 525 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x00039000 526 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x00039300 527 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x0003a000 528 #define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_CH1_OFFSET 0x0003a400 529 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_CH1_OFFSET 0x0003a580 530 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_DIG_CORRECTION_CH1_OFFSET 0x0003a5c0 531 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_MISC_CH1_OFFSET 0x0003a6c0 532 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_BBCLKGEN_CH1_OFFSET 0x0003a734 533 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_CH1_OFFSET 0x0003a740 534 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_EVEN_CH1_OFFSET 0x0003a800 535 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_ODD_CH1_OFFSET 0x0003a840 536 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_CH1_OFFSET 0x0003a880 537 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_ODD_CH1_OFFSET 0x0003a8c0 538 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_RO_CH1_OFFSET 0x0003a900 539 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_BBCLKGEN_CH1_OFFSET 0x0003a99c 540 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_5G_CH1_OFFSET 0x0003c000 541 542 543 /////////////////////////////////////////////////////////////////////////////////////////////// 544 // Instance Relative Offsets from Block rfa_soc 545 /////////////////////////////////////////////////////////////////////////////////////////////// 546 547 #define SEQ_RFA_SOC_AO_SYSCTRL_OFFSET 0x0000f000 548 #define SEQ_RFA_SOC_AO_TLMM_OFFSET 0x0000f400 549 #define SEQ_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x0000f800 550 #define SEQ_RFA_SOC_AON_1P8_REG_OFFSET 0x0000fc00 551 #define SEQ_RFA_SOC_HZ_TLMM_OFFSET 0x00000000 552 #define SEQ_RFA_SOC_HZ_TRC_OFFSET 0x00000200 553 #define SEQ_RFA_SOC_HZ_COEX_LTE_REG_OFFSET 0x00005000 554 #define SEQ_RFA_SOC_PMU_OFFSET 0x00011000 555 #define SEQ_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x00007000 556 #define SEQ_RFA_SOC_BT_SECURITY_CONTROL_BT_SECURITY_CONTROL_CORE_OFFSET 0x00009b00 557 #define SEQ_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_RAW_FUSE_OFFSET 0x00007000 558 #define SEQ_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET 0x0000b000 559 560 561 /////////////////////////////////////////////////////////////////////////////////////////////// 562 // Instance Relative Offsets from Block security_control_bt 563 /////////////////////////////////////////////////////////////////////////////////////////////// 564 565 #define SEQ_SECURITY_CONTROL_BT_BT_SECURITY_CONTROL_CORE_OFFSET 0x00002b00 566 #define SEQ_SECURITY_CONTROL_BT_BT_QFPROM_RAW_FUSE_OFFSET 0x00000000 567 #define SEQ_SECURITY_CONTROL_BT_BT_QFPROM_CORR_FUSE_OFFSET 0x00004000 568 569 570 /////////////////////////////////////////////////////////////////////////////////////////////// 571 // Instance Relative Offsets from Block rfa_cmn 572 /////////////////////////////////////////////////////////////////////////////////////////////// 573 574 #define SEQ_RFA_CMN_AON_COEX_CAL_OFFSET 0x000002f0 575 #define SEQ_RFA_CMN_AON_OFFSET 0x00000000 576 #define SEQ_RFA_CMN_AON_XFEM_OFFSET 0x00000240 577 #define SEQ_RFA_CMN_AON_COEX_OFFSET 0x000002c0 578 #define SEQ_RFA_CMN_RFFE_M_OFFSET 0x00000300 579 #define SEQ_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00000400 580 #define SEQ_RFA_CMN_RFA_OTP_OFFSET 0x00000480 581 #define SEQ_RFA_CMN_CLKGEN_OFFSET 0x00000800 582 #define SEQ_RFA_CMN_BTFMPLL_OFFSET 0x00000c00 583 #define SEQ_RFA_CMN_BBPLL_OFFSET 0x00001000 584 #define SEQ_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x00001400 585 #define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00002000 586 #define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00002040 587 #define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00002100 588 #define SEQ_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00002140 589 #define SEQ_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00002180 590 #define SEQ_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000021c0 591 #define SEQ_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00002280 592 #define SEQ_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00002800 593 #define SEQ_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00002840 594 #define SEQ_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x00002900 595 #define SEQ_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x00002940 596 #define SEQ_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00002980 597 #define SEQ_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x000029c0 598 #define SEQ_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x00002a80 599 #define SEQ_RFA_CMN_WL_SYNTH2_BS_OFFSET 0x00003000 600 #define SEQ_RFA_CMN_WL_SYNTH2_CLBS_OFFSET 0x00003040 601 #define SEQ_RFA_CMN_WL_SYNTH2_BIST_OFFSET 0x00003100 602 #define SEQ_RFA_CMN_WL_SYNTH2_PC_OFFSET 0x00003140 603 #define SEQ_RFA_CMN_WL_SYNTH2_KVCO_OFFSET 0x00003180 604 #define SEQ_RFA_CMN_WL_SYNTH2_AC_OFFSET 0x000031c0 605 #define SEQ_RFA_CMN_WL_SYNTH2_LO_OFFSET 0x00003280 606 #define SEQ_RFA_CMN_PMU_TEST_OFFSET 0x00006000 607 608 609 /////////////////////////////////////////////////////////////////////////////////////////////// 610 // Instance Relative Offsets from Block rfa_bt 611 /////////////////////////////////////////////////////////////////////////////////////////////// 612 613 #define SEQ_RFA_BT_BT_MTOP_OFFSET 0x00000000 614 #define SEQ_RFA_BT_BT_TXBB_OFFSET 0x00000800 615 #define SEQ_RFA_BT_BT_TXFE_CH0_OFFSET 0x00000c00 616 #define SEQ_RFA_BT_BT_TXFE_CH1_OFFSET 0x00001000 617 #define SEQ_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x00002800 618 #define SEQ_RFA_BT_BT_DAC_OFFSET 0x00002980 619 #define SEQ_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x000029c0 620 #define SEQ_RFA_BT_BT_DAC_MISC_OFFSET 0x00002ac0 621 #define SEQ_RFA_BT_BT_RXBB_CH0_OFFSET 0x00002c00 622 #define SEQ_RFA_BT_BT_RXBB_CH1_OFFSET 0x00002e00 623 #define SEQ_RFA_BT_BT_RXFE_CH0_OFFSET 0x00003000 624 #define SEQ_RFA_BT_BT_RXFE_CH1_OFFSET 0x00003200 625 #define SEQ_RFA_BT_BT_SYNTH_BS_OFFSET 0x00003c00 626 #define SEQ_RFA_BT_BT_SYNTH_BIST_OFFSET 0x00003c40 627 #define SEQ_RFA_BT_BT_SYNTH_PC_OFFSET 0x00003c80 628 #define SEQ_RFA_BT_BT_SYNTH_AC_OFFSET 0x00003cc0 629 630 631 /////////////////////////////////////////////////////////////////////////////////////////////// 632 // Instance Relative Offsets from Block rfa_wl 633 /////////////////////////////////////////////////////////////////////////////////////////////// 634 635 #define SEQ_RFA_WL_WL_MC_2G_CH0_OFFSET 0x00000000 636 #define SEQ_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x00001000 637 #define SEQ_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x00001300 638 #define SEQ_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x00002000 639 #define SEQ_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x00004000 640 #define SEQ_RFA_WL_WL_MC_5G_CH0_OFFSET 0x00008000 641 #define SEQ_RFA_WL_WL_RXBB_CH0_OFFSET 0x00008400 642 #define SEQ_RFA_WL_WL_TXBB_CH0_OFFSET 0x00008800 643 #define SEQ_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x00009000 644 #define SEQ_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x00009300 645 #define SEQ_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x0000a000 646 #define SEQ_RFA_WL_RBIST_TX_CH0_OFFSET 0x0000a400 647 #define SEQ_RFA_WL_WL_DAC_CH0_OFFSET 0x0000a580 648 #define SEQ_RFA_WL_WL_DAC_DIG_CORRECTION_CH0_OFFSET 0x0000a5c0 649 #define SEQ_RFA_WL_WL_DAC_MISC_CH0_OFFSET 0x0000a6c0 650 #define SEQ_RFA_WL_WL_DAC_BBCLKGEN_CH0_OFFSET 0x0000a734 651 #define SEQ_RFA_WL_WL_ADC_CH0_OFFSET 0x0000a740 652 #define SEQ_RFA_WL_WL_ADC_POSTPROC_I_EVEN_CH0_OFFSET 0x0000a800 653 #define SEQ_RFA_WL_WL_ADC_POSTPROC_I_ODD_CH0_OFFSET 0x0000a840 654 #define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_CH0_OFFSET 0x0000a880 655 #define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_ODD_CH0_OFFSET 0x0000a8c0 656 #define SEQ_RFA_WL_WL_ADC_POSTPROC_RO_CH0_OFFSET 0x0000a900 657 #define SEQ_RFA_WL_WL_ADC_BBCLKGEN_CH0_OFFSET 0x0000a99c 658 #define SEQ_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x0000c000 659 #define SEQ_RFA_WL_WL_MC_2G_CH1_OFFSET 0x00010000 660 #define SEQ_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x00011000 661 #define SEQ_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x00011300 662 #define SEQ_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x00012000 663 #define SEQ_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x00014000 664 #define SEQ_RFA_WL_WL_MC_5G_CH1_OFFSET 0x00018000 665 #define SEQ_RFA_WL_WL_RXBB_CH1_OFFSET 0x00018400 666 #define SEQ_RFA_WL_WL_TXBB_CH1_OFFSET 0x00018800 667 #define SEQ_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x00019000 668 #define SEQ_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x00019300 669 #define SEQ_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x0001a000 670 #define SEQ_RFA_WL_RBIST_TX_CH1_OFFSET 0x0001a400 671 #define SEQ_RFA_WL_WL_DAC_CH1_OFFSET 0x0001a580 672 #define SEQ_RFA_WL_WL_DAC_DIG_CORRECTION_CH1_OFFSET 0x0001a5c0 673 #define SEQ_RFA_WL_WL_DAC_MISC_CH1_OFFSET 0x0001a6c0 674 #define SEQ_RFA_WL_WL_DAC_BBCLKGEN_CH1_OFFSET 0x0001a734 675 #define SEQ_RFA_WL_WL_ADC_CH1_OFFSET 0x0001a740 676 #define SEQ_RFA_WL_WL_ADC_POSTPROC_I_EVEN_CH1_OFFSET 0x0001a800 677 #define SEQ_RFA_WL_WL_ADC_POSTPROC_I_ODD_CH1_OFFSET 0x0001a840 678 #define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_CH1_OFFSET 0x0001a880 679 #define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_ODD_CH1_OFFSET 0x0001a8c0 680 #define SEQ_RFA_WL_WL_ADC_POSTPROC_RO_CH1_OFFSET 0x0001a900 681 #define SEQ_RFA_WL_WL_ADC_BBCLKGEN_CH1_OFFSET 0x0001a99c 682 #define SEQ_RFA_WL_WL_MEM_5G_CH1_OFFSET 0x0001c000 683 684 685 /////////////////////////////////////////////////////////////////////////////////////////////// 686 // Instance Relative Offsets from Block umac_top_reg 687 /////////////////////////////////////////////////////////////////////////////////////////////// 688 689 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_OFFSET 0x00020000 690 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00020000 691 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00022000 692 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00024000 693 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00026000 694 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00028000 695 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0002a000 696 #define SEQ_UMAC_TOP_REG_MAC_TRACER_REG_OFFSET 0x00030000 697 #define SEQ_UMAC_TOP_REG_WBM_REG_OFFSET 0x00034000 698 #define SEQ_UMAC_TOP_REG_REO_REG_OFFSET 0x00038000 699 #define SEQ_UMAC_TOP_REG_TQM_REG_OFFSET 0x0003c000 700 #define SEQ_UMAC_TOP_REG_MAC_UMCMN_REG_OFFSET 0x00040000 701 #define SEQ_UMAC_TOP_REG_MAC_TCL_REG_OFFSET 0x00044000 702 #define SEQ_UMAC_TOP_REG_MAC_CMN_PARSER_CE_REG_OFFSET 0x00047000 703 704 705 /////////////////////////////////////////////////////////////////////////////////////////////// 706 // Instance Relative Offsets from Block cxc_top_reg 707 /////////////////////////////////////////////////////////////////////////////////////////////// 708 709 #define SEQ_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00000000 710 #define SEQ_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00002000 711 #define SEQ_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00004000 712 #define SEQ_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00006000 713 #define SEQ_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00008000 714 #define SEQ_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0000a000 715 716 717 /////////////////////////////////////////////////////////////////////////////////////////////// 718 // Instance Relative Offsets from Block wmac_top_reg 719 /////////////////////////////////////////////////////////////////////////////////////////////// 720 721 #define SEQ_WMAC_TOP_REG_MAC_PDG_REG_OFFSET 0x00000000 722 #define SEQ_WMAC_TOP_REG_MAC_TXDMA_REG_OFFSET 0x00003000 723 #define SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET 0x00006000 724 #define SEQ_WMAC_TOP_REG_MAC_MCMN_REG_OFFSET 0x00009000 725 #define SEQ_WMAC_TOP_REG_MAC_RXPCU_REG_OFFSET 0x0000c000 726 #define SEQ_WMAC_TOP_REG_MAC_TXPCU_REG_OFFSET 0x0000f000 727 #define SEQ_WMAC_TOP_REG_MAC_AMPI_REG_OFFSET 0x00012000 728 #define SEQ_WMAC_TOP_REG_MAC_RXOLE_REG_OFFSET 0x00015000 729 #define SEQ_WMAC_TOP_REG_MAC_RXOLE_PARSER_REG_OFFSET 0x00018000 730 #define SEQ_WMAC_TOP_REG_MAC_CCE_REG_OFFSET 0x0001b000 731 #define SEQ_WMAC_TOP_REG_MAC_TXOLE_REG_OFFSET 0x0001e000 732 #define SEQ_WMAC_TOP_REG_MAC_TXOLE_PARSER_REG_OFFSET 0x00021000 733 #define SEQ_WMAC_TOP_REG_MAC_RRI_REG_OFFSET 0x00024000 734 #define SEQ_WMAC_TOP_REG_MAC_CRYPTO_REG_OFFSET 0x00027000 735 #define SEQ_WMAC_TOP_REG_MAC_HWSCH_REG_OFFSET 0x0002a000 736 #define SEQ_WMAC_TOP_REG_MAC_MXI_REG_OFFSET 0x00030000 737 #define SEQ_WMAC_TOP_REG_MAC_SFM_REG_OFFSET 0x00033000 738 739 740 /////////////////////////////////////////////////////////////////////////////////////////////// 741 // Instance Relative Offsets from Block wcssdbg 742 /////////////////////////////////////////////////////////////////////////////////////////////// 743 744 #define SEQ_WCSSDBG_WCSS_DBG_DAPROM_OFFSET 0x00000000 745 #define SEQ_WCSSDBG_CSR_WCSS_DBG_CSR_OFFSET 0x00001000 746 #define SEQ_WCSSDBG_TSGEN_CXTSGEN_OFFSET 0x00002000 747 #define SEQ_WCSSDBG_CTIDBG_QC_CTI_32T_8CH_OFFSET 0x00004000 748 #define SEQ_WCSSDBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00005000 749 #define SEQ_WCSSDBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00006000 750 #define SEQ_WCSSDBG_EVENT_MACEVENT_OFFSET 0x00020000 751 #define SEQ_WCSSDBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00021000 752 #define SEQ_WCSSDBG_TLV_MACTLV_OFFSET 0x00022000 753 #define SEQ_WCSSDBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00023000 754 #define SEQ_WCSSDBG_TBUS_MACTBUS_OFFSET 0x00024000 755 #define SEQ_WCSSDBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00025000 756 #define SEQ_WCSSDBG_CTIMAC_QC_CTI_12T_8CH_OFFSET 0x00026000 757 #define SEQ_WCSSDBG_WCSS_DBG_TSTMP_INJCTR_OFFSET 0x00028000 758 #define SEQ_WCSSDBG_TPDM_OFFSET 0x00029000 759 #define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00029280 760 #define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00029000 761 #define SEQ_WCSSDBG_TPDA_OFFSET 0x0002a000 762 #define SEQ_WCSSDBG_CXATBFUNNEL_128W8SP_OFFSET 0x0002b000 763 #define SEQ_WCSSDBG_TMC_CXTMC_F128W32K_OFFSET 0x0002c000 764 #define SEQ_WCSSDBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET 0x0002e000 765 #define SEQ_WCSSDBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET 0x0002f000 766 #define SEQ_WCSSDBG_OUTDMUX_ATB_DEMUX_OFFSET 0x00030000 767 #define SEQ_WCSSDBG_TRCCNTRS_OFFSET 0x00031000 768 #define SEQ_WCSSDBG_TLV_TPDM_ATB128_CMB64_OFFSET 0x00032000 769 #define SEQ_WCSSDBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00032280 770 #define SEQ_WCSSDBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00032000 771 #define SEQ_WCSSDBG_MISC_TPDM_ATB128_CMB64_OFFSET 0x00033000 772 #define SEQ_WCSSDBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00033280 773 #define SEQ_WCSSDBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00033000 774 #define SEQ_WCSSDBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET 0x00034000 775 #define SEQ_WCSSDBG_CTITGU_QC_CTI_4T_8CH_OFFSET 0x00035000 776 #define SEQ_WCSSDBG_PHYADMUX_ATB_DEMUX_OFFSET 0x00036000 777 #define SEQ_WCSSDBG_MISCFUN_CXATBFUNNEL_64W8SP_OFFSET 0x00038000 778 #define SEQ_WCSSDBG_UNOC_UMAC_NOC_OFFSET 0x00040000 779 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_OFFSET 0x00050000 780 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_PHYA_NOC_OFFSET 0x00050000 781 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00054000 782 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00055000 783 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00056000 784 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_ITM_OFFSET 0x00058000 785 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_DWT_OFFSET 0x00059000 786 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_FPB_OFFSET 0x0005a000 787 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_SCS_OFFSET 0x0005b000 788 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_M3_ETM_OFFSET 0x0005c000 789 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x0005d000 790 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_CPU0_M3_AHB_AP_OFFSET 0x0005e000 791 #define SEQ_WCSSDBG_BUS_TIMEOUT_OFFSET 0x000a1000 792 793 794 /////////////////////////////////////////////////////////////////////////////////////////////// 795 // Instance Relative Offsets from Block tpdm_atb64_cmb40_dsb256_csbe6c04f7 796 /////////////////////////////////////////////////////////////////////////////////////////////// 797 798 #define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00000280 799 #define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00000000 800 801 802 /////////////////////////////////////////////////////////////////////////////////////////////// 803 // Instance Relative Offsets from Block tpdm_atb128_cmb64 804 /////////////////////////////////////////////////////////////////////////////////////////////// 805 806 #define SEQ_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00000280 807 #define SEQ_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00000000 808 809 810 /////////////////////////////////////////////////////////////////////////////////////////////// 811 // Instance Relative Offsets from Block phya_dbg 812 /////////////////////////////////////////////////////////////////////////////////////////////// 813 814 #define SEQ_PHYA_DBG_PHYA_NOC_OFFSET 0x00000000 815 #define SEQ_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00004000 816 #define SEQ_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00005000 817 #define SEQ_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00006000 818 #define SEQ_PHYA_DBG_ITM_OFFSET 0x00008000 819 #define SEQ_PHYA_DBG_DWT_OFFSET 0x00009000 820 #define SEQ_PHYA_DBG_FPB_OFFSET 0x0000a000 821 #define SEQ_PHYA_DBG_SCS_OFFSET 0x0000b000 822 #define SEQ_PHYA_DBG_M3_ETM_OFFSET 0x0000c000 823 #define SEQ_PHYA_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x0000d000 824 #define SEQ_PHYA_DBG_CPU0_M3_AHB_AP_OFFSET 0x0000e000 825 826 827 #endif 828 829