1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2018 The Linux Foundation. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for 5*5113495bSYour Name * any purpose with or without fee is hereby granted, provided that the 6*5113495bSYour Name * above copyright notice and this permission notice appear in all 7*5113495bSYour Name * copies. 8*5113495bSYour Name * 9*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10*5113495bSYour Name * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11*5113495bSYour Name * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12*5113495bSYour Name * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13*5113495bSYour Name * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14*5113495bSYour Name * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15*5113495bSYour Name * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16*5113495bSYour Name * PERFORMANCE OF THIS SOFTWARE. 17*5113495bSYour Name */ 18*5113495bSYour Name 19*5113495bSYour Name // $ATH_LICENSE_HW_HDR_C$ 20*5113495bSYour Name // 21*5113495bSYour Name // DO NOT EDIT! This file is automatically generated 22*5113495bSYour Name // These definitions are tied to a particular hardware layout 23*5113495bSYour Name 24*5113495bSYour Name 25*5113495bSYour Name #ifndef _PHYRX_PKT_END_H_ 26*5113495bSYour Name #define _PHYRX_PKT_END_H_ 27*5113495bSYour Name #if !defined(__ASSEMBLER__) 28*5113495bSYour Name #endif 29*5113495bSYour Name 30*5113495bSYour Name #include "rx_location_info.h" 31*5113495bSYour Name #include "rx_timing_offset_info.h" 32*5113495bSYour Name #include "receive_rssi_info.h" 33*5113495bSYour Name 34*5113495bSYour Name // ################ START SUMMARY ################# 35*5113495bSYour Name // 36*5113495bSYour Name // Dword Fields 37*5113495bSYour Name // 0 phy_internal_nap[0], location_info_valid[1], timing_info_valid[2], rssi_info_valid[3], rx_frame_correction_needed[4], frameless_frame_received[5], reserved_0a[31:6] 38*5113495bSYour Name // 1 phy_timestamp_1_lower_32[31:0] 39*5113495bSYour Name // 2 phy_timestamp_1_upper_32[31:0] 40*5113495bSYour Name // 3 phy_timestamp_2_lower_32[31:0] 41*5113495bSYour Name // 4 phy_timestamp_2_upper_32[31:0] 42*5113495bSYour Name // 5-13 struct rx_location_info rx_location_info_details; 43*5113495bSYour Name // 14 struct rx_timing_offset_info rx_timing_offset_info_details; 44*5113495bSYour Name // 15-30 struct receive_rssi_info post_rssi_info_details; 45*5113495bSYour Name // 31 phy_sw_status_31_0[31:0] 46*5113495bSYour Name // 32 phy_sw_status_63_32[31:0] 47*5113495bSYour Name // 48*5113495bSYour Name // ################ END SUMMARY ################# 49*5113495bSYour Name 50*5113495bSYour Name #define NUM_OF_DWORDS_PHYRX_PKT_END 33 51*5113495bSYour Name 52*5113495bSYour Name struct phyrx_pkt_end { 53*5113495bSYour Name uint32_t phy_internal_nap : 1, //[0] 54*5113495bSYour Name location_info_valid : 1, //[1] 55*5113495bSYour Name timing_info_valid : 1, //[2] 56*5113495bSYour Name rssi_info_valid : 1, //[3] 57*5113495bSYour Name rx_frame_correction_needed : 1, //[4] 58*5113495bSYour Name frameless_frame_received : 1, //[5] 59*5113495bSYour Name reserved_0a : 26; //[31:6] 60*5113495bSYour Name uint32_t phy_timestamp_1_lower_32 : 32; //[31:0] 61*5113495bSYour Name uint32_t phy_timestamp_1_upper_32 : 32; //[31:0] 62*5113495bSYour Name uint32_t phy_timestamp_2_lower_32 : 32; //[31:0] 63*5113495bSYour Name uint32_t phy_timestamp_2_upper_32 : 32; //[31:0] 64*5113495bSYour Name struct rx_location_info rx_location_info_details; 65*5113495bSYour Name struct rx_timing_offset_info rx_timing_offset_info_details; 66*5113495bSYour Name struct receive_rssi_info post_rssi_info_details; 67*5113495bSYour Name uint32_t phy_sw_status_31_0 : 32; //[31:0] 68*5113495bSYour Name uint32_t phy_sw_status_63_32 : 32; //[31:0] 69*5113495bSYour Name }; 70*5113495bSYour Name 71*5113495bSYour Name /* 72*5113495bSYour Name 73*5113495bSYour Name phy_internal_nap 74*5113495bSYour Name 75*5113495bSYour Name When set, PHY RX entered an internal NAP state, as PHY 76*5113495bSYour Name determined that this reception was not destined to this 77*5113495bSYour Name device 78*5113495bSYour Name 79*5113495bSYour Name location_info_valid 80*5113495bSYour Name 81*5113495bSYour Name Indicates that the RX_LOCATION_INFO structure later on 82*5113495bSYour Name in the TLV contains valid info 83*5113495bSYour Name 84*5113495bSYour Name timing_info_valid 85*5113495bSYour Name 86*5113495bSYour Name Indicates that the RX_TIMING_OFFSET_INFO structure later 87*5113495bSYour Name on in the TLV contains valid info 88*5113495bSYour Name 89*5113495bSYour Name rssi_info_valid 90*5113495bSYour Name 91*5113495bSYour Name Indicates that the RECEIVE_RSSI_INFO structure later on 92*5113495bSYour Name in the TLV contains valid info 93*5113495bSYour Name 94*5113495bSYour Name rx_frame_correction_needed 95*5113495bSYour Name 96*5113495bSYour Name When clear, no action is needed in the MAC. 97*5113495bSYour Name 98*5113495bSYour Name 99*5113495bSYour Name 100*5113495bSYour Name When set, the falling edge of the rx_frame happened 4us 101*5113495bSYour Name too late. MAC will need to compensate for this delay in 102*5113495bSYour Name order to maintain proper SIFS timing and/or not to get 103*5113495bSYour Name de-slotted. 104*5113495bSYour Name 105*5113495bSYour Name 106*5113495bSYour Name 107*5113495bSYour Name PHY uses this for very short 11a frames. 108*5113495bSYour Name 109*5113495bSYour Name 110*5113495bSYour Name 111*5113495bSYour Name When set, PHY will have passed this TLV to the MAC up to 112*5113495bSYour Name 8 us into the 'real SIFS' time, and thus within 4us from the 113*5113495bSYour Name falling edge of the rx_frame. 114*5113495bSYour Name 115*5113495bSYour Name 116*5113495bSYour Name 117*5113495bSYour Name <legal all> 118*5113495bSYour Name 119*5113495bSYour Name frameless_frame_received 120*5113495bSYour Name 121*5113495bSYour Name When set, PHY has received the 'frameless frame' . Can 122*5113495bSYour Name be used in the 'MU-RTS -CTS exchange where CTS reception can 123*5113495bSYour Name be problematic. 124*5113495bSYour Name 125*5113495bSYour Name <legal all> 126*5113495bSYour Name 127*5113495bSYour Name reserved_0a 128*5113495bSYour Name 129*5113495bSYour Name <legal 0> 130*5113495bSYour Name 131*5113495bSYour Name phy_timestamp_1_lower_32 132*5113495bSYour Name 133*5113495bSYour Name TODO PHY-RF team: Is the description for this and the 134*5113495bSYour Name next 3 fields still correct ? 135*5113495bSYour Name 136*5113495bSYour Name 137*5113495bSYour Name 138*5113495bSYour Name The PHY timestamp in the AMPI of the first rising edge 139*5113495bSYour Name of rx_clear_pri after TX_PHY_DESC. . This field should set 140*5113495bSYour Name to 0 by the PHY and should be updated by the AMPI before 141*5113495bSYour Name being forwarded to the rest of the MAC. This field indicates 142*5113495bSYour Name the lower 32 bits of the timestamp 143*5113495bSYour Name 144*5113495bSYour Name phy_timestamp_1_upper_32 145*5113495bSYour Name 146*5113495bSYour Name The PHY timestamp in the AMPI of the first rising edge 147*5113495bSYour Name of rx_clear_pri after TX_PHY_DESC. This field should set to 148*5113495bSYour Name 0 by the PHY and should be updated by the AMPI before being 149*5113495bSYour Name forwarded to the rest of the MAC. This field indicates the 150*5113495bSYour Name upper 32 bits of the timestamp 151*5113495bSYour Name 152*5113495bSYour Name phy_timestamp_2_lower_32 153*5113495bSYour Name 154*5113495bSYour Name The PHY timestamp in the AMPI of the rising edge of 155*5113495bSYour Name rx_clear_pri after RX_RSSI_LEGACY. This field should set to 156*5113495bSYour Name 0 by the PHY and should be updated by the AMPI before being 157*5113495bSYour Name forwarded to the rest of the MAC. This field indicates the 158*5113495bSYour Name lower 32 bits of the timestamp 159*5113495bSYour Name 160*5113495bSYour Name phy_timestamp_2_upper_32 161*5113495bSYour Name 162*5113495bSYour Name The PHY timestamp in the AMPI of the rising edge of 163*5113495bSYour Name rx_clear_pri after RX_RSSI_LEGACY. This field should set to 164*5113495bSYour Name 0 by the PHY and should be updated by the AMPI before being 165*5113495bSYour Name forwarded to the rest of the MAC. This field indicates the 166*5113495bSYour Name upper 32 bits of the timestamp 167*5113495bSYour Name 168*5113495bSYour Name struct rx_location_info rx_location_info_details 169*5113495bSYour Name 170*5113495bSYour Name Overview of location related info 171*5113495bSYour Name 172*5113495bSYour Name struct rx_timing_offset_info rx_timing_offset_info_details 173*5113495bSYour Name 174*5113495bSYour Name Overview of timing offset related info 175*5113495bSYour Name 176*5113495bSYour Name struct receive_rssi_info post_rssi_info_details 177*5113495bSYour Name 178*5113495bSYour Name Overview of the post-RSSI values. 179*5113495bSYour Name 180*5113495bSYour Name phy_sw_status_31_0 181*5113495bSYour Name 182*5113495bSYour Name Some PHY micro code status that can be put in here. 183*5113495bSYour Name Details of definition within SW specification 184*5113495bSYour Name 185*5113495bSYour Name This field can be used for debugging, FW - SW message 186*5113495bSYour Name exchange, etc. 187*5113495bSYour Name 188*5113495bSYour Name It could for example be a pointer to a DDR memory 189*5113495bSYour Name location where PHY FW put some debug info. 190*5113495bSYour Name 191*5113495bSYour Name <legal all> 192*5113495bSYour Name 193*5113495bSYour Name phy_sw_status_63_32 194*5113495bSYour Name 195*5113495bSYour Name Some PHY micro code status that can be put in here. 196*5113495bSYour Name Details of definition within SW specification 197*5113495bSYour Name 198*5113495bSYour Name This field can be used for debugging, FW - SW message 199*5113495bSYour Name exchange, etc. 200*5113495bSYour Name 201*5113495bSYour Name It could for example be a pointer to a DDR memory 202*5113495bSYour Name location where PHY FW put some debug info. 203*5113495bSYour Name 204*5113495bSYour Name <legal all> 205*5113495bSYour Name */ 206*5113495bSYour Name 207*5113495bSYour Name 208*5113495bSYour Name /* Description PHYRX_PKT_END_0_PHY_INTERNAL_NAP 209*5113495bSYour Name 210*5113495bSYour Name When set, PHY RX entered an internal NAP state, as PHY 211*5113495bSYour Name determined that this reception was not destined to this 212*5113495bSYour Name device 213*5113495bSYour Name */ 214*5113495bSYour Name #define PHYRX_PKT_END_0_PHY_INTERNAL_NAP_OFFSET 0x00000000 215*5113495bSYour Name #define PHYRX_PKT_END_0_PHY_INTERNAL_NAP_LSB 0 216*5113495bSYour Name #define PHYRX_PKT_END_0_PHY_INTERNAL_NAP_MASK 0x00000001 217*5113495bSYour Name 218*5113495bSYour Name /* Description PHYRX_PKT_END_0_LOCATION_INFO_VALID 219*5113495bSYour Name 220*5113495bSYour Name Indicates that the RX_LOCATION_INFO structure later on 221*5113495bSYour Name in the TLV contains valid info 222*5113495bSYour Name */ 223*5113495bSYour Name #define PHYRX_PKT_END_0_LOCATION_INFO_VALID_OFFSET 0x00000000 224*5113495bSYour Name #define PHYRX_PKT_END_0_LOCATION_INFO_VALID_LSB 1 225*5113495bSYour Name #define PHYRX_PKT_END_0_LOCATION_INFO_VALID_MASK 0x00000002 226*5113495bSYour Name 227*5113495bSYour Name /* Description PHYRX_PKT_END_0_TIMING_INFO_VALID 228*5113495bSYour Name 229*5113495bSYour Name Indicates that the RX_TIMING_OFFSET_INFO structure later 230*5113495bSYour Name on in the TLV contains valid info 231*5113495bSYour Name */ 232*5113495bSYour Name #define PHYRX_PKT_END_0_TIMING_INFO_VALID_OFFSET 0x00000000 233*5113495bSYour Name #define PHYRX_PKT_END_0_TIMING_INFO_VALID_LSB 2 234*5113495bSYour Name #define PHYRX_PKT_END_0_TIMING_INFO_VALID_MASK 0x00000004 235*5113495bSYour Name 236*5113495bSYour Name /* Description PHYRX_PKT_END_0_RSSI_INFO_VALID 237*5113495bSYour Name 238*5113495bSYour Name Indicates that the RECEIVE_RSSI_INFO structure later on 239*5113495bSYour Name in the TLV contains valid info 240*5113495bSYour Name */ 241*5113495bSYour Name #define PHYRX_PKT_END_0_RSSI_INFO_VALID_OFFSET 0x00000000 242*5113495bSYour Name #define PHYRX_PKT_END_0_RSSI_INFO_VALID_LSB 3 243*5113495bSYour Name #define PHYRX_PKT_END_0_RSSI_INFO_VALID_MASK 0x00000008 244*5113495bSYour Name 245*5113495bSYour Name /* Description PHYRX_PKT_END_0_RX_FRAME_CORRECTION_NEEDED 246*5113495bSYour Name 247*5113495bSYour Name When clear, no action is needed in the MAC. 248*5113495bSYour Name 249*5113495bSYour Name 250*5113495bSYour Name 251*5113495bSYour Name When set, the falling edge of the rx_frame happened 4us 252*5113495bSYour Name too late. MAC will need to compensate for this delay in 253*5113495bSYour Name order to maintain proper SIFS timing and/or not to get 254*5113495bSYour Name de-slotted. 255*5113495bSYour Name 256*5113495bSYour Name 257*5113495bSYour Name 258*5113495bSYour Name PHY uses this for very short 11a frames. 259*5113495bSYour Name 260*5113495bSYour Name 261*5113495bSYour Name 262*5113495bSYour Name When set, PHY will have passed this TLV to the MAC up to 263*5113495bSYour Name 8 us into the 'real SIFS' time, and thus within 4us from the 264*5113495bSYour Name falling edge of the rx_frame. 265*5113495bSYour Name 266*5113495bSYour Name 267*5113495bSYour Name 268*5113495bSYour Name <legal all> 269*5113495bSYour Name */ 270*5113495bSYour Name #define PHYRX_PKT_END_0_RX_FRAME_CORRECTION_NEEDED_OFFSET 0x00000000 271*5113495bSYour Name #define PHYRX_PKT_END_0_RX_FRAME_CORRECTION_NEEDED_LSB 4 272*5113495bSYour Name #define PHYRX_PKT_END_0_RX_FRAME_CORRECTION_NEEDED_MASK 0x00000010 273*5113495bSYour Name 274*5113495bSYour Name /* Description PHYRX_PKT_END_0_FRAMELESS_FRAME_RECEIVED 275*5113495bSYour Name 276*5113495bSYour Name When set, PHY has received the 'frameless frame' . Can 277*5113495bSYour Name be used in the 'MU-RTS -CTS exchange where CTS reception can 278*5113495bSYour Name be problematic. 279*5113495bSYour Name 280*5113495bSYour Name <legal all> 281*5113495bSYour Name */ 282*5113495bSYour Name #define PHYRX_PKT_END_0_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 283*5113495bSYour Name #define PHYRX_PKT_END_0_FRAMELESS_FRAME_RECEIVED_LSB 5 284*5113495bSYour Name #define PHYRX_PKT_END_0_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 285*5113495bSYour Name 286*5113495bSYour Name /* Description PHYRX_PKT_END_0_RESERVED_0A 287*5113495bSYour Name 288*5113495bSYour Name <legal 0> 289*5113495bSYour Name */ 290*5113495bSYour Name #define PHYRX_PKT_END_0_RESERVED_0A_OFFSET 0x00000000 291*5113495bSYour Name #define PHYRX_PKT_END_0_RESERVED_0A_LSB 6 292*5113495bSYour Name #define PHYRX_PKT_END_0_RESERVED_0A_MASK 0xffffffc0 293*5113495bSYour Name 294*5113495bSYour Name /* Description PHYRX_PKT_END_1_PHY_TIMESTAMP_1_LOWER_32 295*5113495bSYour Name 296*5113495bSYour Name TODO PHY-RF team: Is the description for this and the 297*5113495bSYour Name next 3 fields still correct ? 298*5113495bSYour Name 299*5113495bSYour Name 300*5113495bSYour Name 301*5113495bSYour Name The PHY timestamp in the AMPI of the first rising edge 302*5113495bSYour Name of rx_clear_pri after TX_PHY_DESC. . This field should set 303*5113495bSYour Name to 0 by the PHY and should be updated by the AMPI before 304*5113495bSYour Name being forwarded to the rest of the MAC. This field indicates 305*5113495bSYour Name the lower 32 bits of the timestamp 306*5113495bSYour Name */ 307*5113495bSYour Name #define PHYRX_PKT_END_1_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 308*5113495bSYour Name #define PHYRX_PKT_END_1_PHY_TIMESTAMP_1_LOWER_32_LSB 0 309*5113495bSYour Name #define PHYRX_PKT_END_1_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff 310*5113495bSYour Name 311*5113495bSYour Name /* Description PHYRX_PKT_END_2_PHY_TIMESTAMP_1_UPPER_32 312*5113495bSYour Name 313*5113495bSYour Name The PHY timestamp in the AMPI of the first rising edge 314*5113495bSYour Name of rx_clear_pri after TX_PHY_DESC. This field should set to 315*5113495bSYour Name 0 by the PHY and should be updated by the AMPI before being 316*5113495bSYour Name forwarded to the rest of the MAC. This field indicates the 317*5113495bSYour Name upper 32 bits of the timestamp 318*5113495bSYour Name */ 319*5113495bSYour Name #define PHYRX_PKT_END_2_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 320*5113495bSYour Name #define PHYRX_PKT_END_2_PHY_TIMESTAMP_1_UPPER_32_LSB 0 321*5113495bSYour Name #define PHYRX_PKT_END_2_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff 322*5113495bSYour Name 323*5113495bSYour Name /* Description PHYRX_PKT_END_3_PHY_TIMESTAMP_2_LOWER_32 324*5113495bSYour Name 325*5113495bSYour Name The PHY timestamp in the AMPI of the rising edge of 326*5113495bSYour Name rx_clear_pri after RX_RSSI_LEGACY. This field should set to 327*5113495bSYour Name 0 by the PHY and should be updated by the AMPI before being 328*5113495bSYour Name forwarded to the rest of the MAC. This field indicates the 329*5113495bSYour Name lower 32 bits of the timestamp 330*5113495bSYour Name */ 331*5113495bSYour Name #define PHYRX_PKT_END_3_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c 332*5113495bSYour Name #define PHYRX_PKT_END_3_PHY_TIMESTAMP_2_LOWER_32_LSB 0 333*5113495bSYour Name #define PHYRX_PKT_END_3_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff 334*5113495bSYour Name 335*5113495bSYour Name /* Description PHYRX_PKT_END_4_PHY_TIMESTAMP_2_UPPER_32 336*5113495bSYour Name 337*5113495bSYour Name The PHY timestamp in the AMPI of the rising edge of 338*5113495bSYour Name rx_clear_pri after RX_RSSI_LEGACY. This field should set to 339*5113495bSYour Name 0 by the PHY and should be updated by the AMPI before being 340*5113495bSYour Name forwarded to the rest of the MAC. This field indicates the 341*5113495bSYour Name upper 32 bits of the timestamp 342*5113495bSYour Name */ 343*5113495bSYour Name #define PHYRX_PKT_END_4_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 344*5113495bSYour Name #define PHYRX_PKT_END_4_PHY_TIMESTAMP_2_UPPER_32_LSB 0 345*5113495bSYour Name #define PHYRX_PKT_END_4_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff 346*5113495bSYour Name #define PHYRX_PKT_END_5_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000014 347*5113495bSYour Name #define PHYRX_PKT_END_5_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 348*5113495bSYour Name #define PHYRX_PKT_END_5_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 349*5113495bSYour Name #define PHYRX_PKT_END_6_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000018 350*5113495bSYour Name #define PHYRX_PKT_END_6_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 351*5113495bSYour Name #define PHYRX_PKT_END_6_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 352*5113495bSYour Name #define PHYRX_PKT_END_7_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x0000001c 353*5113495bSYour Name #define PHYRX_PKT_END_7_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 354*5113495bSYour Name #define PHYRX_PKT_END_7_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 355*5113495bSYour Name #define PHYRX_PKT_END_8_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000020 356*5113495bSYour Name #define PHYRX_PKT_END_8_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 357*5113495bSYour Name #define PHYRX_PKT_END_8_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 358*5113495bSYour Name #define PHYRX_PKT_END_9_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000024 359*5113495bSYour Name #define PHYRX_PKT_END_9_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 360*5113495bSYour Name #define PHYRX_PKT_END_9_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 361*5113495bSYour Name #define PHYRX_PKT_END_10_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000028 362*5113495bSYour Name #define PHYRX_PKT_END_10_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 363*5113495bSYour Name #define PHYRX_PKT_END_10_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 364*5113495bSYour Name #define PHYRX_PKT_END_11_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x0000002c 365*5113495bSYour Name #define PHYRX_PKT_END_11_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 366*5113495bSYour Name #define PHYRX_PKT_END_11_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 367*5113495bSYour Name #define PHYRX_PKT_END_12_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000030 368*5113495bSYour Name #define PHYRX_PKT_END_12_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 369*5113495bSYour Name #define PHYRX_PKT_END_12_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 370*5113495bSYour Name #define PHYRX_PKT_END_13_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000034 371*5113495bSYour Name #define PHYRX_PKT_END_13_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 372*5113495bSYour Name #define PHYRX_PKT_END_13_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 373*5113495bSYour Name #define PHYRX_PKT_END_14_RX_TIMING_OFFSET_INFO_RX_TIMING_OFFSET_INFO_DETAILS_OFFSET 0x00000038 374*5113495bSYour Name #define PHYRX_PKT_END_14_RX_TIMING_OFFSET_INFO_RX_TIMING_OFFSET_INFO_DETAILS_LSB 0 375*5113495bSYour Name #define PHYRX_PKT_END_14_RX_TIMING_OFFSET_INFO_RX_TIMING_OFFSET_INFO_DETAILS_MASK 0xffffffff 376*5113495bSYour Name #define PHYRX_PKT_END_15_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x0000003c 377*5113495bSYour Name #define PHYRX_PKT_END_15_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 378*5113495bSYour Name #define PHYRX_PKT_END_15_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 379*5113495bSYour Name #define PHYRX_PKT_END_16_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000040 380*5113495bSYour Name #define PHYRX_PKT_END_16_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 381*5113495bSYour Name #define PHYRX_PKT_END_16_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 382*5113495bSYour Name #define PHYRX_PKT_END_17_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000044 383*5113495bSYour Name #define PHYRX_PKT_END_17_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 384*5113495bSYour Name #define PHYRX_PKT_END_17_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 385*5113495bSYour Name #define PHYRX_PKT_END_18_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000048 386*5113495bSYour Name #define PHYRX_PKT_END_18_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 387*5113495bSYour Name #define PHYRX_PKT_END_18_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 388*5113495bSYour Name #define PHYRX_PKT_END_19_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x0000004c 389*5113495bSYour Name #define PHYRX_PKT_END_19_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 390*5113495bSYour Name #define PHYRX_PKT_END_19_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 391*5113495bSYour Name #define PHYRX_PKT_END_20_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000050 392*5113495bSYour Name #define PHYRX_PKT_END_20_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 393*5113495bSYour Name #define PHYRX_PKT_END_20_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 394*5113495bSYour Name #define PHYRX_PKT_END_21_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000054 395*5113495bSYour Name #define PHYRX_PKT_END_21_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 396*5113495bSYour Name #define PHYRX_PKT_END_21_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 397*5113495bSYour Name #define PHYRX_PKT_END_22_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000058 398*5113495bSYour Name #define PHYRX_PKT_END_22_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 399*5113495bSYour Name #define PHYRX_PKT_END_22_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 400*5113495bSYour Name #define PHYRX_PKT_END_23_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x0000005c 401*5113495bSYour Name #define PHYRX_PKT_END_23_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 402*5113495bSYour Name #define PHYRX_PKT_END_23_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 403*5113495bSYour Name #define PHYRX_PKT_END_24_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000060 404*5113495bSYour Name #define PHYRX_PKT_END_24_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 405*5113495bSYour Name #define PHYRX_PKT_END_24_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 406*5113495bSYour Name #define PHYRX_PKT_END_25_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000064 407*5113495bSYour Name #define PHYRX_PKT_END_25_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 408*5113495bSYour Name #define PHYRX_PKT_END_25_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 409*5113495bSYour Name #define PHYRX_PKT_END_26_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000068 410*5113495bSYour Name #define PHYRX_PKT_END_26_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 411*5113495bSYour Name #define PHYRX_PKT_END_26_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 412*5113495bSYour Name #define PHYRX_PKT_END_27_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x0000006c 413*5113495bSYour Name #define PHYRX_PKT_END_27_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 414*5113495bSYour Name #define PHYRX_PKT_END_27_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 415*5113495bSYour Name #define PHYRX_PKT_END_28_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000070 416*5113495bSYour Name #define PHYRX_PKT_END_28_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 417*5113495bSYour Name #define PHYRX_PKT_END_28_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 418*5113495bSYour Name #define PHYRX_PKT_END_29_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000074 419*5113495bSYour Name #define PHYRX_PKT_END_29_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 420*5113495bSYour Name #define PHYRX_PKT_END_29_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 421*5113495bSYour Name #define PHYRX_PKT_END_30_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000078 422*5113495bSYour Name #define PHYRX_PKT_END_30_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 423*5113495bSYour Name #define PHYRX_PKT_END_30_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 424*5113495bSYour Name 425*5113495bSYour Name /* Description PHYRX_PKT_END_31_PHY_SW_STATUS_31_0 426*5113495bSYour Name 427*5113495bSYour Name Some PHY micro code status that can be put in here. 428*5113495bSYour Name Details of definition within SW specification 429*5113495bSYour Name 430*5113495bSYour Name This field can be used for debugging, FW - SW message 431*5113495bSYour Name exchange, etc. 432*5113495bSYour Name 433*5113495bSYour Name It could for example be a pointer to a DDR memory 434*5113495bSYour Name location where PHY FW put some debug info. 435*5113495bSYour Name 436*5113495bSYour Name <legal all> 437*5113495bSYour Name */ 438*5113495bSYour Name #define PHYRX_PKT_END_31_PHY_SW_STATUS_31_0_OFFSET 0x0000007c 439*5113495bSYour Name #define PHYRX_PKT_END_31_PHY_SW_STATUS_31_0_LSB 0 440*5113495bSYour Name #define PHYRX_PKT_END_31_PHY_SW_STATUS_31_0_MASK 0xffffffff 441*5113495bSYour Name 442*5113495bSYour Name /* Description PHYRX_PKT_END_32_PHY_SW_STATUS_63_32 443*5113495bSYour Name 444*5113495bSYour Name Some PHY micro code status that can be put in here. 445*5113495bSYour Name Details of definition within SW specification 446*5113495bSYour Name 447*5113495bSYour Name This field can be used for debugging, FW - SW message 448*5113495bSYour Name exchange, etc. 449*5113495bSYour Name 450*5113495bSYour Name It could for example be a pointer to a DDR memory 451*5113495bSYour Name location where PHY FW put some debug info. 452*5113495bSYour Name 453*5113495bSYour Name <legal all> 454*5113495bSYour Name */ 455*5113495bSYour Name #define PHYRX_PKT_END_32_PHY_SW_STATUS_63_32_OFFSET 0x00000080 456*5113495bSYour Name #define PHYRX_PKT_END_32_PHY_SW_STATUS_63_32_LSB 0 457*5113495bSYour Name #define PHYRX_PKT_END_32_PHY_SW_STATUS_63_32_MASK 0xffffffff 458*5113495bSYour Name 459*5113495bSYour Name 460*5113495bSYour Name #endif // _PHYRX_PKT_END_H_ 461