1 /* 2 * Copyright (c) 2018 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // $ATH_LICENSE_HW_HDR_C$ 20 // 21 // DO NOT EDIT! This file is automatically generated 22 // These definitions are tied to a particular hardware layout 23 24 25 #ifndef _PHYRX_PKT_END_H_ 26 #define _PHYRX_PKT_END_H_ 27 #if !defined(__ASSEMBLER__) 28 #endif 29 30 #include "rx_location_info.h" 31 #include "rx_timing_offset_info.h" 32 #include "receive_rssi_info.h" 33 34 // ################ START SUMMARY ################# 35 // 36 // Dword Fields 37 // 0 phy_internal_nap[0], location_info_valid[1], timing_info_valid[2], rssi_info_valid[3], rx_frame_correction_needed[4], frameless_frame_received[5], reserved_0a[31:6] 38 // 1 phy_timestamp_1_lower_32[31:0] 39 // 2 phy_timestamp_1_upper_32[31:0] 40 // 3 phy_timestamp_2_lower_32[31:0] 41 // 4 phy_timestamp_2_upper_32[31:0] 42 // 5-13 struct rx_location_info rx_location_info_details; 43 // 14 struct rx_timing_offset_info rx_timing_offset_info_details; 44 // 15-30 struct receive_rssi_info post_rssi_info_details; 45 // 31 phy_sw_status_31_0[31:0] 46 // 32 phy_sw_status_63_32[31:0] 47 // 48 // ################ END SUMMARY ################# 49 50 #define NUM_OF_DWORDS_PHYRX_PKT_END 33 51 52 struct phyrx_pkt_end { 53 uint32_t phy_internal_nap : 1, //[0] 54 location_info_valid : 1, //[1] 55 timing_info_valid : 1, //[2] 56 rssi_info_valid : 1, //[3] 57 rx_frame_correction_needed : 1, //[4] 58 frameless_frame_received : 1, //[5] 59 reserved_0a : 26; //[31:6] 60 uint32_t phy_timestamp_1_lower_32 : 32; //[31:0] 61 uint32_t phy_timestamp_1_upper_32 : 32; //[31:0] 62 uint32_t phy_timestamp_2_lower_32 : 32; //[31:0] 63 uint32_t phy_timestamp_2_upper_32 : 32; //[31:0] 64 struct rx_location_info rx_location_info_details; 65 struct rx_timing_offset_info rx_timing_offset_info_details; 66 struct receive_rssi_info post_rssi_info_details; 67 uint32_t phy_sw_status_31_0 : 32; //[31:0] 68 uint32_t phy_sw_status_63_32 : 32; //[31:0] 69 }; 70 71 /* 72 73 phy_internal_nap 74 75 When set, PHY RX entered an internal NAP state, as PHY 76 determined that this reception was not destined to this 77 device 78 79 location_info_valid 80 81 Indicates that the RX_LOCATION_INFO structure later on 82 in the TLV contains valid info 83 84 timing_info_valid 85 86 Indicates that the RX_TIMING_OFFSET_INFO structure later 87 on in the TLV contains valid info 88 89 rssi_info_valid 90 91 Indicates that the RECEIVE_RSSI_INFO structure later on 92 in the TLV contains valid info 93 94 rx_frame_correction_needed 95 96 When clear, no action is needed in the MAC. 97 98 99 100 When set, the falling edge of the rx_frame happened 4us 101 too late. MAC will need to compensate for this delay in 102 order to maintain proper SIFS timing and/or not to get 103 de-slotted. 104 105 106 107 PHY uses this for very short 11a frames. 108 109 110 111 When set, PHY will have passed this TLV to the MAC up to 112 8 us into the 'real SIFS' time, and thus within 4us from the 113 falling edge of the rx_frame. 114 115 116 117 <legal all> 118 119 frameless_frame_received 120 121 When set, PHY has received the 'frameless frame' . Can 122 be used in the 'MU-RTS -CTS exchange where CTS reception can 123 be problematic. 124 125 <legal all> 126 127 reserved_0a 128 129 <legal 0> 130 131 phy_timestamp_1_lower_32 132 133 TODO PHY-RF team: Is the description for this and the 134 next 3 fields still correct ? 135 136 137 138 The PHY timestamp in the AMPI of the first rising edge 139 of rx_clear_pri after TX_PHY_DESC. . This field should set 140 to 0 by the PHY and should be updated by the AMPI before 141 being forwarded to the rest of the MAC. This field indicates 142 the lower 32 bits of the timestamp 143 144 phy_timestamp_1_upper_32 145 146 The PHY timestamp in the AMPI of the first rising edge 147 of rx_clear_pri after TX_PHY_DESC. This field should set to 148 0 by the PHY and should be updated by the AMPI before being 149 forwarded to the rest of the MAC. This field indicates the 150 upper 32 bits of the timestamp 151 152 phy_timestamp_2_lower_32 153 154 The PHY timestamp in the AMPI of the rising edge of 155 rx_clear_pri after RX_RSSI_LEGACY. This field should set to 156 0 by the PHY and should be updated by the AMPI before being 157 forwarded to the rest of the MAC. This field indicates the 158 lower 32 bits of the timestamp 159 160 phy_timestamp_2_upper_32 161 162 The PHY timestamp in the AMPI of the rising edge of 163 rx_clear_pri after RX_RSSI_LEGACY. This field should set to 164 0 by the PHY and should be updated by the AMPI before being 165 forwarded to the rest of the MAC. This field indicates the 166 upper 32 bits of the timestamp 167 168 struct rx_location_info rx_location_info_details 169 170 Overview of location related info 171 172 struct rx_timing_offset_info rx_timing_offset_info_details 173 174 Overview of timing offset related info 175 176 struct receive_rssi_info post_rssi_info_details 177 178 Overview of the post-RSSI values. 179 180 phy_sw_status_31_0 181 182 Some PHY micro code status that can be put in here. 183 Details of definition within SW specification 184 185 This field can be used for debugging, FW - SW message 186 exchange, etc. 187 188 It could for example be a pointer to a DDR memory 189 location where PHY FW put some debug info. 190 191 <legal all> 192 193 phy_sw_status_63_32 194 195 Some PHY micro code status that can be put in here. 196 Details of definition within SW specification 197 198 This field can be used for debugging, FW - SW message 199 exchange, etc. 200 201 It could for example be a pointer to a DDR memory 202 location where PHY FW put some debug info. 203 204 <legal all> 205 */ 206 207 208 /* Description PHYRX_PKT_END_0_PHY_INTERNAL_NAP 209 210 When set, PHY RX entered an internal NAP state, as PHY 211 determined that this reception was not destined to this 212 device 213 */ 214 #define PHYRX_PKT_END_0_PHY_INTERNAL_NAP_OFFSET 0x00000000 215 #define PHYRX_PKT_END_0_PHY_INTERNAL_NAP_LSB 0 216 #define PHYRX_PKT_END_0_PHY_INTERNAL_NAP_MASK 0x00000001 217 218 /* Description PHYRX_PKT_END_0_LOCATION_INFO_VALID 219 220 Indicates that the RX_LOCATION_INFO structure later on 221 in the TLV contains valid info 222 */ 223 #define PHYRX_PKT_END_0_LOCATION_INFO_VALID_OFFSET 0x00000000 224 #define PHYRX_PKT_END_0_LOCATION_INFO_VALID_LSB 1 225 #define PHYRX_PKT_END_0_LOCATION_INFO_VALID_MASK 0x00000002 226 227 /* Description PHYRX_PKT_END_0_TIMING_INFO_VALID 228 229 Indicates that the RX_TIMING_OFFSET_INFO structure later 230 on in the TLV contains valid info 231 */ 232 #define PHYRX_PKT_END_0_TIMING_INFO_VALID_OFFSET 0x00000000 233 #define PHYRX_PKT_END_0_TIMING_INFO_VALID_LSB 2 234 #define PHYRX_PKT_END_0_TIMING_INFO_VALID_MASK 0x00000004 235 236 /* Description PHYRX_PKT_END_0_RSSI_INFO_VALID 237 238 Indicates that the RECEIVE_RSSI_INFO structure later on 239 in the TLV contains valid info 240 */ 241 #define PHYRX_PKT_END_0_RSSI_INFO_VALID_OFFSET 0x00000000 242 #define PHYRX_PKT_END_0_RSSI_INFO_VALID_LSB 3 243 #define PHYRX_PKT_END_0_RSSI_INFO_VALID_MASK 0x00000008 244 245 /* Description PHYRX_PKT_END_0_RX_FRAME_CORRECTION_NEEDED 246 247 When clear, no action is needed in the MAC. 248 249 250 251 When set, the falling edge of the rx_frame happened 4us 252 too late. MAC will need to compensate for this delay in 253 order to maintain proper SIFS timing and/or not to get 254 de-slotted. 255 256 257 258 PHY uses this for very short 11a frames. 259 260 261 262 When set, PHY will have passed this TLV to the MAC up to 263 8 us into the 'real SIFS' time, and thus within 4us from the 264 falling edge of the rx_frame. 265 266 267 268 <legal all> 269 */ 270 #define PHYRX_PKT_END_0_RX_FRAME_CORRECTION_NEEDED_OFFSET 0x00000000 271 #define PHYRX_PKT_END_0_RX_FRAME_CORRECTION_NEEDED_LSB 4 272 #define PHYRX_PKT_END_0_RX_FRAME_CORRECTION_NEEDED_MASK 0x00000010 273 274 /* Description PHYRX_PKT_END_0_FRAMELESS_FRAME_RECEIVED 275 276 When set, PHY has received the 'frameless frame' . Can 277 be used in the 'MU-RTS -CTS exchange where CTS reception can 278 be problematic. 279 280 <legal all> 281 */ 282 #define PHYRX_PKT_END_0_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 283 #define PHYRX_PKT_END_0_FRAMELESS_FRAME_RECEIVED_LSB 5 284 #define PHYRX_PKT_END_0_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 285 286 /* Description PHYRX_PKT_END_0_RESERVED_0A 287 288 <legal 0> 289 */ 290 #define PHYRX_PKT_END_0_RESERVED_0A_OFFSET 0x00000000 291 #define PHYRX_PKT_END_0_RESERVED_0A_LSB 6 292 #define PHYRX_PKT_END_0_RESERVED_0A_MASK 0xffffffc0 293 294 /* Description PHYRX_PKT_END_1_PHY_TIMESTAMP_1_LOWER_32 295 296 TODO PHY-RF team: Is the description for this and the 297 next 3 fields still correct ? 298 299 300 301 The PHY timestamp in the AMPI of the first rising edge 302 of rx_clear_pri after TX_PHY_DESC. . This field should set 303 to 0 by the PHY and should be updated by the AMPI before 304 being forwarded to the rest of the MAC. This field indicates 305 the lower 32 bits of the timestamp 306 */ 307 #define PHYRX_PKT_END_1_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 308 #define PHYRX_PKT_END_1_PHY_TIMESTAMP_1_LOWER_32_LSB 0 309 #define PHYRX_PKT_END_1_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff 310 311 /* Description PHYRX_PKT_END_2_PHY_TIMESTAMP_1_UPPER_32 312 313 The PHY timestamp in the AMPI of the first rising edge 314 of rx_clear_pri after TX_PHY_DESC. This field should set to 315 0 by the PHY and should be updated by the AMPI before being 316 forwarded to the rest of the MAC. This field indicates the 317 upper 32 bits of the timestamp 318 */ 319 #define PHYRX_PKT_END_2_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 320 #define PHYRX_PKT_END_2_PHY_TIMESTAMP_1_UPPER_32_LSB 0 321 #define PHYRX_PKT_END_2_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff 322 323 /* Description PHYRX_PKT_END_3_PHY_TIMESTAMP_2_LOWER_32 324 325 The PHY timestamp in the AMPI of the rising edge of 326 rx_clear_pri after RX_RSSI_LEGACY. This field should set to 327 0 by the PHY and should be updated by the AMPI before being 328 forwarded to the rest of the MAC. This field indicates the 329 lower 32 bits of the timestamp 330 */ 331 #define PHYRX_PKT_END_3_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c 332 #define PHYRX_PKT_END_3_PHY_TIMESTAMP_2_LOWER_32_LSB 0 333 #define PHYRX_PKT_END_3_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff 334 335 /* Description PHYRX_PKT_END_4_PHY_TIMESTAMP_2_UPPER_32 336 337 The PHY timestamp in the AMPI of the rising edge of 338 rx_clear_pri after RX_RSSI_LEGACY. This field should set to 339 0 by the PHY and should be updated by the AMPI before being 340 forwarded to the rest of the MAC. This field indicates the 341 upper 32 bits of the timestamp 342 */ 343 #define PHYRX_PKT_END_4_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 344 #define PHYRX_PKT_END_4_PHY_TIMESTAMP_2_UPPER_32_LSB 0 345 #define PHYRX_PKT_END_4_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff 346 #define PHYRX_PKT_END_5_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000014 347 #define PHYRX_PKT_END_5_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 348 #define PHYRX_PKT_END_5_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 349 #define PHYRX_PKT_END_6_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000018 350 #define PHYRX_PKT_END_6_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 351 #define PHYRX_PKT_END_6_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 352 #define PHYRX_PKT_END_7_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x0000001c 353 #define PHYRX_PKT_END_7_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 354 #define PHYRX_PKT_END_7_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 355 #define PHYRX_PKT_END_8_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000020 356 #define PHYRX_PKT_END_8_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 357 #define PHYRX_PKT_END_8_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 358 #define PHYRX_PKT_END_9_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000024 359 #define PHYRX_PKT_END_9_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 360 #define PHYRX_PKT_END_9_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 361 #define PHYRX_PKT_END_10_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000028 362 #define PHYRX_PKT_END_10_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 363 #define PHYRX_PKT_END_10_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 364 #define PHYRX_PKT_END_11_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x0000002c 365 #define PHYRX_PKT_END_11_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 366 #define PHYRX_PKT_END_11_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 367 #define PHYRX_PKT_END_12_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000030 368 #define PHYRX_PKT_END_12_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 369 #define PHYRX_PKT_END_12_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 370 #define PHYRX_PKT_END_13_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_OFFSET 0x00000034 371 #define PHYRX_PKT_END_13_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_LSB 0 372 #define PHYRX_PKT_END_13_RX_LOCATION_INFO_RX_LOCATION_INFO_DETAILS_MASK 0xffffffff 373 #define PHYRX_PKT_END_14_RX_TIMING_OFFSET_INFO_RX_TIMING_OFFSET_INFO_DETAILS_OFFSET 0x00000038 374 #define PHYRX_PKT_END_14_RX_TIMING_OFFSET_INFO_RX_TIMING_OFFSET_INFO_DETAILS_LSB 0 375 #define PHYRX_PKT_END_14_RX_TIMING_OFFSET_INFO_RX_TIMING_OFFSET_INFO_DETAILS_MASK 0xffffffff 376 #define PHYRX_PKT_END_15_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x0000003c 377 #define PHYRX_PKT_END_15_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 378 #define PHYRX_PKT_END_15_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 379 #define PHYRX_PKT_END_16_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000040 380 #define PHYRX_PKT_END_16_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 381 #define PHYRX_PKT_END_16_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 382 #define PHYRX_PKT_END_17_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000044 383 #define PHYRX_PKT_END_17_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 384 #define PHYRX_PKT_END_17_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 385 #define PHYRX_PKT_END_18_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000048 386 #define PHYRX_PKT_END_18_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 387 #define PHYRX_PKT_END_18_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 388 #define PHYRX_PKT_END_19_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x0000004c 389 #define PHYRX_PKT_END_19_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 390 #define PHYRX_PKT_END_19_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 391 #define PHYRX_PKT_END_20_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000050 392 #define PHYRX_PKT_END_20_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 393 #define PHYRX_PKT_END_20_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 394 #define PHYRX_PKT_END_21_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000054 395 #define PHYRX_PKT_END_21_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 396 #define PHYRX_PKT_END_21_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 397 #define PHYRX_PKT_END_22_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000058 398 #define PHYRX_PKT_END_22_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 399 #define PHYRX_PKT_END_22_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 400 #define PHYRX_PKT_END_23_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x0000005c 401 #define PHYRX_PKT_END_23_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 402 #define PHYRX_PKT_END_23_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 403 #define PHYRX_PKT_END_24_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000060 404 #define PHYRX_PKT_END_24_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 405 #define PHYRX_PKT_END_24_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 406 #define PHYRX_PKT_END_25_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000064 407 #define PHYRX_PKT_END_25_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 408 #define PHYRX_PKT_END_25_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 409 #define PHYRX_PKT_END_26_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000068 410 #define PHYRX_PKT_END_26_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 411 #define PHYRX_PKT_END_26_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 412 #define PHYRX_PKT_END_27_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x0000006c 413 #define PHYRX_PKT_END_27_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 414 #define PHYRX_PKT_END_27_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 415 #define PHYRX_PKT_END_28_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000070 416 #define PHYRX_PKT_END_28_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 417 #define PHYRX_PKT_END_28_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 418 #define PHYRX_PKT_END_29_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000074 419 #define PHYRX_PKT_END_29_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 420 #define PHYRX_PKT_END_29_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 421 #define PHYRX_PKT_END_30_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_OFFSET 0x00000078 422 #define PHYRX_PKT_END_30_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_LSB 0 423 #define PHYRX_PKT_END_30_RECEIVE_RSSI_INFO_POST_RSSI_INFO_DETAILS_MASK 0xffffffff 424 425 /* Description PHYRX_PKT_END_31_PHY_SW_STATUS_31_0 426 427 Some PHY micro code status that can be put in here. 428 Details of definition within SW specification 429 430 This field can be used for debugging, FW - SW message 431 exchange, etc. 432 433 It could for example be a pointer to a DDR memory 434 location where PHY FW put some debug info. 435 436 <legal all> 437 */ 438 #define PHYRX_PKT_END_31_PHY_SW_STATUS_31_0_OFFSET 0x0000007c 439 #define PHYRX_PKT_END_31_PHY_SW_STATUS_31_0_LSB 0 440 #define PHYRX_PKT_END_31_PHY_SW_STATUS_31_0_MASK 0xffffffff 441 442 /* Description PHYRX_PKT_END_32_PHY_SW_STATUS_63_32 443 444 Some PHY micro code status that can be put in here. 445 Details of definition within SW specification 446 447 This field can be used for debugging, FW - SW message 448 exchange, etc. 449 450 It could for example be a pointer to a DDR memory 451 location where PHY FW put some debug info. 452 453 <legal all> 454 */ 455 #define PHYRX_PKT_END_32_PHY_SW_STATUS_63_32_OFFSET 0x00000080 456 #define PHYRX_PKT_END_32_PHY_SW_STATUS_63_32_LSB 0 457 #define PHYRX_PKT_END_32_PHY_SW_STATUS_63_32_MASK 0xffffffff 458 459 460 #endif // _PHYRX_PKT_END_H_ 461