1 /* 2 * Copyright (c) 2016 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // $ATH_LICENSE_HW_HDR_C$ 20 // 21 // DO NOT EDIT! This file is automatically generated 22 // These definitions are tied to a particular hardware layout 23 24 25 #ifndef _REO_DESTINATION_RING_H_ 26 #define _REO_DESTINATION_RING_H_ 27 #if !defined(__ASSEMBLER__) 28 #endif 29 30 #include "buffer_addr_info.h" 31 #include "rx_mpdu_desc_info.h" 32 #include "rx_msdu_desc_info.h" 33 34 // ################ START SUMMARY ################# 35 // 36 // Dword Fields 37 // 0-1 struct buffer_addr_info buf_or_link_desc_addr_info; 38 // 2-3 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 39 // 4-5 struct rx_msdu_desc_info rx_msdu_desc_info_details; 40 // 6 rx_reo_queue_desc_addr_31_0[31:0] 41 // 7 rx_reo_queue_desc_addr_39_32[7:0], reo_dest_buffer_type[8], reo_push_reason[10:9], reo_error_code[15:11], receive_queue_number[31:16] 42 // 8 soft_reorder_info_valid[0], reorder_opcode[4:1], reorder_slot_index[12:5], reserved_8a[31:13] 43 // 9 reserved_9a[31:0] 44 // 10 reserved_10a[31:0] 45 // 11 reserved_11a[31:0] 46 // 12 reserved_12a[31:0] 47 // 13 reserved_13a[31:0] 48 // 14 reserved_14a[31:0] 49 // 15 reserved_15[19:0], ring_id[27:20], looping_count[31:28] 50 // 51 // ################ END SUMMARY ################# 52 53 #define NUM_OF_DWORDS_REO_DESTINATION_RING 16 54 55 struct reo_destination_ring { 56 struct buffer_addr_info buf_or_link_desc_addr_info; 57 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 58 struct rx_msdu_desc_info rx_msdu_desc_info_details; 59 uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] 60 uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] 61 reo_dest_buffer_type : 1, //[8] 62 reo_push_reason : 2, //[10:9] 63 reo_error_code : 5, //[15:11] 64 receive_queue_number : 16; //[31:16] 65 uint32_t soft_reorder_info_valid : 1, //[0] 66 reorder_opcode : 4, //[4:1] 67 reorder_slot_index : 8, //[12:5] 68 reserved_8a : 19; //[31:13] 69 uint32_t reserved_9a : 32; //[31:0] 70 uint32_t reserved_10a : 32; //[31:0] 71 uint32_t reserved_11a : 32; //[31:0] 72 uint32_t reserved_12a : 32; //[31:0] 73 uint32_t reserved_13a : 32; //[31:0] 74 uint32_t reserved_14a : 32; //[31:0] 75 uint32_t reserved_15 : 20, //[19:0] 76 ring_id : 8, //[27:20] 77 looping_count : 4; //[31:28] 78 }; 79 80 /* 81 82 struct buffer_addr_info buf_or_link_desc_addr_info 83 84 Consumer: REO/SW/FW 85 86 Producer: RXDMA 87 88 89 90 Details of the physical address of the a buffer or MSDU 91 link descriptor 92 93 struct rx_mpdu_desc_info rx_mpdu_desc_info_details 94 95 Consumer: REO/SW/FW 96 97 Producer: RXDMA 98 99 100 101 General information related to the MPDU that is passed 102 on from REO entrance ring to the REO destination ring 103 104 struct rx_msdu_desc_info rx_msdu_desc_info_details 105 106 General information related to the MSDU that is passed 107 on from RXDMA all the way to to the REO destination ring. 108 109 rx_reo_queue_desc_addr_31_0 110 111 Consumer: REO 112 113 Producer: RXDMA 114 115 116 117 Address (lower 32 bits) of the REO queue descriptor. 118 119 <legal all> 120 121 rx_reo_queue_desc_addr_39_32 122 123 Consumer: REO 124 125 Producer: RXDMA 126 127 128 129 Address (upper 8 bits) of the REO queue descriptor. 130 131 <legal all> 132 133 reo_dest_buffer_type 134 135 Indicates the type of address provided in the 136 'Buf_or_link_desc_addr_info' 137 138 139 140 <enum 0 MSDU_buf_address> The address of an MSDU buffer 141 142 <enum 1 MSDU_link_desc_address> The address of the MSDU 143 link descriptor. 144 145 146 147 <legal all> 148 149 reo_push_reason 150 151 Indicates why REO pushed the frame to this exit ring 152 153 154 155 <enum 0 reo_error_detected> Reo detected an error an 156 pushed this frame to this queue 157 158 <enum 1 reo_routing_instruction> Reo pushed the frame to 159 this queue per received routing instructions. No error 160 within REO was detected 161 162 163 164 165 166 <legal 0 - 1> 167 168 reo_error_code 169 170 Field only valid when 'Reo_push_reason' set to 171 'reo_error_detected'. 172 173 174 175 <enum 0 reo_queue_desc_addr_zero> Reo queue descriptor 176 provided in the REO_ENTRANCE ring is set to 0 177 178 <enum 1 reo_queue_desc_not_valid> Reo queue descriptor 179 valid bit is NOT set 180 181 <enum 2 ampdu_in_non_ba> AMPDU frame received without BA 182 session having been setup. 183 184 <enum 3 non_ba_duplicate> Non-BA session, SN equal to 185 SSN, Retry bit set: duplicate frame 186 187 <enum 4 ba_duplicate> BA session, duplicate frame 188 189 <enum 5 regular_frame_2k_jump> A normal (management/data 190 frame) received with 2K jump in SN 191 192 <enum 6 bar_frame_2k_jump> A bar received with 2K jump 193 in SSN 194 195 <enum 7 regular_frame_OOR> A normal (management/data 196 frame) received with SN falling within the OOR window 197 198 <enum 8 bar_frame_OOR> A bar received with SSN falling 199 within the OOR window 200 201 <enum 9 bar_frame_no_ba_session> A bar received without 202 a BA session 203 204 <enum 10 bar_frame_sn_equals_ssn> A bar received with 205 SSN equal to SN 206 207 <enum 11 pn_check_failed> PN Check Failed packet. 208 209 <enum 12 2k_error_handling_flag_set> Frame is forwarded 210 as a result of the 'Seq_2k_error_detected_flag' been set in 211 the REO Queue descriptor 212 213 <enum 13 pn_error_handling_flag_set> Frame is forwarded 214 as a result of the 'pn_error_detected_flag' been set in the 215 REO Queue descriptor 216 217 <enum 14 queue_descriptor_blocked_set> Frame is 218 forwarded as a result of the queue descriptor(address) being 219 blocked as SW/FW seems to be currently in the process of 220 making updates to this descriptor... 221 222 223 224 <legal 0-14> 225 226 receive_queue_number 227 228 This field indicates the REO MPDU reorder queue ID from 229 which this frame originated. This field is populated from a 230 field with the same name in the RX_REO_QUEUE descriptor. 231 232 <legal all> 233 234 soft_reorder_info_valid 235 236 When set, REO has been instructed to not perform the 237 actual re-ordering of frames for this queue, but just to 238 insert the reorder opcodes 239 240 <legal all> 241 242 reorder_opcode 243 244 Field is valid when 'Soft_reorder_info_valid' is set. 245 This field is always valid for debug purpose as well. 246 247 Details are in the MLD. 248 249 250 251 <enum 0 invalid> 252 253 <enum 1 fwdcur_fwdbuf> 254 255 <enum 2 fwdbuf_fwdcur> 256 257 <enum 3 qcur> 258 259 <enum 4 fwdbuf_qcur> 260 261 <enum 5 fwdbuf_drop> 262 263 <enum 6 fwdall_drop> 264 265 <enum 7 fwdall_qcur> 266 267 <enum 8 reserved_reo_opcode_1> 268 269 <enum 9 dropcur> the error reason code is in 270 reo_error_code field. 271 272 <enum 10 reserved_reo_opcode_2> 273 274 <enum 11 reserved_reo_opcode_3> 275 276 <enum 12 reserved_reo_opcode_4> 277 278 <enum 13 reserved_reo_opcode_5> 279 280 <enum 14 reserved_reo_opcode_6> 281 282 <enum 15 reserved_reo_opcode_7> 283 284 285 286 <legal all> 287 288 reorder_slot_index 289 290 Field only valid when 'Soft_reorder_info_valid' is set. 291 292 293 294 TODO: add description 295 296 297 298 <legal all> 299 300 reserved_8a 301 302 <legal 0> 303 304 reserved_9a 305 306 <legal 0> 307 308 reserved_10a 309 310 <legal 0> 311 312 reserved_11a 313 314 <legal 0> 315 316 reserved_12a 317 318 <legal 0> 319 320 reserved_13a 321 322 <legal 0> 323 324 reserved_14a 325 326 <legal 0> 327 328 reserved_15 329 330 <legal 0> 331 332 ring_id 333 334 The buffer pointer ring ID. 335 336 0 refers to the IDLE ring 337 338 1 - N refers to other rings 339 340 341 342 Helps with debugging when dumping ring contents. 343 344 <legal all> 345 346 looping_count 347 348 A count value that indicates the number of times the 349 producer of entries into this Ring has looped around the 350 ring. 351 352 At initialization time, this value is set to 0. On the 353 first loop, this value is set to 1. After the max value is 354 reached allowed by the number of bits for this field, the 355 count value continues with 0 again. 356 357 In case SW is the consumer of the ring entries, it can 358 use this field to figure out up to where the producer of 359 entries has created new entries. This eliminates the need to 360 check where the head pointer' of the ring is located once 361 the SW starts processing an interrupt indicating that new 362 entries have been put into this ring... 363 364 365 366 Also note that SW if it wants only needs to look at the 367 LSB bit of this count value. 368 369 <legal all> 370 */ 371 372 #define REO_DESTINATION_RING_0_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_OFFSET 0x00000000 373 #define REO_DESTINATION_RING_0_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_LSB 28 374 #define REO_DESTINATION_RING_0_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_MASK 0xffffffff 375 #define REO_DESTINATION_RING_1_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_OFFSET 0x00000004 376 #define REO_DESTINATION_RING_1_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_LSB 28 377 #define REO_DESTINATION_RING_1_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_MASK 0xffffffff 378 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 0x00000008 379 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_LSB 28 380 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_MASK 0xffffffff 381 #define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 0x0000000c 382 #define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_LSB 28 383 #define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_MASK 0xffffffff 384 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 0x00000010 385 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_LSB 28 386 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_MASK 0xffffffff 387 #define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 0x00000014 388 #define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_LSB 28 389 #define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_MASK 0xffffffff 390 391 /* Description REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0 392 393 Consumer: REO 394 395 Producer: RXDMA 396 397 398 399 Address (lower 32 bits) of the REO queue descriptor. 400 401 <legal all> 402 */ 403 #define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000018 404 #define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 405 #define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 406 407 /* Description REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32 408 409 Consumer: REO 410 411 Producer: RXDMA 412 413 414 415 Address (upper 8 bits) of the REO queue descriptor. 416 417 <legal all> 418 */ 419 #define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000001c 420 #define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 421 #define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 422 423 /* Description REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE 424 425 Indicates the type of address provided in the 426 'Buf_or_link_desc_addr_info' 427 428 429 430 <enum 0 MSDU_buf_address> The address of an MSDU buffer 431 432 <enum 1 MSDU_link_desc_address> The address of the MSDU 433 link descriptor. 434 435 436 437 <legal all> 438 */ 439 #define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c 440 #define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB 8 441 #define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK 0x00000100 442 443 /* Description REO_DESTINATION_RING_7_REO_PUSH_REASON 444 445 Indicates why REO pushed the frame to this exit ring 446 447 448 449 <enum 0 reo_error_detected> Reo detected an error an 450 pushed this frame to this queue 451 452 <enum 1 reo_routing_instruction> Reo pushed the frame to 453 this queue per received routing instructions. No error 454 within REO was detected 455 456 457 458 459 460 <legal 0 - 1> 461 */ 462 #define REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET 0x0000001c 463 #define REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB 9 464 #define REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK 0x00000600 465 466 /* Description REO_DESTINATION_RING_7_REO_ERROR_CODE 467 468 Field only valid when 'Reo_push_reason' set to 469 'reo_error_detected'. 470 471 472 473 <enum 0 reo_queue_desc_addr_zero> Reo queue descriptor 474 provided in the REO_ENTRANCE ring is set to 0 475 476 <enum 1 reo_queue_desc_not_valid> Reo queue descriptor 477 valid bit is NOT set 478 479 <enum 2 ampdu_in_non_ba> AMPDU frame received without BA 480 session having been setup. 481 482 <enum 3 non_ba_duplicate> Non-BA session, SN equal to 483 SSN, Retry bit set: duplicate frame 484 485 <enum 4 ba_duplicate> BA session, duplicate frame 486 487 <enum 5 regular_frame_2k_jump> A normal (management/data 488 frame) received with 2K jump in SN 489 490 <enum 6 bar_frame_2k_jump> A bar received with 2K jump 491 in SSN 492 493 <enum 7 regular_frame_OOR> A normal (management/data 494 frame) received with SN falling within the OOR window 495 496 <enum 8 bar_frame_OOR> A bar received with SSN falling 497 within the OOR window 498 499 <enum 9 bar_frame_no_ba_session> A bar received without 500 a BA session 501 502 <enum 10 bar_frame_sn_equals_ssn> A bar received with 503 SSN equal to SN 504 505 <enum 11 pn_check_failed> PN Check Failed packet. 506 507 <enum 12 2k_error_handling_flag_set> Frame is forwarded 508 as a result of the 'Seq_2k_error_detected_flag' been set in 509 the REO Queue descriptor 510 511 <enum 13 pn_error_handling_flag_set> Frame is forwarded 512 as a result of the 'pn_error_detected_flag' been set in the 513 REO Queue descriptor 514 515 <enum 14 queue_descriptor_blocked_set> Frame is 516 forwarded as a result of the queue descriptor(address) being 517 blocked as SW/FW seems to be currently in the process of 518 making updates to this descriptor... 519 520 521 522 <legal 0-14> 523 */ 524 #define REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET 0x0000001c 525 #define REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB 11 526 #define REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK 0x0000f800 527 528 /* Description REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER 529 530 This field indicates the REO MPDU reorder queue ID from 531 which this frame originated. This field is populated from a 532 field with the same name in the RX_REO_QUEUE descriptor. 533 534 <legal all> 535 */ 536 #define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000001c 537 #define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_LSB 16 538 #define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_MASK 0xffff0000 539 540 /* Description REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID 541 542 When set, REO has been instructed to not perform the 543 actual re-ordering of frames for this queue, but just to 544 insert the reorder opcodes 545 546 <legal all> 547 */ 548 #define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_OFFSET 0x00000020 549 #define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_LSB 0 550 #define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_MASK 0x00000001 551 552 /* Description REO_DESTINATION_RING_8_REORDER_OPCODE 553 554 Field is valid when 'Soft_reorder_info_valid' is set. 555 This field is always valid for debug purpose as well. 556 557 Details are in the MLD. 558 559 560 561 <enum 0 invalid> 562 563 <enum 1 fwdcur_fwdbuf> 564 565 <enum 2 fwdbuf_fwdcur> 566 567 <enum 3 qcur> 568 569 <enum 4 fwdbuf_qcur> 570 571 <enum 5 fwdbuf_drop> 572 573 <enum 6 fwdall_drop> 574 575 <enum 7 fwdall_qcur> 576 577 <enum 8 reserved_reo_opcode_1> 578 579 <enum 9 dropcur> the error reason code is in 580 reo_error_code field. 581 582 <enum 10 reserved_reo_opcode_2> 583 584 <enum 11 reserved_reo_opcode_3> 585 586 <enum 12 reserved_reo_opcode_4> 587 588 <enum 13 reserved_reo_opcode_5> 589 590 <enum 14 reserved_reo_opcode_6> 591 592 <enum 15 reserved_reo_opcode_7> 593 594 595 596 <legal all> 597 */ 598 #define REO_DESTINATION_RING_8_REORDER_OPCODE_OFFSET 0x00000020 599 #define REO_DESTINATION_RING_8_REORDER_OPCODE_LSB 1 600 #define REO_DESTINATION_RING_8_REORDER_OPCODE_MASK 0x0000001e 601 602 /* Description REO_DESTINATION_RING_8_REORDER_SLOT_INDEX 603 604 Field only valid when 'Soft_reorder_info_valid' is set. 605 606 607 608 TODO: add description 609 610 611 612 <legal all> 613 */ 614 #define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_OFFSET 0x00000020 615 #define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_LSB 5 616 #define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_MASK 0x00001fe0 617 618 /* Description REO_DESTINATION_RING_8_RESERVED_8A 619 620 <legal 0> 621 */ 622 #define REO_DESTINATION_RING_8_RESERVED_8A_OFFSET 0x00000020 623 #define REO_DESTINATION_RING_8_RESERVED_8A_LSB 13 624 #define REO_DESTINATION_RING_8_RESERVED_8A_MASK 0xffffe000 625 626 /* Description REO_DESTINATION_RING_9_RESERVED_9A 627 628 <legal 0> 629 */ 630 #define REO_DESTINATION_RING_9_RESERVED_9A_OFFSET 0x00000024 631 #define REO_DESTINATION_RING_9_RESERVED_9A_LSB 0 632 #define REO_DESTINATION_RING_9_RESERVED_9A_MASK 0xffffffff 633 634 /* Description REO_DESTINATION_RING_10_RESERVED_10A 635 636 <legal 0> 637 */ 638 #define REO_DESTINATION_RING_10_RESERVED_10A_OFFSET 0x00000028 639 #define REO_DESTINATION_RING_10_RESERVED_10A_LSB 0 640 #define REO_DESTINATION_RING_10_RESERVED_10A_MASK 0xffffffff 641 642 /* Description REO_DESTINATION_RING_11_RESERVED_11A 643 644 <legal 0> 645 */ 646 #define REO_DESTINATION_RING_11_RESERVED_11A_OFFSET 0x0000002c 647 #define REO_DESTINATION_RING_11_RESERVED_11A_LSB 0 648 #define REO_DESTINATION_RING_11_RESERVED_11A_MASK 0xffffffff 649 650 /* Description REO_DESTINATION_RING_12_RESERVED_12A 651 652 <legal 0> 653 */ 654 #define REO_DESTINATION_RING_12_RESERVED_12A_OFFSET 0x00000030 655 #define REO_DESTINATION_RING_12_RESERVED_12A_LSB 0 656 #define REO_DESTINATION_RING_12_RESERVED_12A_MASK 0xffffffff 657 658 /* Description REO_DESTINATION_RING_13_RESERVED_13A 659 660 <legal 0> 661 */ 662 #define REO_DESTINATION_RING_13_RESERVED_13A_OFFSET 0x00000034 663 #define REO_DESTINATION_RING_13_RESERVED_13A_LSB 0 664 #define REO_DESTINATION_RING_13_RESERVED_13A_MASK 0xffffffff 665 666 /* Description REO_DESTINATION_RING_14_RESERVED_14A 667 668 <legal 0> 669 */ 670 #define REO_DESTINATION_RING_14_RESERVED_14A_OFFSET 0x00000038 671 #define REO_DESTINATION_RING_14_RESERVED_14A_LSB 0 672 #define REO_DESTINATION_RING_14_RESERVED_14A_MASK 0xffffffff 673 674 /* Description REO_DESTINATION_RING_15_RESERVED_15 675 676 <legal 0> 677 */ 678 #define REO_DESTINATION_RING_15_RESERVED_15_OFFSET 0x0000003c 679 #define REO_DESTINATION_RING_15_RESERVED_15_LSB 0 680 #define REO_DESTINATION_RING_15_RESERVED_15_MASK 0x000fffff 681 682 /* Description REO_DESTINATION_RING_15_RING_ID 683 684 The buffer pointer ring ID. 685 686 0 refers to the IDLE ring 687 688 1 - N refers to other rings 689 690 691 692 Helps with debugging when dumping ring contents. 693 694 <legal all> 695 */ 696 #define REO_DESTINATION_RING_15_RING_ID_OFFSET 0x0000003c 697 #define REO_DESTINATION_RING_15_RING_ID_LSB 20 698 #define REO_DESTINATION_RING_15_RING_ID_MASK 0x0ff00000 699 700 /* Description REO_DESTINATION_RING_15_LOOPING_COUNT 701 702 A count value that indicates the number of times the 703 producer of entries into this Ring has looped around the 704 ring. 705 706 At initialization time, this value is set to 0. On the 707 first loop, this value is set to 1. After the max value is 708 reached allowed by the number of bits for this field, the 709 count value continues with 0 again. 710 711 In case SW is the consumer of the ring entries, it can 712 use this field to figure out up to where the producer of 713 entries has created new entries. This eliminates the need to 714 check where the head pointer' of the ring is located once 715 the SW starts processing an interrupt indicating that new 716 entries have been put into this ring... 717 718 719 720 Also note that SW if it wants only needs to look at the 721 LSB bit of this count value. 722 723 <legal all> 724 */ 725 #define REO_DESTINATION_RING_15_LOOPING_COUNT_OFFSET 0x0000003c 726 #define REO_DESTINATION_RING_15_LOOPING_COUNT_LSB 28 727 #define REO_DESTINATION_RING_15_LOOPING_COUNT_MASK 0xf0000000 728 729 730 #endif // _REO_DESTINATION_RING_H_ 731