1 /* 2 * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // DO NOT EDIT! This file is automatically generated 20 // These definitions are tied to a particular hardware layout 21 22 23 #ifndef _REO_FLUSH_QUEUE_H_ 24 #define _REO_FLUSH_QUEUE_H_ 25 #if !defined(__ASSEMBLER__) 26 #endif 27 28 #include "uniform_reo_cmd_header.h" 29 30 // ################ START SUMMARY ################# 31 // 32 // Dword Fields 33 // 0 struct uniform_reo_cmd_header cmd_header; 34 // 1 flush_desc_addr_31_0[31:0] 35 // 2 flush_desc_addr_39_32[7:0], block_desc_addr_usage_after_flush[8], block_resource_index[10:9], reserved_2a[31:11] 36 // 3 reserved_3a[31:0] 37 // 4 reserved_4a[31:0] 38 // 5 reserved_5a[31:0] 39 // 6 reserved_6a[31:0] 40 // 7 reserved_7a[31:0] 41 // 8 reserved_8a[31:0] 42 // 43 // ################ END SUMMARY ################# 44 45 #define NUM_OF_DWORDS_REO_FLUSH_QUEUE 9 46 47 struct reo_flush_queue { 48 struct uniform_reo_cmd_header cmd_header; 49 uint32_t flush_desc_addr_31_0 : 32; //[31:0] 50 uint32_t flush_desc_addr_39_32 : 8, //[7:0] 51 block_desc_addr_usage_after_flush: 1, //[8] 52 block_resource_index : 2, //[10:9] 53 reserved_2a : 21; //[31:11] 54 uint32_t reserved_3a : 32; //[31:0] 55 uint32_t reserved_4a : 32; //[31:0] 56 uint32_t reserved_5a : 32; //[31:0] 57 uint32_t reserved_6a : 32; //[31:0] 58 uint32_t reserved_7a : 32; //[31:0] 59 uint32_t reserved_8a : 32; //[31:0] 60 }; 61 62 /* 63 64 struct uniform_reo_cmd_header cmd_header 65 66 Consumer: REO 67 68 Producer: SW 69 70 71 72 Details for command execution tracking purposes. 73 74 flush_desc_addr_31_0 75 76 Consumer: REO 77 78 Producer: SW 79 80 81 82 Address (lower 32 bits) of the descriptor to flush 83 84 <legal all> 85 86 flush_desc_addr_39_32 87 88 Consumer: REO 89 90 Producer: SW 91 92 93 94 Address (upper 8 bits) of the descriptor to flush 95 96 <legal all> 97 98 block_desc_addr_usage_after_flush 99 100 When set, REO shall not re-fetch this address till SW 101 explicitly unblocked this address 102 103 104 105 If the blocking resource was already used, this command 106 shall fail and an error is reported 107 108 109 110 <legal all> 111 112 block_resource_index 113 114 Field only valid when 'Block_desc_addr_usage_after_flush 115 ' is set. 116 117 118 119 Indicates which of the four blocking resources in REO 120 will be assigned for managing the blocking of this address. 121 122 <legal all> 123 124 reserved_2a 125 126 <legal 0> 127 128 reserved_3a 129 130 <legal 0> 131 132 reserved_4a 133 134 <legal 0> 135 136 reserved_5a 137 138 <legal 0> 139 140 reserved_6a 141 142 <legal 0> 143 144 reserved_7a 145 146 <legal 0> 147 148 reserved_8a 149 150 <legal 0> 151 */ 152 153 #define REO_FLUSH_QUEUE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_OFFSET 0x00000000 154 #define REO_FLUSH_QUEUE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_LSB 0 155 #define REO_FLUSH_QUEUE_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_MASK 0xffffffff 156 157 /* Description REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0 158 159 Consumer: REO 160 161 Producer: SW 162 163 164 165 Address (lower 32 bits) of the descriptor to flush 166 167 <legal all> 168 */ 169 #define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_OFFSET 0x00000004 170 #define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_LSB 0 171 #define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff 172 173 /* Description REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32 174 175 Consumer: REO 176 177 Producer: SW 178 179 180 181 Address (upper 8 bits) of the descriptor to flush 182 183 <legal all> 184 */ 185 #define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_OFFSET 0x00000008 186 #define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_LSB 0 187 #define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_MASK 0x000000ff 188 189 /* Description REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH 190 191 When set, REO shall not re-fetch this address till SW 192 explicitly unblocked this address 193 194 195 196 If the blocking resource was already used, this command 197 shall fail and an error is reported 198 199 200 201 <legal all> 202 */ 203 #define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x00000008 204 #define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8 205 #define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x00000100 206 207 /* Description REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX 208 209 Field only valid when 'Block_desc_addr_usage_after_flush 210 ' is set. 211 212 213 214 Indicates which of the four blocking resources in REO 215 will be assigned for managing the blocking of this address. 216 217 <legal all> 218 */ 219 #define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008 220 #define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_LSB 9 221 #define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_MASK 0x00000600 222 223 /* Description REO_FLUSH_QUEUE_2_RESERVED_2A 224 225 <legal 0> 226 */ 227 #define REO_FLUSH_QUEUE_2_RESERVED_2A_OFFSET 0x00000008 228 #define REO_FLUSH_QUEUE_2_RESERVED_2A_LSB 11 229 #define REO_FLUSH_QUEUE_2_RESERVED_2A_MASK 0xfffff800 230 231 /* Description REO_FLUSH_QUEUE_3_RESERVED_3A 232 233 <legal 0> 234 */ 235 #define REO_FLUSH_QUEUE_3_RESERVED_3A_OFFSET 0x0000000c 236 #define REO_FLUSH_QUEUE_3_RESERVED_3A_LSB 0 237 #define REO_FLUSH_QUEUE_3_RESERVED_3A_MASK 0xffffffff 238 239 /* Description REO_FLUSH_QUEUE_4_RESERVED_4A 240 241 <legal 0> 242 */ 243 #define REO_FLUSH_QUEUE_4_RESERVED_4A_OFFSET 0x00000010 244 #define REO_FLUSH_QUEUE_4_RESERVED_4A_LSB 0 245 #define REO_FLUSH_QUEUE_4_RESERVED_4A_MASK 0xffffffff 246 247 /* Description REO_FLUSH_QUEUE_5_RESERVED_5A 248 249 <legal 0> 250 */ 251 #define REO_FLUSH_QUEUE_5_RESERVED_5A_OFFSET 0x00000014 252 #define REO_FLUSH_QUEUE_5_RESERVED_5A_LSB 0 253 #define REO_FLUSH_QUEUE_5_RESERVED_5A_MASK 0xffffffff 254 255 /* Description REO_FLUSH_QUEUE_6_RESERVED_6A 256 257 <legal 0> 258 */ 259 #define REO_FLUSH_QUEUE_6_RESERVED_6A_OFFSET 0x00000018 260 #define REO_FLUSH_QUEUE_6_RESERVED_6A_LSB 0 261 #define REO_FLUSH_QUEUE_6_RESERVED_6A_MASK 0xffffffff 262 263 /* Description REO_FLUSH_QUEUE_7_RESERVED_7A 264 265 <legal 0> 266 */ 267 #define REO_FLUSH_QUEUE_7_RESERVED_7A_OFFSET 0x0000001c 268 #define REO_FLUSH_QUEUE_7_RESERVED_7A_LSB 0 269 #define REO_FLUSH_QUEUE_7_RESERVED_7A_MASK 0xffffffff 270 271 /* Description REO_FLUSH_QUEUE_8_RESERVED_8A 272 273 <legal 0> 274 */ 275 #define REO_FLUSH_QUEUE_8_RESERVED_8A_OFFSET 0x00000020 276 #define REO_FLUSH_QUEUE_8_RESERVED_8A_LSB 0 277 #define REO_FLUSH_QUEUE_8_RESERVED_8A_MASK 0xffffffff 278 279 280 #endif // _REO_FLUSH_QUEUE_H_ 281