1 /* 2 * Copyright (c) 2016 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // $ATH_LICENSE_HW_HDR_C$ 20 // 21 // DO NOT EDIT! This file is automatically generated 22 // These definitions are tied to a particular hardware layout 23 24 25 #ifndef _RX_MPDU_END_H_ 26 #define _RX_MPDU_END_H_ 27 #if !defined(__ASSEMBLER__) 28 #endif 29 30 31 // ################ START SUMMARY ################# 32 // 33 // Dword Fields 34 // 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16] 35 // 1 reserved_1a[10:0], unsup_ktype_short_frame[11], rx_in_tx_decrypt_byp[12], overflow_err[13], mpdu_length_err[14], tkip_mic_err[15], decrypt_err[16], unencrypted_frame_err[17], pn_fields_contain_valid_info[18], fcs_err[19], msdu_length_err[20], rxdma0_destination_ring[22:21], rxdma1_destination_ring[24:23], decrypt_status_code[27:25], rx_bitmap_not_updated[28], reserved_1b[31:29] 36 // 37 // ################ END SUMMARY ################# 38 39 #define NUM_OF_DWORDS_RX_MPDU_END 2 40 41 struct rx_mpdu_end { 42 uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] 43 sw_frame_group_id : 7, //[8:2] 44 reserved_0 : 7, //[15:9] 45 phy_ppdu_id : 16; //[31:16] 46 uint32_t reserved_1a : 11, //[10:0] 47 unsup_ktype_short_frame : 1, //[11] 48 rx_in_tx_decrypt_byp : 1, //[12] 49 overflow_err : 1, //[13] 50 mpdu_length_err : 1, //[14] 51 tkip_mic_err : 1, //[15] 52 decrypt_err : 1, //[16] 53 unencrypted_frame_err : 1, //[17] 54 pn_fields_contain_valid_info : 1, //[18] 55 fcs_err : 1, //[19] 56 msdu_length_err : 1, //[20] 57 rxdma0_destination_ring : 2, //[22:21] 58 rxdma1_destination_ring : 2, //[24:23] 59 decrypt_status_code : 3, //[27:25] 60 rx_bitmap_not_updated : 1, //[28] 61 reserved_1b : 3; //[31:29] 62 }; 63 64 /* 65 66 rxpcu_mpdu_filter_in_category 67 68 Field indicates what the reason was that this MPDU frame 69 was allowed to come into the receive path by RXPCU 70 71 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 72 frame filter programming of rxpcu 73 74 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 75 regular frame filter and would have been dropped, were it 76 not for the frame fitting into the 'monitor_client' 77 category. 78 79 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 80 regular frame filter and also did not pass the 81 rxpcu_monitor_client filter. It would have been dropped 82 accept that it did pass the 'monitor_other' category. 83 84 <legal 0-2> 85 86 sw_frame_group_id 87 88 SW processes frames based on certain classifications. 89 This field indicates to what sw classification this MPDU is 90 mapped. 91 92 The classification is given in priority order 93 94 95 96 <enum 0 sw_frame_group_NDP_frame> 97 98 99 100 <enum 1 sw_frame_group_Multicast_data> 101 102 <enum 2 sw_frame_group_Unicast_data> 103 104 <enum 3 sw_frame_group_Null_data > This includes mpdus 105 of type Data Null as well as QoS Data Null 106 107 108 109 <enum 4 sw_frame_group_mgmt_0000 > 110 111 <enum 5 sw_frame_group_mgmt_0001 > 112 113 <enum 6 sw_frame_group_mgmt_0010 > 114 115 <enum 7 sw_frame_group_mgmt_0011 > 116 117 <enum 8 sw_frame_group_mgmt_0100 > 118 119 <enum 9 sw_frame_group_mgmt_0101 > 120 121 <enum 10 sw_frame_group_mgmt_0110 > 122 123 <enum 11 sw_frame_group_mgmt_0111 > 124 125 <enum 12 sw_frame_group_mgmt_1000 > 126 127 <enum 13 sw_frame_group_mgmt_1001 > 128 129 <enum 14 sw_frame_group_mgmt_1010 > 130 131 <enum 15 sw_frame_group_mgmt_1011 > 132 133 <enum 16 sw_frame_group_mgmt_1100 > 134 135 <enum 17 sw_frame_group_mgmt_1101 > 136 137 <enum 18 sw_frame_group_mgmt_1110 > 138 139 <enum 19 sw_frame_group_mgmt_1111 > 140 141 142 143 <enum 20 sw_frame_group_ctrl_0000 > 144 145 <enum 21 sw_frame_group_ctrl_0001 > 146 147 <enum 22 sw_frame_group_ctrl_0010 > 148 149 <enum 23 sw_frame_group_ctrl_0011 > 150 151 <enum 24 sw_frame_group_ctrl_0100 > 152 153 <enum 25 sw_frame_group_ctrl_0101 > 154 155 <enum 26 sw_frame_group_ctrl_0110 > 156 157 <enum 27 sw_frame_group_ctrl_0111 > 158 159 <enum 28 sw_frame_group_ctrl_1000 > 160 161 <enum 29 sw_frame_group_ctrl_1001 > 162 163 <enum 30 sw_frame_group_ctrl_1010 > 164 165 <enum 31 sw_frame_group_ctrl_1011 > 166 167 <enum 32 sw_frame_group_ctrl_1100 > 168 169 <enum 33 sw_frame_group_ctrl_1101 > 170 171 <enum 34 sw_frame_group_ctrl_1110 > 172 173 <enum 35 sw_frame_group_ctrl_1111 > 174 175 176 177 <enum 36 sw_frame_group_unsupported> This covers type 3 178 and protocol version != 0 179 180 181 182 183 184 185 <legal 0-37> 186 187 reserved_0 188 189 <legal 0> 190 191 phy_ppdu_id 192 193 A ppdu counter value that PHY increments for every PPDU 194 received. The counter value wraps around 195 196 <legal all> 197 198 reserved_1a 199 200 <legal 0> 201 202 unsup_ktype_short_frame 203 204 This bit will be '1' when WEP or TKIP or WAPI key type 205 is received for 11ah short frame. Crypto will bypass the 206 received packet without decryption to RxOLE after setting 207 this bit. 208 209 rx_in_tx_decrypt_byp 210 211 Indicates that RX packet is not decrypted as Crypto is 212 busy with TX packet processing. 213 214 overflow_err 215 216 RXPCU Receive FIFO ran out of space to receive the full 217 MPDU. Therefor this MPDU is terminated early and is thus 218 corrupted. 219 220 221 222 This MPDU will not be ACKed. 223 224 RXPCU might still be able to correctly receive the 225 following MPDUs in the PPDU if enough fifo space became 226 available in time 227 228 mpdu_length_err 229 230 Set by RXPCU if the expected MPDU length does not 231 correspond with the actually received number of bytes in the 232 MPDU. 233 234 tkip_mic_err 235 236 Set by RX CRYPTO when CRYPTO detected a TKIP MIC error 237 for this MPDU 238 239 decrypt_err 240 241 Set by RX CRYPTO when CRYPTO detected a decrypt error 242 for this MPDU. 243 244 unencrypted_frame_err 245 246 Set by RX CRYPTO when CRYPTO detected an unencrypted 247 frame while in the peer entry field 248 'All_frames_shall_be_encrypted' is set. 249 250 pn_fields_contain_valid_info 251 252 Set by RX CRYPTO to indicate that there is a valid PN 253 field present in this MPDU 254 255 fcs_err 256 257 Set by RXPCU when there is an FCS error detected for 258 this MPDU 259 260 msdu_length_err 261 262 Set by RXOLE when there is an msdu length error detected 263 in at least 1 of the MSDUs embedded within the MPDU 264 265 rxdma0_destination_ring 266 267 The ring to which RXDMA0 shall push the frame, assuming 268 no MPDU level errors are detected. In case of MPDU level 269 errors, RXDMA0 might change the RXDMA0 destination 270 271 272 273 <enum 0 rxdma_release_ring > RXDMA0 shall push the 274 frame to the Release ring. Effectively this means the frame 275 needs to be dropped. 276 277 278 279 <enum 1 rxdma2fw_ring > RXDMA0 shall push the frame to 280 the FW ring 281 282 283 284 <enum 2 rxdma2sw_ring > RXDMA0 shall push the frame to 285 the SW ring 286 287 288 289 <enum 3 rxdma2reo_ring > RXDMA0 shall push the frame 290 to the REO entrance ring 291 292 293 294 <legal all> 295 296 rxdma1_destination_ring 297 298 The ring to which RXDMA1 shall push the frame, assuming 299 no MPDU level errors are detected. In case of MPDU level 300 errors, RXDMA1 might change the RXDMA destination 301 302 303 304 <enum 0 rxdma_release_ring > RXDMA1 shall push the 305 frame to the Release ring. Effectively this means the frame 306 needs to be dropped. 307 308 309 310 <enum 1 rxdma2fw_ring > RXDMA1 shall push the frame to 311 the FW ring 312 313 314 315 <enum 2 rxdma2sw_ring > RXDMA1 shall push the frame to 316 the SW ring 317 318 319 320 <enum 3 rxdma2reo_ring > RXDMA1 shall push the frame 321 to the REO entrance ring 322 323 324 325 <legal all> 326 327 decrypt_status_code 328 329 Field provides insight into the decryption performed 330 331 332 333 <enum 0 decrypt_ok> Frame had protection enabled and 334 decrypted properly 335 336 <enum 1 decrypt_unprotected_frame > Frame is unprotected 337 and hence bypassed 338 339 <enum 2 decrypt_data_err > Frame has protection enabled 340 and could not be properly decrypted due to MIC/ICV mismatch 341 etc. 342 343 <enum 3 decrypt_key_invalid > Frame has protection 344 enabled but the key that was required to decrypt this frame 345 was not valid 346 347 <enum 4 decrypt_peer_entry_invalid > Frame has 348 protection enabled but the key that was required to decrypt 349 this frame was not valid 350 351 <enum 5 decrypt_other > Reserved for other indications 352 353 354 355 <legal 0 - 5> 356 357 rx_bitmap_not_updated 358 359 Frame is received, but RXPCU could not update the 360 receive bitmap due to (temporary) fifo contraints. 361 362 <legal all> 363 364 reserved_1b 365 366 <legal 0> 367 */ 368 369 370 /* Description RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY 371 372 Field indicates what the reason was that this MPDU frame 373 was allowed to come into the receive path by RXPCU 374 375 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 376 frame filter programming of rxpcu 377 378 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 379 regular frame filter and would have been dropped, were it 380 not for the frame fitting into the 'monitor_client' 381 category. 382 383 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 384 regular frame filter and also did not pass the 385 rxpcu_monitor_client filter. It would have been dropped 386 accept that it did pass the 'monitor_other' category. 387 388 <legal 0-2> 389 */ 390 #define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 391 #define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 392 #define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 393 394 /* Description RX_MPDU_END_0_SW_FRAME_GROUP_ID 395 396 SW processes frames based on certain classifications. 397 This field indicates to what sw classification this MPDU is 398 mapped. 399 400 The classification is given in priority order 401 402 403 404 <enum 0 sw_frame_group_NDP_frame> 405 406 407 408 <enum 1 sw_frame_group_Multicast_data> 409 410 <enum 2 sw_frame_group_Unicast_data> 411 412 <enum 3 sw_frame_group_Null_data > This includes mpdus 413 of type Data Null as well as QoS Data Null 414 415 416 417 <enum 4 sw_frame_group_mgmt_0000 > 418 419 <enum 5 sw_frame_group_mgmt_0001 > 420 421 <enum 6 sw_frame_group_mgmt_0010 > 422 423 <enum 7 sw_frame_group_mgmt_0011 > 424 425 <enum 8 sw_frame_group_mgmt_0100 > 426 427 <enum 9 sw_frame_group_mgmt_0101 > 428 429 <enum 10 sw_frame_group_mgmt_0110 > 430 431 <enum 11 sw_frame_group_mgmt_0111 > 432 433 <enum 12 sw_frame_group_mgmt_1000 > 434 435 <enum 13 sw_frame_group_mgmt_1001 > 436 437 <enum 14 sw_frame_group_mgmt_1010 > 438 439 <enum 15 sw_frame_group_mgmt_1011 > 440 441 <enum 16 sw_frame_group_mgmt_1100 > 442 443 <enum 17 sw_frame_group_mgmt_1101 > 444 445 <enum 18 sw_frame_group_mgmt_1110 > 446 447 <enum 19 sw_frame_group_mgmt_1111 > 448 449 450 451 <enum 20 sw_frame_group_ctrl_0000 > 452 453 <enum 21 sw_frame_group_ctrl_0001 > 454 455 <enum 22 sw_frame_group_ctrl_0010 > 456 457 <enum 23 sw_frame_group_ctrl_0011 > 458 459 <enum 24 sw_frame_group_ctrl_0100 > 460 461 <enum 25 sw_frame_group_ctrl_0101 > 462 463 <enum 26 sw_frame_group_ctrl_0110 > 464 465 <enum 27 sw_frame_group_ctrl_0111 > 466 467 <enum 28 sw_frame_group_ctrl_1000 > 468 469 <enum 29 sw_frame_group_ctrl_1001 > 470 471 <enum 30 sw_frame_group_ctrl_1010 > 472 473 <enum 31 sw_frame_group_ctrl_1011 > 474 475 <enum 32 sw_frame_group_ctrl_1100 > 476 477 <enum 33 sw_frame_group_ctrl_1101 > 478 479 <enum 34 sw_frame_group_ctrl_1110 > 480 481 <enum 35 sw_frame_group_ctrl_1111 > 482 483 484 485 <enum 36 sw_frame_group_unsupported> This covers type 3 486 and protocol version != 0 487 488 489 490 491 492 493 <legal 0-37> 494 */ 495 #define RX_MPDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 496 #define RX_MPDU_END_0_SW_FRAME_GROUP_ID_LSB 2 497 #define RX_MPDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc 498 499 /* Description RX_MPDU_END_0_RESERVED_0 500 501 <legal 0> 502 */ 503 #define RX_MPDU_END_0_RESERVED_0_OFFSET 0x00000000 504 #define RX_MPDU_END_0_RESERVED_0_LSB 9 505 #define RX_MPDU_END_0_RESERVED_0_MASK 0x0000fe00 506 507 /* Description RX_MPDU_END_0_PHY_PPDU_ID 508 509 A ppdu counter value that PHY increments for every PPDU 510 received. The counter value wraps around 511 512 <legal all> 513 */ 514 #define RX_MPDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000 515 #define RX_MPDU_END_0_PHY_PPDU_ID_LSB 16 516 #define RX_MPDU_END_0_PHY_PPDU_ID_MASK 0xffff0000 517 518 /* Description RX_MPDU_END_1_RESERVED_1A 519 520 <legal 0> 521 */ 522 #define RX_MPDU_END_1_RESERVED_1A_OFFSET 0x00000004 523 #define RX_MPDU_END_1_RESERVED_1A_LSB 0 524 #define RX_MPDU_END_1_RESERVED_1A_MASK 0x000007ff 525 526 /* Description RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME 527 528 This bit will be '1' when WEP or TKIP or WAPI key type 529 is received for 11ah short frame. Crypto will bypass the 530 received packet without decryption to RxOLE after setting 531 this bit. 532 */ 533 #define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x00000004 534 #define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_LSB 11 535 #define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_MASK 0x00000800 536 537 /* Description RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP 538 539 Indicates that RX packet is not decrypted as Crypto is 540 busy with TX packet processing. 541 */ 542 #define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004 543 #define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB 12 544 #define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK 0x00001000 545 546 /* Description RX_MPDU_END_1_OVERFLOW_ERR 547 548 RXPCU Receive FIFO ran out of space to receive the full 549 MPDU. Therefor this MPDU is terminated early and is thus 550 corrupted. 551 552 553 554 This MPDU will not be ACKed. 555 556 RXPCU might still be able to correctly receive the 557 following MPDUs in the PPDU if enough fifo space became 558 available in time 559 */ 560 #define RX_MPDU_END_1_OVERFLOW_ERR_OFFSET 0x00000004 561 #define RX_MPDU_END_1_OVERFLOW_ERR_LSB 13 562 #define RX_MPDU_END_1_OVERFLOW_ERR_MASK 0x00002000 563 564 /* Description RX_MPDU_END_1_MPDU_LENGTH_ERR 565 566 Set by RXPCU if the expected MPDU length does not 567 correspond with the actually received number of bytes in the 568 MPDU. 569 */ 570 #define RX_MPDU_END_1_MPDU_LENGTH_ERR_OFFSET 0x00000004 571 #define RX_MPDU_END_1_MPDU_LENGTH_ERR_LSB 14 572 #define RX_MPDU_END_1_MPDU_LENGTH_ERR_MASK 0x00004000 573 574 /* Description RX_MPDU_END_1_TKIP_MIC_ERR 575 576 Set by RX CRYPTO when CRYPTO detected a TKIP MIC error 577 for this MPDU 578 */ 579 #define RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET 0x00000004 580 #define RX_MPDU_END_1_TKIP_MIC_ERR_LSB 15 581 #define RX_MPDU_END_1_TKIP_MIC_ERR_MASK 0x00008000 582 583 /* Description RX_MPDU_END_1_DECRYPT_ERR 584 585 Set by RX CRYPTO when CRYPTO detected a decrypt error 586 for this MPDU. 587 */ 588 #define RX_MPDU_END_1_DECRYPT_ERR_OFFSET 0x00000004 589 #define RX_MPDU_END_1_DECRYPT_ERR_LSB 16 590 #define RX_MPDU_END_1_DECRYPT_ERR_MASK 0x00010000 591 592 /* Description RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR 593 594 Set by RX CRYPTO when CRYPTO detected an unencrypted 595 frame while in the peer entry field 596 'All_frames_shall_be_encrypted' is set. 597 */ 598 #define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004 599 #define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_LSB 17 600 #define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_MASK 0x00020000 601 602 /* Description RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO 603 604 Set by RX CRYPTO to indicate that there is a valid PN 605 field present in this MPDU 606 */ 607 #define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000004 608 #define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_LSB 18 609 #define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00040000 610 611 /* Description RX_MPDU_END_1_FCS_ERR 612 613 Set by RXPCU when there is an FCS error detected for 614 this MPDU 615 */ 616 #define RX_MPDU_END_1_FCS_ERR_OFFSET 0x00000004 617 #define RX_MPDU_END_1_FCS_ERR_LSB 19 618 #define RX_MPDU_END_1_FCS_ERR_MASK 0x00080000 619 620 /* Description RX_MPDU_END_1_MSDU_LENGTH_ERR 621 622 Set by RXOLE when there is an msdu length error detected 623 in at least 1 of the MSDUs embedded within the MPDU 624 */ 625 #define RX_MPDU_END_1_MSDU_LENGTH_ERR_OFFSET 0x00000004 626 #define RX_MPDU_END_1_MSDU_LENGTH_ERR_LSB 20 627 #define RX_MPDU_END_1_MSDU_LENGTH_ERR_MASK 0x00100000 628 629 /* Description RX_MPDU_END_1_RXDMA0_DESTINATION_RING 630 631 The ring to which RXDMA0 shall push the frame, assuming 632 no MPDU level errors are detected. In case of MPDU level 633 errors, RXDMA0 might change the RXDMA0 destination 634 635 636 637 <enum 0 rxdma_release_ring > RXDMA0 shall push the 638 frame to the Release ring. Effectively this means the frame 639 needs to be dropped. 640 641 642 643 <enum 1 rxdma2fw_ring > RXDMA0 shall push the frame to 644 the FW ring 645 646 647 648 <enum 2 rxdma2sw_ring > RXDMA0 shall push the frame to 649 the SW ring 650 651 652 653 <enum 3 rxdma2reo_ring > RXDMA0 shall push the frame 654 to the REO entrance ring 655 656 657 658 <legal all> 659 */ 660 #define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_OFFSET 0x00000004 661 #define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_LSB 21 662 #define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_MASK 0x00600000 663 664 /* Description RX_MPDU_END_1_RXDMA1_DESTINATION_RING 665 666 The ring to which RXDMA1 shall push the frame, assuming 667 no MPDU level errors are detected. In case of MPDU level 668 errors, RXDMA1 might change the RXDMA destination 669 670 671 672 <enum 0 rxdma_release_ring > RXDMA1 shall push the 673 frame to the Release ring. Effectively this means the frame 674 needs to be dropped. 675 676 677 678 <enum 1 rxdma2fw_ring > RXDMA1 shall push the frame to 679 the FW ring 680 681 682 683 <enum 2 rxdma2sw_ring > RXDMA1 shall push the frame to 684 the SW ring 685 686 687 688 <enum 3 rxdma2reo_ring > RXDMA1 shall push the frame 689 to the REO entrance ring 690 691 692 693 <legal all> 694 */ 695 #define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_OFFSET 0x00000004 696 #define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_LSB 23 697 #define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_MASK 0x01800000 698 699 /* Description RX_MPDU_END_1_DECRYPT_STATUS_CODE 700 701 Field provides insight into the decryption performed 702 703 704 705 <enum 0 decrypt_ok> Frame had protection enabled and 706 decrypted properly 707 708 <enum 1 decrypt_unprotected_frame > Frame is unprotected 709 and hence bypassed 710 711 <enum 2 decrypt_data_err > Frame has protection enabled 712 and could not be properly decrypted due to MIC/ICV mismatch 713 etc. 714 715 <enum 3 decrypt_key_invalid > Frame has protection 716 enabled but the key that was required to decrypt this frame 717 was not valid 718 719 <enum 4 decrypt_peer_entry_invalid > Frame has 720 protection enabled but the key that was required to decrypt 721 this frame was not valid 722 723 <enum 5 decrypt_other > Reserved for other indications 724 725 726 727 <legal 0 - 5> 728 */ 729 #define RX_MPDU_END_1_DECRYPT_STATUS_CODE_OFFSET 0x00000004 730 #define RX_MPDU_END_1_DECRYPT_STATUS_CODE_LSB 25 731 #define RX_MPDU_END_1_DECRYPT_STATUS_CODE_MASK 0x0e000000 732 733 /* Description RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED 734 735 Frame is received, but RXPCU could not update the 736 receive bitmap due to (temporary) fifo contraints. 737 738 <legal all> 739 */ 740 #define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000004 741 #define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_LSB 28 742 #define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_MASK 0x10000000 743 744 /* Description RX_MPDU_END_1_RESERVED_1B 745 746 <legal 0> 747 */ 748 #define RX_MPDU_END_1_RESERVED_1B_OFFSET 0x00000004 749 #define RX_MPDU_END_1_RESERVED_1B_LSB 29 750 #define RX_MPDU_END_1_RESERVED_1B_MASK 0xe0000000 751 752 753 #endif // _RX_MPDU_END_H_ 754