1 /* 2 * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // DO NOT EDIT! This file is automatically generated 20 // These definitions are tied to a particular hardware layout 21 22 23 #ifndef _RX_MSDU_END_H_ 24 #define _RX_MSDU_END_H_ 25 #if !defined(__ASSEMBLER__) 26 #endif 27 28 29 // ################ START SUMMARY ################# 30 // 31 // Dword Fields 32 // 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16] 33 // 1 ip_hdr_chksum[15:0], tcp_udp_chksum[31:16] 34 // 2 key_id_octet[7:0], cce_super_rule[13:8], cce_classify_not_done_truncate[14], cce_classify_not_done_cce_dis[15], ext_wapi_pn_63_48[31:16] 35 // 3 ext_wapi_pn_95_64[31:0] 36 // 4 ext_wapi_pn_127_96[31:0] 37 // 5 reported_mpdu_length[13:0], first_msdu[14], last_msdu[15], sa_idx_timeout[16], da_idx_timeout[17], msdu_limit_error[18], flow_idx_timeout[19], flow_idx_invalid[20], wifi_parser_error[21], amsdu_parser_error[22], sa_is_valid[23], da_is_valid[24], da_is_mcbc[25], l3_header_padding[27:26], reserved_5a[31:28] 38 // 6 ipv6_options_crc[31:0] 39 // 7 tcp_seq_number[31:0] 40 // 8 tcp_ack_number[31:0] 41 // 9 tcp_flag[8:0], lro_eligible[9], reserved_9a[15:10], window_size[31:16] 42 // 10 da_offset[5:0], sa_offset[11:6], da_offset_valid[12], sa_offset_valid[13], type_offset[20:14], reserved_10a[31:21] 43 // 11 rule_indication_31_0[31:0] 44 // 12 rule_indication_63_32[31:0] 45 // 13 sa_idx[15:0], da_idx[31:16] 46 // 14 msdu_drop[0], reo_destination_indication[5:1], flow_idx[25:6], reserved_14[31:26] 47 // 15 fse_metadata[31:0] 48 // 16 cce_metadata[15:0], sa_sw_peer_id[31:16] 49 // 50 // ################ END SUMMARY ################# 51 52 #define NUM_OF_DWORDS_RX_MSDU_END 17 53 54 struct rx_msdu_end { 55 uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] 56 sw_frame_group_id : 7, //[8:2] 57 reserved_0 : 7, //[15:9] 58 phy_ppdu_id : 16; //[31:16] 59 uint32_t ip_hdr_chksum : 16, //[15:0] 60 tcp_udp_chksum : 16; //[31:16] 61 uint32_t key_id_octet : 8, //[7:0] 62 cce_super_rule : 6, //[13:8] 63 cce_classify_not_done_truncate : 1, //[14] 64 cce_classify_not_done_cce_dis : 1, //[15] 65 ext_wapi_pn_63_48 : 16; //[31:16] 66 uint32_t ext_wapi_pn_95_64 : 32; //[31:0] 67 uint32_t ext_wapi_pn_127_96 : 32; //[31:0] 68 uint32_t reported_mpdu_length : 14, //[13:0] 69 first_msdu : 1, //[14] 70 last_msdu : 1, //[15] 71 sa_idx_timeout : 1, //[16] 72 da_idx_timeout : 1, //[17] 73 msdu_limit_error : 1, //[18] 74 flow_idx_timeout : 1, //[19] 75 flow_idx_invalid : 1, //[20] 76 wifi_parser_error : 1, //[21] 77 amsdu_parser_error : 1, //[22] 78 sa_is_valid : 1, //[23] 79 da_is_valid : 1, //[24] 80 da_is_mcbc : 1, //[25] 81 l3_header_padding : 2, //[27:26] 82 reserved_5a : 4; //[31:28] 83 uint32_t ipv6_options_crc : 32; //[31:0] 84 uint32_t tcp_seq_number : 32; //[31:0] 85 uint32_t tcp_ack_number : 32; //[31:0] 86 uint32_t tcp_flag : 9, //[8:0] 87 lro_eligible : 1, //[9] 88 reserved_9a : 6, //[15:10] 89 window_size : 16; //[31:16] 90 uint32_t da_offset : 6, //[5:0] 91 sa_offset : 6, //[11:6] 92 da_offset_valid : 1, //[12] 93 sa_offset_valid : 1, //[13] 94 type_offset : 7, //[20:14] 95 reserved_10a : 11; //[31:21] 96 uint32_t rule_indication_31_0 : 32; //[31:0] 97 uint32_t rule_indication_63_32 : 32; //[31:0] 98 uint32_t sa_idx : 16, //[15:0] 99 da_idx : 16; //[31:16] 100 uint32_t msdu_drop : 1, //[0] 101 reo_destination_indication : 5, //[5:1] 102 flow_idx : 20, //[25:6] 103 reserved_14 : 6; //[31:26] 104 uint32_t fse_metadata : 32; //[31:0] 105 uint32_t cce_metadata : 16, //[15:0] 106 sa_sw_peer_id : 16; //[31:16] 107 }; 108 109 /* 110 111 rxpcu_mpdu_filter_in_category 112 113 Field indicates what the reason was that this MPDU frame 114 was allowed to come into the receive path by RXPCU 115 116 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 117 frame filter programming of rxpcu 118 119 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 120 regular frame filter and would have been dropped, were it 121 not for the frame fitting into the 'monitor_client' 122 category. 123 124 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 125 regular frame filter and also did not pass the 126 rxpcu_monitor_client filter. It would have been dropped 127 accept that it did pass the 'monitor_other' category. 128 129 <legal 0-2> 130 131 sw_frame_group_id 132 133 SW processes frames based on certain classifications. 134 This field indicates to what sw classification this MPDU is 135 mapped. 136 137 The classification is given in priority order 138 139 140 141 <enum 0 sw_frame_group_NDP_frame> 142 143 144 145 <enum 1 sw_frame_group_Multicast_data> 146 147 <enum 2 sw_frame_group_Unicast_data> 148 149 <enum 3 sw_frame_group_Null_data > This includes mpdus 150 of type Data Null as well as QoS Data Null 151 152 153 154 <enum 4 sw_frame_group_mgmt_0000 > 155 156 <enum 5 sw_frame_group_mgmt_0001 > 157 158 <enum 6 sw_frame_group_mgmt_0010 > 159 160 <enum 7 sw_frame_group_mgmt_0011 > 161 162 <enum 8 sw_frame_group_mgmt_0100 > 163 164 <enum 9 sw_frame_group_mgmt_0101 > 165 166 <enum 10 sw_frame_group_mgmt_0110 > 167 168 <enum 11 sw_frame_group_mgmt_0111 > 169 170 <enum 12 sw_frame_group_mgmt_1000 > 171 172 <enum 13 sw_frame_group_mgmt_1001 > 173 174 <enum 14 sw_frame_group_mgmt_1010 > 175 176 <enum 15 sw_frame_group_mgmt_1011 > 177 178 <enum 16 sw_frame_group_mgmt_1100 > 179 180 <enum 17 sw_frame_group_mgmt_1101 > 181 182 <enum 18 sw_frame_group_mgmt_1110 > 183 184 <enum 19 sw_frame_group_mgmt_1111 > 185 186 187 188 <enum 20 sw_frame_group_ctrl_0000 > 189 190 <enum 21 sw_frame_group_ctrl_0001 > 191 192 <enum 22 sw_frame_group_ctrl_0010 > 193 194 <enum 23 sw_frame_group_ctrl_0011 > 195 196 <enum 24 sw_frame_group_ctrl_0100 > 197 198 <enum 25 sw_frame_group_ctrl_0101 > 199 200 <enum 26 sw_frame_group_ctrl_0110 > 201 202 <enum 27 sw_frame_group_ctrl_0111 > 203 204 <enum 28 sw_frame_group_ctrl_1000 > 205 206 <enum 29 sw_frame_group_ctrl_1001 > 207 208 <enum 30 sw_frame_group_ctrl_1010 > 209 210 <enum 31 sw_frame_group_ctrl_1011 > 211 212 <enum 32 sw_frame_group_ctrl_1100 > 213 214 <enum 33 sw_frame_group_ctrl_1101 > 215 216 <enum 34 sw_frame_group_ctrl_1110 > 217 218 <enum 35 sw_frame_group_ctrl_1111 > 219 220 221 222 <enum 36 sw_frame_group_unsupported> This covers type 3 223 and protocol version != 0 224 225 226 227 228 229 230 <legal 0-37> 231 232 reserved_0 233 234 <legal 0> 235 236 phy_ppdu_id 237 238 A ppdu counter value that PHY increments for every PPDU 239 received. The counter value wraps around 240 241 <legal all> 242 243 ip_hdr_chksum 244 245 This can include the IP header checksum or the pseudo 246 header checksum used by TCP/UDP checksum. 247 248 tcp_udp_chksum 249 250 The value of the computed TCP/UDP checksum. A mode bit 251 selects whether this checksum is the full checksum or the 252 partial checksum which does not include the pseudo header. 253 254 key_id_octet 255 256 The key ID octet from the IV. Only valid when 257 first_msdu is set. 258 259 cce_super_rule 260 261 Indicates the super filter rule 262 263 cce_classify_not_done_truncate 264 265 Classification failed due to truncated frame 266 267 cce_classify_not_done_cce_dis 268 269 Classification failed due to CCE global disable 270 271 ext_wapi_pn_63_48 272 273 Extension PN (packet number) which is only used by WAPI. 274 This corresponds to WAPI PN bits [63:48] (pn6 and pn7). 275 The WAPI PN bits [63:0] are in the pn field of the 276 rx_mpdu_start descriptor. 277 278 ext_wapi_pn_95_64 279 280 Extension PN (packet number) which is only used by WAPI. 281 This corresponds to WAPI PN bits [95:64] (pn8, pn9, pn10 282 and pn11). 283 284 ext_wapi_pn_127_96 285 286 Extension PN (packet number) which is only used by WAPI. 287 This corresponds to WAPI PN bits [127:96] (pn12, pn13, 288 pn14, pn15). 289 290 reported_mpdu_length 291 292 MPDU length before decapsulation. Only valid when 293 first_msdu is set. This field is taken directly from the 294 length field of the A-MPDU delimiter or the preamble length 295 field for non-A-MPDU frames. 296 297 first_msdu 298 299 Indicates the first MSDU of A-MSDU. If both first_msdu 300 and last_msdu are set in the MSDU then this is a 301 non-aggregated MSDU frame: normal MPDU. Interior MSDU in an 302 A-MSDU shall have both first_mpdu and last_mpdu bits set to 303 0. 304 305 last_msdu 306 307 Indicates the last MSDU of the A-MSDU. MPDU end status 308 is only valid when last_msdu is set. 309 310 sa_idx_timeout 311 312 Indicates an unsuccessful MAC source address search due 313 to the expiring of the search timer. 314 315 da_idx_timeout 316 317 Indicates an unsuccessful MAC destination address search 318 due to the expiring of the search timer. 319 320 msdu_limit_error 321 322 Indicates that the MSDU threshold was exceeded and thus 323 all the rest of the MSDUs will not be scattered and will not 324 be decapsulated but will be DMA'ed in RAW format as a single 325 MSDU buffer 326 327 flow_idx_timeout 328 329 Indicates an unsuccessful flow search due to the 330 expiring of the search timer. 331 332 <legal all> 333 334 flow_idx_invalid 335 336 flow id is not valid 337 338 <legal all> 339 340 wifi_parser_error 341 342 TODO: add details to the description 343 344 <legal all> 345 346 amsdu_parser_error 347 348 A-MSDU could not be properly de-agregated. 349 350 <legal all> 351 352 sa_is_valid 353 354 Indicates that OLE found a valid SA entry 355 356 da_is_valid 357 358 Indicates that OLE found a valid DA entry 359 360 da_is_mcbc 361 362 Field Only valid if da_is_valid is set 363 364 365 366 Indicates the DA address was a Multicast of Broadcast 367 address. 368 369 l3_header_padding 370 371 Number of bytes padded to make sure that the L3 header 372 will always start of a Dword boundary 373 374 reserved_5a 375 376 <legal 0> 377 378 ipv6_options_crc 379 380 32 bit CRC computed out of IP v6 extension headers 381 382 tcp_seq_number 383 384 TCP sequence number 385 386 tcp_ack_number 387 388 TCP acknowledge number 389 390 tcp_flag 391 392 TCP flags 393 394 {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} 395 396 lro_eligible 397 398 Computed out of TCP and IP fields to indicate that this 399 MSDU is eligible for LRO 400 401 reserved_9a 402 403 NOTE: DO not assign a field... Internally used in 404 RXOLE.. 405 406 <legal 0> 407 408 window_size 409 410 TCP receive window size 411 412 da_offset 413 414 Offset into MSDU buffer for DA 415 416 sa_offset 417 418 Offset into MSDU buffer for SA 419 420 da_offset_valid 421 422 da_offset field is valid. This will be set to 0 in case 423 of a dynamic A-MSDU when DA is compressed 424 425 sa_offset_valid 426 427 sa_offset field is valid. This will be set to 0 in case 428 of a dynamic A-MSDU when SA is compressed 429 430 type_offset 431 432 Offset into MSDU buffer for Type 433 434 reserved_10a 435 436 <legal 0> 437 438 rule_indication_31_0 439 440 Bitmap indicating which of rules 31-0 have matched 441 442 rule_indication_63_32 443 444 Bitmap indicating which of rules 63-32 have matched 445 446 sa_idx 447 448 The offset in the address table which matches the MAC 449 source address. 450 451 da_idx 452 453 The offset in the address table which matches the MAC 454 source address 455 456 msdu_drop 457 458 When set, REO shall drop this MSDU and not forward it to 459 any other ring... 460 461 <legal all> 462 463 reo_destination_indication 464 465 The ID of the REO exit ring where the MSDU frame shall 466 push after (MPDU level) reordering has finished. 467 468 469 470 <enum 0 reo_destination_tcl> Reo will push the frame 471 into the REO2TCL ring 472 473 <enum 1 reo_destination_sw1> Reo will push the frame 474 into the REO2SW1 ring 475 476 <enum 2 reo_destination_sw2> Reo will push the frame 477 into the REO2SW1 ring 478 479 <enum 3 reo_destination_sw3> Reo will push the frame 480 into the REO2SW1 ring 481 482 <enum 4 reo_destination_sw4> Reo will push the frame 483 into the REO2SW1 ring 484 485 <enum 5 reo_destination_release> Reo will push the frame 486 into the REO_release ring 487 488 <enum 6 reo_destination_fw> Reo will push the frame into 489 the REO2FW ring 490 491 <enum 7 reo_destination_7> REO remaps this 492 493 <enum 8 reo_destination_8> REO remaps this <enum 9 494 reo_destination_9> REO remaps this <enum 10 495 reo_destination_10> REO remaps this 496 497 <enum 11 reo_destination_11> REO remaps this 498 499 <enum 12 reo_destination_12> REO remaps this <enum 13 500 reo_destination_13> REO remaps this 501 502 <enum 14 reo_destination_14> REO remaps this 503 504 <enum 15 reo_destination_15> REO remaps this 505 506 <enum 16 reo_destination_16> REO remaps this 507 508 <enum 17 reo_destination_17> REO remaps this 509 510 <enum 18 reo_destination_18> REO remaps this 511 512 <enum 19 reo_destination_19> REO remaps this 513 514 <enum 20 reo_destination_20> REO remaps this 515 516 <enum 21 reo_destination_21> REO remaps this 517 518 <enum 22 reo_destination_22> REO remaps this 519 520 <enum 23 reo_destination_23> REO remaps this 521 522 <enum 24 reo_destination_24> REO remaps this 523 524 <enum 25 reo_destination_25> REO remaps this 525 526 <enum 26 reo_destination_26> REO remaps this 527 528 <enum 27 reo_destination_27> REO remaps this 529 530 <enum 28 reo_destination_28> REO remaps this 531 532 <enum 29 reo_destination_29> REO remaps this 533 534 <enum 30 reo_destination_30> REO remaps this 535 536 <enum 31 reo_destination_31> REO remaps this 537 538 539 540 <legal all> 541 542 flow_idx 543 544 Flow table index 545 546 <legal all> 547 548 reserved_14 549 550 <legal 0> 551 552 fse_metadata 553 554 FSE related meta data: 555 556 <legal all> 557 558 cce_metadata 559 560 CCE related meta data: 561 562 <legal all> 563 564 sa_sw_peer_id 565 566 sw_peer_id from the address search entry corresponding 567 to the source address of the MSDU 568 569 <legal 0> 570 */ 571 572 573 /* Description RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY 574 575 Field indicates what the reason was that this MPDU frame 576 was allowed to come into the receive path by RXPCU 577 578 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 579 frame filter programming of rxpcu 580 581 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 582 regular frame filter and would have been dropped, were it 583 not for the frame fitting into the 'monitor_client' 584 category. 585 586 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 587 regular frame filter and also did not pass the 588 rxpcu_monitor_client filter. It would have been dropped 589 accept that it did pass the 'monitor_other' category. 590 591 <legal 0-2> 592 */ 593 #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 594 #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 595 #define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 596 597 /* Description RX_MSDU_END_0_SW_FRAME_GROUP_ID 598 599 SW processes frames based on certain classifications. 600 This field indicates to what sw classification this MPDU is 601 mapped. 602 603 The classification is given in priority order 604 605 606 607 <enum 0 sw_frame_group_NDP_frame> 608 609 610 611 <enum 1 sw_frame_group_Multicast_data> 612 613 <enum 2 sw_frame_group_Unicast_data> 614 615 <enum 3 sw_frame_group_Null_data > This includes mpdus 616 of type Data Null as well as QoS Data Null 617 618 619 620 <enum 4 sw_frame_group_mgmt_0000 > 621 622 <enum 5 sw_frame_group_mgmt_0001 > 623 624 <enum 6 sw_frame_group_mgmt_0010 > 625 626 <enum 7 sw_frame_group_mgmt_0011 > 627 628 <enum 8 sw_frame_group_mgmt_0100 > 629 630 <enum 9 sw_frame_group_mgmt_0101 > 631 632 <enum 10 sw_frame_group_mgmt_0110 > 633 634 <enum 11 sw_frame_group_mgmt_0111 > 635 636 <enum 12 sw_frame_group_mgmt_1000 > 637 638 <enum 13 sw_frame_group_mgmt_1001 > 639 640 <enum 14 sw_frame_group_mgmt_1010 > 641 642 <enum 15 sw_frame_group_mgmt_1011 > 643 644 <enum 16 sw_frame_group_mgmt_1100 > 645 646 <enum 17 sw_frame_group_mgmt_1101 > 647 648 <enum 18 sw_frame_group_mgmt_1110 > 649 650 <enum 19 sw_frame_group_mgmt_1111 > 651 652 653 654 <enum 20 sw_frame_group_ctrl_0000 > 655 656 <enum 21 sw_frame_group_ctrl_0001 > 657 658 <enum 22 sw_frame_group_ctrl_0010 > 659 660 <enum 23 sw_frame_group_ctrl_0011 > 661 662 <enum 24 sw_frame_group_ctrl_0100 > 663 664 <enum 25 sw_frame_group_ctrl_0101 > 665 666 <enum 26 sw_frame_group_ctrl_0110 > 667 668 <enum 27 sw_frame_group_ctrl_0111 > 669 670 <enum 28 sw_frame_group_ctrl_1000 > 671 672 <enum 29 sw_frame_group_ctrl_1001 > 673 674 <enum 30 sw_frame_group_ctrl_1010 > 675 676 <enum 31 sw_frame_group_ctrl_1011 > 677 678 <enum 32 sw_frame_group_ctrl_1100 > 679 680 <enum 33 sw_frame_group_ctrl_1101 > 681 682 <enum 34 sw_frame_group_ctrl_1110 > 683 684 <enum 35 sw_frame_group_ctrl_1111 > 685 686 687 688 <enum 36 sw_frame_group_unsupported> This covers type 3 689 and protocol version != 0 690 691 692 693 694 695 696 <legal 0-37> 697 */ 698 #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 699 #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_LSB 2 700 #define RX_MSDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc 701 702 /* Description RX_MSDU_END_0_RESERVED_0 703 704 <legal 0> 705 */ 706 #define RX_MSDU_END_0_RESERVED_0_OFFSET 0x00000000 707 #define RX_MSDU_END_0_RESERVED_0_LSB 9 708 #define RX_MSDU_END_0_RESERVED_0_MASK 0x0000fe00 709 710 /* Description RX_MSDU_END_0_PHY_PPDU_ID 711 712 A ppdu counter value that PHY increments for every PPDU 713 received. The counter value wraps around 714 715 <legal all> 716 */ 717 #define RX_MSDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000 718 #define RX_MSDU_END_0_PHY_PPDU_ID_LSB 16 719 #define RX_MSDU_END_0_PHY_PPDU_ID_MASK 0xffff0000 720 721 /* Description RX_MSDU_END_1_IP_HDR_CHKSUM 722 723 This can include the IP header checksum or the pseudo 724 header checksum used by TCP/UDP checksum. 725 */ 726 #define RX_MSDU_END_1_IP_HDR_CHKSUM_OFFSET 0x00000004 727 #define RX_MSDU_END_1_IP_HDR_CHKSUM_LSB 0 728 #define RX_MSDU_END_1_IP_HDR_CHKSUM_MASK 0x0000ffff 729 730 /* Description RX_MSDU_END_1_TCP_UDP_CHKSUM 731 732 The value of the computed TCP/UDP checksum. A mode bit 733 selects whether this checksum is the full checksum or the 734 partial checksum which does not include the pseudo header. 735 */ 736 #define RX_MSDU_END_1_TCP_UDP_CHKSUM_OFFSET 0x00000004 737 #define RX_MSDU_END_1_TCP_UDP_CHKSUM_LSB 16 738 #define RX_MSDU_END_1_TCP_UDP_CHKSUM_MASK 0xffff0000 739 740 /* Description RX_MSDU_END_2_KEY_ID_OCTET 741 742 The key ID octet from the IV. Only valid when 743 first_msdu is set. 744 */ 745 #define RX_MSDU_END_2_KEY_ID_OCTET_OFFSET 0x00000008 746 #define RX_MSDU_END_2_KEY_ID_OCTET_LSB 0 747 #define RX_MSDU_END_2_KEY_ID_OCTET_MASK 0x000000ff 748 749 /* Description RX_MSDU_END_2_CCE_SUPER_RULE 750 751 Indicates the super filter rule 752 */ 753 #define RX_MSDU_END_2_CCE_SUPER_RULE_OFFSET 0x00000008 754 #define RX_MSDU_END_2_CCE_SUPER_RULE_LSB 8 755 #define RX_MSDU_END_2_CCE_SUPER_RULE_MASK 0x00003f00 756 757 /* Description RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE 758 759 Classification failed due to truncated frame 760 */ 761 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x00000008 762 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 763 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x00004000 764 765 /* Description RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS 766 767 Classification failed due to CCE global disable 768 */ 769 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x00000008 770 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 771 #define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x00008000 772 773 /* Description RX_MSDU_END_2_EXT_WAPI_PN_63_48 774 775 Extension PN (packet number) which is only used by WAPI. 776 This corresponds to WAPI PN bits [63:48] (pn6 and pn7). 777 The WAPI PN bits [63:0] are in the pn field of the 778 rx_mpdu_start descriptor. 779 */ 780 #define RX_MSDU_END_2_EXT_WAPI_PN_63_48_OFFSET 0x00000008 781 #define RX_MSDU_END_2_EXT_WAPI_PN_63_48_LSB 16 782 #define RX_MSDU_END_2_EXT_WAPI_PN_63_48_MASK 0xffff0000 783 784 /* Description RX_MSDU_END_3_EXT_WAPI_PN_95_64 785 786 Extension PN (packet number) which is only used by WAPI. 787 This corresponds to WAPI PN bits [95:64] (pn8, pn9, pn10 788 and pn11). 789 */ 790 #define RX_MSDU_END_3_EXT_WAPI_PN_95_64_OFFSET 0x0000000c 791 #define RX_MSDU_END_3_EXT_WAPI_PN_95_64_LSB 0 792 #define RX_MSDU_END_3_EXT_WAPI_PN_95_64_MASK 0xffffffff 793 794 /* Description RX_MSDU_END_4_EXT_WAPI_PN_127_96 795 796 Extension PN (packet number) which is only used by WAPI. 797 This corresponds to WAPI PN bits [127:96] (pn12, pn13, 798 pn14, pn15). 799 */ 800 #define RX_MSDU_END_4_EXT_WAPI_PN_127_96_OFFSET 0x00000010 801 #define RX_MSDU_END_4_EXT_WAPI_PN_127_96_LSB 0 802 #define RX_MSDU_END_4_EXT_WAPI_PN_127_96_MASK 0xffffffff 803 804 /* Description RX_MSDU_END_5_REPORTED_MPDU_LENGTH 805 806 MPDU length before decapsulation. Only valid when 807 first_msdu is set. This field is taken directly from the 808 length field of the A-MPDU delimiter or the preamble length 809 field for non-A-MPDU frames. 810 */ 811 #define RX_MSDU_END_5_REPORTED_MPDU_LENGTH_OFFSET 0x00000014 812 #define RX_MSDU_END_5_REPORTED_MPDU_LENGTH_LSB 0 813 #define RX_MSDU_END_5_REPORTED_MPDU_LENGTH_MASK 0x00003fff 814 815 /* Description RX_MSDU_END_5_FIRST_MSDU 816 817 Indicates the first MSDU of A-MSDU. If both first_msdu 818 and last_msdu are set in the MSDU then this is a 819 non-aggregated MSDU frame: normal MPDU. Interior MSDU in an 820 A-MSDU shall have both first_mpdu and last_mpdu bits set to 821 0. 822 */ 823 #define RX_MSDU_END_5_FIRST_MSDU_OFFSET 0x00000014 824 #define RX_MSDU_END_5_FIRST_MSDU_LSB 14 825 #define RX_MSDU_END_5_FIRST_MSDU_MASK 0x00004000 826 827 /* Description RX_MSDU_END_5_LAST_MSDU 828 829 Indicates the last MSDU of the A-MSDU. MPDU end status 830 is only valid when last_msdu is set. 831 */ 832 #define RX_MSDU_END_5_LAST_MSDU_OFFSET 0x00000014 833 #define RX_MSDU_END_5_LAST_MSDU_LSB 15 834 #define RX_MSDU_END_5_LAST_MSDU_MASK 0x00008000 835 836 /* Description RX_MSDU_END_5_SA_IDX_TIMEOUT 837 838 Indicates an unsuccessful MAC source address search due 839 to the expiring of the search timer. 840 */ 841 #define RX_MSDU_END_5_SA_IDX_TIMEOUT_OFFSET 0x00000014 842 #define RX_MSDU_END_5_SA_IDX_TIMEOUT_LSB 16 843 #define RX_MSDU_END_5_SA_IDX_TIMEOUT_MASK 0x00010000 844 845 /* Description RX_MSDU_END_5_DA_IDX_TIMEOUT 846 847 Indicates an unsuccessful MAC destination address search 848 due to the expiring of the search timer. 849 */ 850 #define RX_MSDU_END_5_DA_IDX_TIMEOUT_OFFSET 0x00000014 851 #define RX_MSDU_END_5_DA_IDX_TIMEOUT_LSB 17 852 #define RX_MSDU_END_5_DA_IDX_TIMEOUT_MASK 0x00020000 853 854 /* Description RX_MSDU_END_5_MSDU_LIMIT_ERROR 855 856 Indicates that the MSDU threshold was exceeded and thus 857 all the rest of the MSDUs will not be scattered and will not 858 be decapsulated but will be DMA'ed in RAW format as a single 859 MSDU buffer 860 */ 861 #define RX_MSDU_END_5_MSDU_LIMIT_ERROR_OFFSET 0x00000014 862 #define RX_MSDU_END_5_MSDU_LIMIT_ERROR_LSB 18 863 #define RX_MSDU_END_5_MSDU_LIMIT_ERROR_MASK 0x00040000 864 865 /* Description RX_MSDU_END_5_FLOW_IDX_TIMEOUT 866 867 Indicates an unsuccessful flow search due to the 868 expiring of the search timer. 869 870 <legal all> 871 */ 872 #define RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET 0x00000014 873 #define RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB 19 874 #define RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK 0x00080000 875 876 /* Description RX_MSDU_END_5_FLOW_IDX_INVALID 877 878 flow id is not valid 879 880 <legal all> 881 */ 882 #define RX_MSDU_END_5_FLOW_IDX_INVALID_OFFSET 0x00000014 883 #define RX_MSDU_END_5_FLOW_IDX_INVALID_LSB 20 884 #define RX_MSDU_END_5_FLOW_IDX_INVALID_MASK 0x00100000 885 886 /* Description RX_MSDU_END_5_WIFI_PARSER_ERROR 887 888 TODO: add details to the description 889 890 <legal all> 891 */ 892 #define RX_MSDU_END_5_WIFI_PARSER_ERROR_OFFSET 0x00000014 893 #define RX_MSDU_END_5_WIFI_PARSER_ERROR_LSB 21 894 #define RX_MSDU_END_5_WIFI_PARSER_ERROR_MASK 0x00200000 895 896 /* Description RX_MSDU_END_5_AMSDU_PARSER_ERROR 897 898 A-MSDU could not be properly de-agregated. 899 900 <legal all> 901 */ 902 #define RX_MSDU_END_5_AMSDU_PARSER_ERROR_OFFSET 0x00000014 903 #define RX_MSDU_END_5_AMSDU_PARSER_ERROR_LSB 22 904 #define RX_MSDU_END_5_AMSDU_PARSER_ERROR_MASK 0x00400000 905 906 /* Description RX_MSDU_END_5_SA_IS_VALID 907 908 Indicates that OLE found a valid SA entry 909 */ 910 #define RX_MSDU_END_5_SA_IS_VALID_OFFSET 0x00000014 911 #define RX_MSDU_END_5_SA_IS_VALID_LSB 23 912 #define RX_MSDU_END_5_SA_IS_VALID_MASK 0x00800000 913 914 /* Description RX_MSDU_END_5_DA_IS_VALID 915 916 Indicates that OLE found a valid DA entry 917 */ 918 #define RX_MSDU_END_5_DA_IS_VALID_OFFSET 0x00000014 919 #define RX_MSDU_END_5_DA_IS_VALID_LSB 24 920 #define RX_MSDU_END_5_DA_IS_VALID_MASK 0x01000000 921 922 /* Description RX_MSDU_END_5_DA_IS_MCBC 923 924 Field Only valid if da_is_valid is set 925 926 927 928 Indicates the DA address was a Multicast of Broadcast 929 address. 930 */ 931 #define RX_MSDU_END_5_DA_IS_MCBC_OFFSET 0x00000014 932 #define RX_MSDU_END_5_DA_IS_MCBC_LSB 25 933 #define RX_MSDU_END_5_DA_IS_MCBC_MASK 0x02000000 934 935 /* Description RX_MSDU_END_5_L3_HEADER_PADDING 936 937 Number of bytes padded to make sure that the L3 header 938 will always start of a Dword boundary 939 */ 940 #define RX_MSDU_END_5_L3_HEADER_PADDING_OFFSET 0x00000014 941 #define RX_MSDU_END_5_L3_HEADER_PADDING_LSB 26 942 #define RX_MSDU_END_5_L3_HEADER_PADDING_MASK 0x0c000000 943 944 /* Description RX_MSDU_END_5_RESERVED_5A 945 946 <legal 0> 947 */ 948 #define RX_MSDU_END_5_RESERVED_5A_OFFSET 0x00000014 949 #define RX_MSDU_END_5_RESERVED_5A_LSB 28 950 #define RX_MSDU_END_5_RESERVED_5A_MASK 0xf0000000 951 952 /* Description RX_MSDU_END_6_IPV6_OPTIONS_CRC 953 954 32 bit CRC computed out of IP v6 extension headers 955 */ 956 #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_OFFSET 0x00000018 957 #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_LSB 0 958 #define RX_MSDU_END_6_IPV6_OPTIONS_CRC_MASK 0xffffffff 959 960 /* Description RX_MSDU_END_7_TCP_SEQ_NUMBER 961 962 TCP sequence number 963 */ 964 #define RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET 0x0000001c 965 #define RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB 0 966 #define RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK 0xffffffff 967 968 /* Description RX_MSDU_END_8_TCP_ACK_NUMBER 969 970 TCP acknowledge number 971 */ 972 #define RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET 0x00000020 973 #define RX_MSDU_END_8_TCP_ACK_NUMBER_LSB 0 974 #define RX_MSDU_END_8_TCP_ACK_NUMBER_MASK 0xffffffff 975 976 /* Description RX_MSDU_END_9_TCP_FLAG 977 978 TCP flags 979 980 {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} 981 */ 982 #define RX_MSDU_END_9_TCP_FLAG_OFFSET 0x00000024 983 #define RX_MSDU_END_9_TCP_FLAG_LSB 0 984 #define RX_MSDU_END_9_TCP_FLAG_MASK 0x000001ff 985 986 /* Description RX_MSDU_END_9_LRO_ELIGIBLE 987 988 Computed out of TCP and IP fields to indicate that this 989 MSDU is eligible for LRO 990 */ 991 #define RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET 0x00000024 992 #define RX_MSDU_END_9_LRO_ELIGIBLE_LSB 9 993 #define RX_MSDU_END_9_LRO_ELIGIBLE_MASK 0x00000200 994 995 /* Description RX_MSDU_END_9_RESERVED_9A 996 997 NOTE: DO not assign a field... Internally used in 998 RXOLE.. 999 1000 <legal 0> 1001 */ 1002 #define RX_MSDU_END_9_RESERVED_9A_OFFSET 0x00000024 1003 #define RX_MSDU_END_9_RESERVED_9A_LSB 10 1004 #define RX_MSDU_END_9_RESERVED_9A_MASK 0x0000fc00 1005 1006 /* Description RX_MSDU_END_9_WINDOW_SIZE 1007 1008 TCP receive window size 1009 */ 1010 #define RX_MSDU_END_9_WINDOW_SIZE_OFFSET 0x00000024 1011 #define RX_MSDU_END_9_WINDOW_SIZE_LSB 16 1012 #define RX_MSDU_END_9_WINDOW_SIZE_MASK 0xffff0000 1013 1014 /* Description RX_MSDU_END_10_DA_OFFSET 1015 1016 Offset into MSDU buffer for DA 1017 */ 1018 #define RX_MSDU_END_10_DA_OFFSET_OFFSET 0x00000028 1019 #define RX_MSDU_END_10_DA_OFFSET_LSB 0 1020 #define RX_MSDU_END_10_DA_OFFSET_MASK 0x0000003f 1021 1022 /* Description RX_MSDU_END_10_SA_OFFSET 1023 1024 Offset into MSDU buffer for SA 1025 */ 1026 #define RX_MSDU_END_10_SA_OFFSET_OFFSET 0x00000028 1027 #define RX_MSDU_END_10_SA_OFFSET_LSB 6 1028 #define RX_MSDU_END_10_SA_OFFSET_MASK 0x00000fc0 1029 1030 /* Description RX_MSDU_END_10_DA_OFFSET_VALID 1031 1032 da_offset field is valid. This will be set to 0 in case 1033 of a dynamic A-MSDU when DA is compressed 1034 */ 1035 #define RX_MSDU_END_10_DA_OFFSET_VALID_OFFSET 0x00000028 1036 #define RX_MSDU_END_10_DA_OFFSET_VALID_LSB 12 1037 #define RX_MSDU_END_10_DA_OFFSET_VALID_MASK 0x00001000 1038 1039 /* Description RX_MSDU_END_10_SA_OFFSET_VALID 1040 1041 sa_offset field is valid. This will be set to 0 in case 1042 of a dynamic A-MSDU when SA is compressed 1043 */ 1044 #define RX_MSDU_END_10_SA_OFFSET_VALID_OFFSET 0x00000028 1045 #define RX_MSDU_END_10_SA_OFFSET_VALID_LSB 13 1046 #define RX_MSDU_END_10_SA_OFFSET_VALID_MASK 0x00002000 1047 1048 /* Description RX_MSDU_END_10_TYPE_OFFSET 1049 1050 Offset into MSDU buffer for Type 1051 */ 1052 #define RX_MSDU_END_10_TYPE_OFFSET_OFFSET 0x00000028 1053 #define RX_MSDU_END_10_TYPE_OFFSET_LSB 14 1054 #define RX_MSDU_END_10_TYPE_OFFSET_MASK 0x001fc000 1055 1056 /* Description RX_MSDU_END_10_RESERVED_10A 1057 1058 <legal 0> 1059 */ 1060 #define RX_MSDU_END_10_RESERVED_10A_OFFSET 0x00000028 1061 #define RX_MSDU_END_10_RESERVED_10A_LSB 21 1062 #define RX_MSDU_END_10_RESERVED_10A_MASK 0xffe00000 1063 1064 /* Description RX_MSDU_END_11_RULE_INDICATION_31_0 1065 1066 Bitmap indicating which of rules 31-0 have matched 1067 */ 1068 #define RX_MSDU_END_11_RULE_INDICATION_31_0_OFFSET 0x0000002c 1069 #define RX_MSDU_END_11_RULE_INDICATION_31_0_LSB 0 1070 #define RX_MSDU_END_11_RULE_INDICATION_31_0_MASK 0xffffffff 1071 1072 /* Description RX_MSDU_END_12_RULE_INDICATION_63_32 1073 1074 Bitmap indicating which of rules 63-32 have matched 1075 */ 1076 #define RX_MSDU_END_12_RULE_INDICATION_63_32_OFFSET 0x00000030 1077 #define RX_MSDU_END_12_RULE_INDICATION_63_32_LSB 0 1078 #define RX_MSDU_END_12_RULE_INDICATION_63_32_MASK 0xffffffff 1079 1080 /* Description RX_MSDU_END_13_SA_IDX 1081 1082 The offset in the address table which matches the MAC 1083 source address. 1084 */ 1085 #define RX_MSDU_END_13_SA_IDX_OFFSET 0x00000034 1086 #define RX_MSDU_END_13_SA_IDX_LSB 0 1087 #define RX_MSDU_END_13_SA_IDX_MASK 0x0000ffff 1088 1089 /* Description RX_MSDU_END_13_DA_IDX 1090 1091 The offset in the address table which matches the MAC 1092 source address 1093 */ 1094 #define RX_MSDU_END_13_DA_IDX_OFFSET 0x00000034 1095 #define RX_MSDU_END_13_DA_IDX_LSB 16 1096 #define RX_MSDU_END_13_DA_IDX_MASK 0xffff0000 1097 1098 /* Description RX_MSDU_END_14_MSDU_DROP 1099 1100 When set, REO shall drop this MSDU and not forward it to 1101 any other ring... 1102 1103 <legal all> 1104 */ 1105 #define RX_MSDU_END_14_MSDU_DROP_OFFSET 0x00000038 1106 #define RX_MSDU_END_14_MSDU_DROP_LSB 0 1107 #define RX_MSDU_END_14_MSDU_DROP_MASK 0x00000001 1108 1109 /* Description RX_MSDU_END_14_REO_DESTINATION_INDICATION 1110 1111 The ID of the REO exit ring where the MSDU frame shall 1112 push after (MPDU level) reordering has finished. 1113 1114 1115 1116 <enum 0 reo_destination_tcl> Reo will push the frame 1117 into the REO2TCL ring 1118 1119 <enum 1 reo_destination_sw1> Reo will push the frame 1120 into the REO2SW1 ring 1121 1122 <enum 2 reo_destination_sw2> Reo will push the frame 1123 into the REO2SW1 ring 1124 1125 <enum 3 reo_destination_sw3> Reo will push the frame 1126 into the REO2SW1 ring 1127 1128 <enum 4 reo_destination_sw4> Reo will push the frame 1129 into the REO2SW1 ring 1130 1131 <enum 5 reo_destination_release> Reo will push the frame 1132 into the REO_release ring 1133 1134 <enum 6 reo_destination_fw> Reo will push the frame into 1135 the REO2FW ring 1136 1137 <enum 7 reo_destination_7> REO remaps this 1138 1139 <enum 8 reo_destination_8> REO remaps this <enum 9 1140 reo_destination_9> REO remaps this <enum 10 1141 reo_destination_10> REO remaps this 1142 1143 <enum 11 reo_destination_11> REO remaps this 1144 1145 <enum 12 reo_destination_12> REO remaps this <enum 13 1146 reo_destination_13> REO remaps this 1147 1148 <enum 14 reo_destination_14> REO remaps this 1149 1150 <enum 15 reo_destination_15> REO remaps this 1151 1152 <enum 16 reo_destination_16> REO remaps this 1153 1154 <enum 17 reo_destination_17> REO remaps this 1155 1156 <enum 18 reo_destination_18> REO remaps this 1157 1158 <enum 19 reo_destination_19> REO remaps this 1159 1160 <enum 20 reo_destination_20> REO remaps this 1161 1162 <enum 21 reo_destination_21> REO remaps this 1163 1164 <enum 22 reo_destination_22> REO remaps this 1165 1166 <enum 23 reo_destination_23> REO remaps this 1167 1168 <enum 24 reo_destination_24> REO remaps this 1169 1170 <enum 25 reo_destination_25> REO remaps this 1171 1172 <enum 26 reo_destination_26> REO remaps this 1173 1174 <enum 27 reo_destination_27> REO remaps this 1175 1176 <enum 28 reo_destination_28> REO remaps this 1177 1178 <enum 29 reo_destination_29> REO remaps this 1179 1180 <enum 30 reo_destination_30> REO remaps this 1181 1182 <enum 31 reo_destination_31> REO remaps this 1183 1184 1185 1186 <legal all> 1187 */ 1188 #define RX_MSDU_END_14_REO_DESTINATION_INDICATION_OFFSET 0x00000038 1189 #define RX_MSDU_END_14_REO_DESTINATION_INDICATION_LSB 1 1190 #define RX_MSDU_END_14_REO_DESTINATION_INDICATION_MASK 0x0000003e 1191 1192 /* Description RX_MSDU_END_14_FLOW_IDX 1193 1194 Flow table index 1195 1196 <legal all> 1197 */ 1198 #define RX_MSDU_END_14_FLOW_IDX_OFFSET 0x00000038 1199 #define RX_MSDU_END_14_FLOW_IDX_LSB 6 1200 #define RX_MSDU_END_14_FLOW_IDX_MASK 0x03ffffc0 1201 1202 /* Description RX_MSDU_END_14_RESERVED_14 1203 1204 <legal 0> 1205 */ 1206 #define RX_MSDU_END_14_RESERVED_14_OFFSET 0x00000038 1207 #define RX_MSDU_END_14_RESERVED_14_LSB 26 1208 #define RX_MSDU_END_14_RESERVED_14_MASK 0xfc000000 1209 1210 /* Description RX_MSDU_END_15_FSE_METADATA 1211 1212 FSE related meta data: 1213 1214 <legal all> 1215 */ 1216 #define RX_MSDU_END_15_FSE_METADATA_OFFSET 0x0000003c 1217 #define RX_MSDU_END_15_FSE_METADATA_LSB 0 1218 #define RX_MSDU_END_15_FSE_METADATA_MASK 0xffffffff 1219 1220 /* Description RX_MSDU_END_16_CCE_METADATA 1221 1222 CCE related meta data: 1223 1224 <legal all> 1225 */ 1226 #define RX_MSDU_END_16_CCE_METADATA_OFFSET 0x00000040 1227 #define RX_MSDU_END_16_CCE_METADATA_LSB 0 1228 #define RX_MSDU_END_16_CCE_METADATA_MASK 0x0000ffff 1229 1230 /* Description RX_MSDU_END_16_SA_SW_PEER_ID 1231 1232 sw_peer_id from the address search entry corresponding 1233 to the source address of the MSDU 1234 1235 <legal 0> 1236 */ 1237 #define RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET 0x00000040 1238 #define RX_MSDU_END_16_SA_SW_PEER_ID_LSB 16 1239 #define RX_MSDU_END_16_SA_SW_PEER_ID_MASK 0xffff0000 1240 1241 1242 #endif // _RX_MSDU_END_H_ 1243