1 /* 2 * Copyright (c) 2016 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // $ATH_LICENSE_HW_HDR_C$ 20 // 21 // DO NOT EDIT! This file is automatically generated 22 // These definitions are tied to a particular hardware layout 23 24 25 #ifndef _TCL_GSE_CMD_H_ 26 #define _TCL_GSE_CMD_H_ 27 #if !defined(__ASSEMBLER__) 28 #endif 29 30 31 // ################ START SUMMARY ################# 32 // 33 // Dword Fields 34 // 0 control_buffer_addr_31_0[31:0] 35 // 1 control_buffer_addr_39_32[7:0], gse_ctrl[11:8], gse_sel[12], status_destination_ring_id[13], swap[14], reserved_1a[31:15] 36 // 2 cmd_meta_data_31_0[31:0] 37 // 3 cmd_meta_data_63_32[31:0] 38 // 4 reserved_4a[31:0] 39 // 5 reserved_5a[31:0] 40 // 6 reserved_6a[19:0], ring_id[27:20], looping_count[31:28] 41 // 42 // ################ END SUMMARY ################# 43 44 #define NUM_OF_DWORDS_TCL_GSE_CMD 7 45 46 struct tcl_gse_cmd { 47 uint32_t control_buffer_addr_31_0 : 32; //[31:0] 48 uint32_t control_buffer_addr_39_32 : 8, //[7:0] 49 gse_ctrl : 4, //[11:8] 50 gse_sel : 1, //[12] 51 status_destination_ring_id : 1, //[13] 52 swap : 1, //[14] 53 reserved_1a : 17; //[31:15] 54 uint32_t cmd_meta_data_31_0 : 32; //[31:0] 55 uint32_t cmd_meta_data_63_32 : 32; //[31:0] 56 uint32_t reserved_4a : 32; //[31:0] 57 uint32_t reserved_5a : 32; //[31:0] 58 uint32_t reserved_6a : 20, //[19:0] 59 ring_id : 8, //[27:20] 60 looping_count : 4; //[31:28] 61 }; 62 63 /* 64 65 control_buffer_addr_31_0 66 67 Address (lower 32 bits) of a control buffer containing 68 additional info needed for this command execution. 69 70 <legal all> 71 72 control_buffer_addr_39_32 73 74 Address (upper 8 bits) of a control buffer containing 75 additional info needed for this command execution. 76 77 <legal all> 78 79 gse_ctrl 80 81 GSE control operations. This includes cache operations 82 and table entry statistics read/clear operation. 83 84 <enum 0 rd_stat> Report or Read statistics 85 86 <enum 1 srch_dis> Search disable. Report only Hash 87 88 <enum 2 Wr_bk_single> Write Back single entry 89 90 <enum 3 wr_bk_all> Write Back entire cache entry 91 92 <enum 4 inval_single> Invalidate single cache entry 93 94 <enum 5 inval_all> Invalidate entire cache 95 96 <enum 6 wr_bk_inval_single> Write back and Invalidate 97 single entry in cache 98 99 <enum 7 wr_bk_inval_all> write back and invalidate 100 entire cache 101 102 <enum 8 clr_stat_single> Clear statistics for single 103 entry 104 105 <legal 0-8> 106 107 Rest of the values reserved. 108 109 For all single entry control operations (write back, 110 Invalidate or both)Statistics will be reported 111 112 gse_sel 113 114 Bit to select the ASE or FSE to do the operation mention 115 by GSE_ctrl bit 116 117 0: FSE select 118 119 1: ASE select 120 121 status_destination_ring_id 122 123 The TCL status ring to which the GSE status needs to be 124 send. 125 126 127 128 <enum 0 tcl_status_0_ring> 129 130 <enum 1 tcl_status_1_ring> 131 132 133 134 <legal all> 135 136 swap 137 138 Bit to enable byte swapping of contents of buffer 139 140 <enum 0 Byte_swap_disable > 141 142 <enum 1 byte_swap_enable > 143 144 <legal all> 145 146 reserved_1a 147 148 <legal 0> 149 150 cmd_meta_data_31_0 151 152 Meta data to be returned in the status descriptor 153 154 <legal all> 155 156 cmd_meta_data_63_32 157 158 Meta data to be returned in the status descriptor 159 160 <legal all> 161 162 reserved_4a 163 164 <legal 0> 165 166 reserved_5a 167 168 <legal 0> 169 170 reserved_6a 171 172 <legal 0> 173 174 ring_id 175 176 Helps with debugging when dumping ring contents. 177 178 <legal all> 179 180 looping_count 181 182 A count value that indicates the number of times the 183 producer of entries into the Ring has looped around the 184 ring. 185 186 At initialization time, this value is set to 0. On the 187 first loop, this value is set to 1. After the max value is 188 reached allowed by the number of bits for this field, the 189 count value continues with 0 again. 190 191 192 193 In case SW is the consumer of the ring entries, it can 194 use this field to figure out up to where the producer of 195 entries has created new entries. This eliminates the need to 196 check where the head pointer' of the ring is located once 197 the SW starts processing an interrupt indicating that new 198 entries have been put into this ring... 199 200 201 202 Also note that SW if it wants only needs to look at the 203 LSB bit of this count value. 204 205 <legal all> 206 */ 207 208 209 /* Description TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0 210 211 Address (lower 32 bits) of a control buffer containing 212 additional info needed for this command execution. 213 214 <legal all> 215 */ 216 #define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000 217 #define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_LSB 0 218 #define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff 219 220 /* Description TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32 221 222 Address (upper 8 bits) of a control buffer containing 223 additional info needed for this command execution. 224 225 <legal all> 226 */ 227 #define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004 228 #define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_LSB 0 229 #define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff 230 231 /* Description TCL_GSE_CMD_1_GSE_CTRL 232 233 GSE control operations. This includes cache operations 234 and table entry statistics read/clear operation. 235 236 <enum 0 rd_stat> Report or Read statistics 237 238 <enum 1 srch_dis> Search disable. Report only Hash 239 240 <enum 2 Wr_bk_single> Write Back single entry 241 242 <enum 3 wr_bk_all> Write Back entire cache entry 243 244 <enum 4 inval_single> Invalidate single cache entry 245 246 <enum 5 inval_all> Invalidate entire cache 247 248 <enum 6 wr_bk_inval_single> Write back and Invalidate 249 single entry in cache 250 251 <enum 7 wr_bk_inval_all> write back and invalidate 252 entire cache 253 254 <enum 8 clr_stat_single> Clear statistics for single 255 entry 256 257 <legal 0-8> 258 259 Rest of the values reserved. 260 261 For all single entry control operations (write back, 262 Invalidate or both)Statistics will be reported 263 */ 264 #define TCL_GSE_CMD_1_GSE_CTRL_OFFSET 0x00000004 265 #define TCL_GSE_CMD_1_GSE_CTRL_LSB 8 266 #define TCL_GSE_CMD_1_GSE_CTRL_MASK 0x00000f00 267 268 /* Description TCL_GSE_CMD_1_GSE_SEL 269 270 Bit to select the ASE or FSE to do the operation mention 271 by GSE_ctrl bit 272 273 0: FSE select 274 275 1: ASE select 276 */ 277 #define TCL_GSE_CMD_1_GSE_SEL_OFFSET 0x00000004 278 #define TCL_GSE_CMD_1_GSE_SEL_LSB 12 279 #define TCL_GSE_CMD_1_GSE_SEL_MASK 0x00001000 280 281 /* Description TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID 282 283 The TCL status ring to which the GSE status needs to be 284 send. 285 286 287 288 <enum 0 tcl_status_0_ring> 289 290 <enum 1 tcl_status_1_ring> 291 292 293 294 <legal all> 295 */ 296 #define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004 297 #define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_LSB 13 298 #define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_MASK 0x00002000 299 300 /* Description TCL_GSE_CMD_1_SWAP 301 302 Bit to enable byte swapping of contents of buffer 303 304 <enum 0 Byte_swap_disable > 305 306 <enum 1 byte_swap_enable > 307 308 <legal all> 309 */ 310 #define TCL_GSE_CMD_1_SWAP_OFFSET 0x00000004 311 #define TCL_GSE_CMD_1_SWAP_LSB 14 312 #define TCL_GSE_CMD_1_SWAP_MASK 0x00004000 313 314 /* Description TCL_GSE_CMD_1_RESERVED_1A 315 316 <legal 0> 317 */ 318 #define TCL_GSE_CMD_1_RESERVED_1A_OFFSET 0x00000004 319 #define TCL_GSE_CMD_1_RESERVED_1A_LSB 15 320 #define TCL_GSE_CMD_1_RESERVED_1A_MASK 0xffff8000 321 322 /* Description TCL_GSE_CMD_2_CMD_META_DATA_31_0 323 324 Meta data to be returned in the status descriptor 325 326 <legal all> 327 */ 328 #define TCL_GSE_CMD_2_CMD_META_DATA_31_0_OFFSET 0x00000008 329 #define TCL_GSE_CMD_2_CMD_META_DATA_31_0_LSB 0 330 #define TCL_GSE_CMD_2_CMD_META_DATA_31_0_MASK 0xffffffff 331 332 /* Description TCL_GSE_CMD_3_CMD_META_DATA_63_32 333 334 Meta data to be returned in the status descriptor 335 336 <legal all> 337 */ 338 #define TCL_GSE_CMD_3_CMD_META_DATA_63_32_OFFSET 0x0000000c 339 #define TCL_GSE_CMD_3_CMD_META_DATA_63_32_LSB 0 340 #define TCL_GSE_CMD_3_CMD_META_DATA_63_32_MASK 0xffffffff 341 342 /* Description TCL_GSE_CMD_4_RESERVED_4A 343 344 <legal 0> 345 */ 346 #define TCL_GSE_CMD_4_RESERVED_4A_OFFSET 0x00000010 347 #define TCL_GSE_CMD_4_RESERVED_4A_LSB 0 348 #define TCL_GSE_CMD_4_RESERVED_4A_MASK 0xffffffff 349 350 /* Description TCL_GSE_CMD_5_RESERVED_5A 351 352 <legal 0> 353 */ 354 #define TCL_GSE_CMD_5_RESERVED_5A_OFFSET 0x00000014 355 #define TCL_GSE_CMD_5_RESERVED_5A_LSB 0 356 #define TCL_GSE_CMD_5_RESERVED_5A_MASK 0xffffffff 357 358 /* Description TCL_GSE_CMD_6_RESERVED_6A 359 360 <legal 0> 361 */ 362 #define TCL_GSE_CMD_6_RESERVED_6A_OFFSET 0x00000018 363 #define TCL_GSE_CMD_6_RESERVED_6A_LSB 0 364 #define TCL_GSE_CMD_6_RESERVED_6A_MASK 0x000fffff 365 366 /* Description TCL_GSE_CMD_6_RING_ID 367 368 Helps with debugging when dumping ring contents. 369 370 <legal all> 371 */ 372 #define TCL_GSE_CMD_6_RING_ID_OFFSET 0x00000018 373 #define TCL_GSE_CMD_6_RING_ID_LSB 20 374 #define TCL_GSE_CMD_6_RING_ID_MASK 0x0ff00000 375 376 /* Description TCL_GSE_CMD_6_LOOPING_COUNT 377 378 A count value that indicates the number of times the 379 producer of entries into the Ring has looped around the 380 ring. 381 382 At initialization time, this value is set to 0. On the 383 first loop, this value is set to 1. After the max value is 384 reached allowed by the number of bits for this field, the 385 count value continues with 0 again. 386 387 388 389 In case SW is the consumer of the ring entries, it can 390 use this field to figure out up to where the producer of 391 entries has created new entries. This eliminates the need to 392 check where the head pointer' of the ring is located once 393 the SW starts processing an interrupt indicating that new 394 entries have been put into this ring... 395 396 397 398 Also note that SW if it wants only needs to look at the 399 LSB bit of this count value. 400 401 <legal all> 402 */ 403 #define TCL_GSE_CMD_6_LOOPING_COUNT_OFFSET 0x00000018 404 #define TCL_GSE_CMD_6_LOOPING_COUNT_LSB 28 405 #define TCL_GSE_CMD_6_LOOPING_COUNT_MASK 0xf0000000 406 407 408 #endif // _TCL_GSE_CMD_H_ 409