1 /* 2 * Copyright (c) 2016 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for 5 * any purpose with or without fee is hereby granted, provided that the 6 * above copyright notice and this permission notice appear in all 7 * copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 16 * PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 // $ATH_LICENSE_HW_HDR_C$ 20 // 21 // DO NOT EDIT! This file is automatically generated 22 // These definitions are tied to a particular hardware layout 23 24 25 #ifndef _TX_MSDU_EXTENSION_H_ 26 #define _TX_MSDU_EXTENSION_H_ 27 #if !defined(__ASSEMBLER__) 28 #endif 29 30 31 // ################ START SUMMARY ################# 32 // 33 // Dword Fields 34 // 0 tso_enable[0], ipv4_checksum_en[1], udp_over_ipv4_checksum_en[2], udp_over_ipv6_checksum_en[3], tcp_over_ipv4_checksum_en[4], tcp_over_ipv6_checksum_en[5], reserved_0a[6], tcp_flag[15:7], tcp_flag_mask[24:16], reserved_0b[31:25] 35 // 1 l2_length[15:0], ip_length[31:16] 36 // 2 tcp_seq_number[31:0] 37 // 3 ip_identification[15:0], udp_length[31:16] 38 // 4 checksum_offset[13:0], partial_checksum_en[14], reserved_4a[15], payload_start_offset[29:16], reserved_4b[31:30] 39 // 5 payload_end_offset[13:0], reserved_5a[15:14], wds[16], reserved_5b[31:17] 40 // 6 buf0_ptr_31_0[31:0] 41 // 7 buf0_ptr_39_32[7:0], reserved_7a[15:8], buf0_len[31:16] 42 // 8 buf1_ptr_31_0[31:0] 43 // 9 buf1_ptr_39_32[7:0], reserved_9a[15:8], buf1_len[31:16] 44 // 10 buf2_ptr_31_0[31:0] 45 // 11 buf2_ptr_39_32[7:0], reserved_11a[15:8], buf2_len[31:16] 46 // 12 buf3_ptr_31_0[31:0] 47 // 13 buf3_ptr_39_32[7:0], reserved_13a[15:8], buf3_len[31:16] 48 // 14 buf4_ptr_31_0[31:0] 49 // 15 buf4_ptr_39_32[7:0], reserved_15a[15:8], buf4_len[31:16] 50 // 16 buf5_ptr_31_0[31:0] 51 // 17 buf5_ptr_39_32[7:0], reserved_17a[15:8], buf5_len[31:16] 52 // 53 // ################ END SUMMARY ################# 54 55 #define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 56 57 struct tx_msdu_extension { 58 uint32_t tso_enable : 1, //[0] 59 ipv4_checksum_en : 1, //[1] 60 udp_over_ipv4_checksum_en : 1, //[2] 61 udp_over_ipv6_checksum_en : 1, //[3] 62 tcp_over_ipv4_checksum_en : 1, //[4] 63 tcp_over_ipv6_checksum_en : 1, //[5] 64 reserved_0a : 1, //[6] 65 tcp_flag : 9, //[15:7] 66 tcp_flag_mask : 9, //[24:16] 67 reserved_0b : 7; //[31:25] 68 uint32_t l2_length : 16, //[15:0] 69 ip_length : 16; //[31:16] 70 uint32_t tcp_seq_number : 32; //[31:0] 71 uint32_t ip_identification : 16, //[15:0] 72 udp_length : 16; //[31:16] 73 uint32_t checksum_offset : 14, //[13:0] 74 partial_checksum_en : 1, //[14] 75 reserved_4a : 1, //[15] 76 payload_start_offset : 14, //[29:16] 77 reserved_4b : 2; //[31:30] 78 uint32_t payload_end_offset : 14, //[13:0] 79 reserved_5a : 2, //[15:14] 80 wds : 1, //[16] 81 reserved_5b : 15; //[31:17] 82 uint32_t buf0_ptr_31_0 : 32; //[31:0] 83 uint32_t buf0_ptr_39_32 : 8, //[7:0] 84 reserved_7a : 8, //[15:8] 85 buf0_len : 16; //[31:16] 86 uint32_t buf1_ptr_31_0 : 32; //[31:0] 87 uint32_t buf1_ptr_39_32 : 8, //[7:0] 88 reserved_9a : 8, //[15:8] 89 buf1_len : 16; //[31:16] 90 uint32_t buf2_ptr_31_0 : 32; //[31:0] 91 uint32_t buf2_ptr_39_32 : 8, //[7:0] 92 reserved_11a : 8, //[15:8] 93 buf2_len : 16; //[31:16] 94 uint32_t buf3_ptr_31_0 : 32; //[31:0] 95 uint32_t buf3_ptr_39_32 : 8, //[7:0] 96 reserved_13a : 8, //[15:8] 97 buf3_len : 16; //[31:16] 98 uint32_t buf4_ptr_31_0 : 32; //[31:0] 99 uint32_t buf4_ptr_39_32 : 8, //[7:0] 100 reserved_15a : 8, //[15:8] 101 buf4_len : 16; //[31:16] 102 uint32_t buf5_ptr_31_0 : 32; //[31:0] 103 uint32_t buf5_ptr_39_32 : 8, //[7:0] 104 reserved_17a : 8, //[15:8] 105 buf5_len : 16; //[31:16] 106 }; 107 108 /* 109 110 tso_enable 111 112 Enable transmit segmentation offload <legal all> 113 114 ipv4_checksum_en 115 116 Enable IPv4 checksum replacement 117 118 udp_over_ipv4_checksum_en 119 120 Enable UDP over IPv4 checksum replacement. UDP checksum 121 over IPv4 is optional for TCP/IP stacks. 122 123 udp_over_ipv6_checksum_en 124 125 Enable UDP over IPv6 checksum replacement. UDP checksum 126 over IPv6 is mandatory for TCP/IP stacks. 127 128 tcp_over_ipv4_checksum_en 129 130 Enable TCP checksum over IPv4 replacement 131 132 tcp_over_ipv6_checksum_en 133 134 Enable TCP checksum over IPv6 eplacement 135 136 reserved_0a 137 138 FW will set to 0, MAC will ignore. <legal 0> 139 140 tcp_flag 141 142 TCP flags 143 144 {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}<legal all> 145 146 tcp_flag_mask 147 148 TCP flag mask. Tcp_flag is inserted into the header 149 based on the mask, if tso is enabled 150 151 reserved_0b 152 153 FW will set to 0, MAC will ignore. <legal 0> 154 155 l2_length 156 157 L2 length for the msdu, if tso is enabled <legal all> 158 159 ip_length 160 161 Ip length for the msdu, if tso is enabled <legal all> 162 163 tcp_seq_number 164 165 Tcp_seq_number for the msdu, if tso is enabled <legal 166 all> 167 168 ip_identification 169 170 Ip_identification for the msdu, if tso is enabled <legal 171 all> 172 173 udp_length 174 175 TXDMA is copies this field into MSDU START TLV 176 177 checksum_offset 178 179 The calculated checksum from start offset to end offset 180 will be added to the checksum at the offset given by this 181 field<legal all> 182 183 partial_checksum_en 184 185 Partial Checksum Enable Bit. 186 187 <legal 0-1> 188 189 reserved_4a 190 191 <Legal 0> 192 193 payload_start_offset 194 195 L4 checksum calculations will start fromt this offset 196 197 <Legal all> 198 199 reserved_4b 200 201 <Legal 0> 202 203 payload_end_offset 204 205 L4 checksum calculations will end at this offset. 206 207 <Legal all> 208 209 reserved_5a 210 211 <Legal 0> 212 213 wds 214 215 If set the current packet is 4-address frame. Required 216 because an aggregate can include some frames with 3 address 217 format and other frames with 4 address format. Used by the 218 OLE during encapsulation. 219 220 Note: there is also global wds tx control in the 221 TX_PEER_ENTRY 222 223 <legal all> 224 225 reserved_5b 226 227 <Legal 0> 228 229 buf0_ptr_31_0 230 231 Lower 32 bits of the first buffer pointer 232 233 234 235 NOTE: SW/FW manages the 'cookie' info related to this 236 buffer together with the 'cookie' info for this 237 MSDU_EXTENSION descriptor 238 239 <legal all> 240 241 buf0_ptr_39_32 242 243 Upper 8 bits of the first buffer pointer <legal all> 244 245 reserved_7a 246 247 <Legal 0> 248 249 buf0_len 250 251 Length of the first buffer <legal all> 252 253 buf1_ptr_31_0 254 255 Lower 32 bits of the second buffer pointer 256 257 258 259 NOTE: SW/FW manages the 'cookie' info related to this 260 buffer together with the 'cookie' info for this 261 MSDU_EXTENSION descriptor 262 263 <legal all> 264 265 buf1_ptr_39_32 266 267 Upper 8 bits of the second buffer pointer <legal all> 268 269 reserved_9a 270 271 <Legal 0> 272 273 buf1_len 274 275 Length of the second buffer <legal all> 276 277 buf2_ptr_31_0 278 279 Lower 32 bits of the third buffer pointer 280 281 NOTE: SW/FW manages the 'cookie' info related to this 282 buffer together with the 'cookie' info for this 283 MSDU_EXTENSION descriptor 284 285 <legal all> 286 287 buf2_ptr_39_32 288 289 Upper 8 bits of the third buffer pointer <legal all> 290 291 reserved_11a 292 293 <Legal 0> 294 295 buf2_len 296 297 Length of the third buffer <legal all> 298 299 buf3_ptr_31_0 300 301 Lower 32 bits of the fourth buffer pointer 302 303 304 305 NOTE: SW/FW manages the 'cookie' info related to this 306 buffer together with the 'cookie' info for this 307 MSDU_EXTENSION descriptor 308 309 <legal all> 310 311 buf3_ptr_39_32 312 313 Upper 8 bits of the fourth buffer pointer <legal all> 314 315 reserved_13a 316 317 <Legal 0> 318 319 buf3_len 320 321 Length of the fourth buffer <legal all> 322 323 buf4_ptr_31_0 324 325 Lower 32 bits of the fifth buffer pointer 326 327 328 329 NOTE: SW/FW manages the 'cookie' info related to this 330 buffer together with the 'cookie' info for this 331 MSDU_EXTENSION descriptor 332 333 <legal all> 334 335 buf4_ptr_39_32 336 337 Upper 8 bits of the fifth buffer pointer <legal all> 338 339 reserved_15a 340 341 <Legal 0> 342 343 buf4_len 344 345 Length of the fifth buffer <legal all> 346 347 buf5_ptr_31_0 348 349 Lower 32 bits of the sixth buffer pointer 350 351 352 353 NOTE: SW/FW manages the 'cookie' info related to this 354 buffer together with the 'cookie' info for this 355 MSDU_EXTENSION descriptor 356 357 <legal all> 358 359 buf5_ptr_39_32 360 361 Upper 8 bits of the sixth buffer pointer <legal all> 362 363 reserved_17a 364 365 <Legal 0> 366 367 buf5_len 368 369 Length of the sixth buffer <legal all> 370 */ 371 372 373 /* Description TX_MSDU_EXTENSION_0_TSO_ENABLE 374 375 Enable transmit segmentation offload <legal all> 376 */ 377 #define TX_MSDU_EXTENSION_0_TSO_ENABLE_OFFSET 0x00000000 378 #define TX_MSDU_EXTENSION_0_TSO_ENABLE_LSB 0 379 #define TX_MSDU_EXTENSION_0_TSO_ENABLE_MASK 0x00000001 380 381 /* Description TX_MSDU_EXTENSION_0_IPV4_CHECKSUM_EN 382 383 Enable IPv4 checksum replacement 384 */ 385 #define TX_MSDU_EXTENSION_0_IPV4_CHECKSUM_EN_OFFSET 0x00000000 386 #define TX_MSDU_EXTENSION_0_IPV4_CHECKSUM_EN_LSB 1 387 #define TX_MSDU_EXTENSION_0_IPV4_CHECKSUM_EN_MASK 0x00000002 388 389 /* Description TX_MSDU_EXTENSION_0_UDP_OVER_IPV4_CHECKSUM_EN 390 391 Enable UDP over IPv4 checksum replacement. UDP checksum 392 over IPv4 is optional for TCP/IP stacks. 393 */ 394 #define TX_MSDU_EXTENSION_0_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000000 395 #define TX_MSDU_EXTENSION_0_UDP_OVER_IPV4_CHECKSUM_EN_LSB 2 396 #define TX_MSDU_EXTENSION_0_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00000004 397 398 /* Description TX_MSDU_EXTENSION_0_UDP_OVER_IPV6_CHECKSUM_EN 399 400 Enable UDP over IPv6 checksum replacement. UDP checksum 401 over IPv6 is mandatory for TCP/IP stacks. 402 */ 403 #define TX_MSDU_EXTENSION_0_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000000 404 #define TX_MSDU_EXTENSION_0_UDP_OVER_IPV6_CHECKSUM_EN_LSB 3 405 #define TX_MSDU_EXTENSION_0_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00000008 406 407 /* Description TX_MSDU_EXTENSION_0_TCP_OVER_IPV4_CHECKSUM_EN 408 409 Enable TCP checksum over IPv4 replacement 410 */ 411 #define TX_MSDU_EXTENSION_0_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000000 412 #define TX_MSDU_EXTENSION_0_TCP_OVER_IPV4_CHECKSUM_EN_LSB 4 413 #define TX_MSDU_EXTENSION_0_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x00000010 414 415 /* Description TX_MSDU_EXTENSION_0_TCP_OVER_IPV6_CHECKSUM_EN 416 417 Enable TCP checksum over IPv6 eplacement 418 */ 419 #define TX_MSDU_EXTENSION_0_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000000 420 #define TX_MSDU_EXTENSION_0_TCP_OVER_IPV6_CHECKSUM_EN_LSB 5 421 #define TX_MSDU_EXTENSION_0_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x00000020 422 423 /* Description TX_MSDU_EXTENSION_0_RESERVED_0A 424 425 FW will set to 0, MAC will ignore. <legal 0> 426 */ 427 #define TX_MSDU_EXTENSION_0_RESERVED_0A_OFFSET 0x00000000 428 #define TX_MSDU_EXTENSION_0_RESERVED_0A_LSB 6 429 #define TX_MSDU_EXTENSION_0_RESERVED_0A_MASK 0x00000040 430 431 /* Description TX_MSDU_EXTENSION_0_TCP_FLAG 432 433 TCP flags 434 435 {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}<legal all> 436 */ 437 #define TX_MSDU_EXTENSION_0_TCP_FLAG_OFFSET 0x00000000 438 #define TX_MSDU_EXTENSION_0_TCP_FLAG_LSB 7 439 #define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK 0x0000ff80 440 441 /* Description TX_MSDU_EXTENSION_0_TCP_FLAG_MASK 442 443 TCP flag mask. Tcp_flag is inserted into the header 444 based on the mask, if tso is enabled 445 */ 446 #define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_OFFSET 0x00000000 447 #define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_LSB 16 448 #define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_MASK 0x01ff0000 449 450 /* Description TX_MSDU_EXTENSION_0_RESERVED_0B 451 452 FW will set to 0, MAC will ignore. <legal 0> 453 */ 454 #define TX_MSDU_EXTENSION_0_RESERVED_0B_OFFSET 0x00000000 455 #define TX_MSDU_EXTENSION_0_RESERVED_0B_LSB 25 456 #define TX_MSDU_EXTENSION_0_RESERVED_0B_MASK 0xfe000000 457 458 /* Description TX_MSDU_EXTENSION_1_L2_LENGTH 459 460 L2 length for the msdu, if tso is enabled <legal all> 461 */ 462 #define TX_MSDU_EXTENSION_1_L2_LENGTH_OFFSET 0x00000004 463 #define TX_MSDU_EXTENSION_1_L2_LENGTH_LSB 0 464 #define TX_MSDU_EXTENSION_1_L2_LENGTH_MASK 0x0000ffff 465 466 /* Description TX_MSDU_EXTENSION_1_IP_LENGTH 467 468 Ip length for the msdu, if tso is enabled <legal all> 469 */ 470 #define TX_MSDU_EXTENSION_1_IP_LENGTH_OFFSET 0x00000004 471 #define TX_MSDU_EXTENSION_1_IP_LENGTH_LSB 16 472 #define TX_MSDU_EXTENSION_1_IP_LENGTH_MASK 0xffff0000 473 474 /* Description TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER 475 476 Tcp_seq_number for the msdu, if tso is enabled <legal 477 all> 478 */ 479 #define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_OFFSET 0x00000008 480 #define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_LSB 0 481 #define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_MASK 0xffffffff 482 483 /* Description TX_MSDU_EXTENSION_3_IP_IDENTIFICATION 484 485 Ip_identification for the msdu, if tso is enabled <legal 486 all> 487 */ 488 #define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_OFFSET 0x0000000c 489 #define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_LSB 0 490 #define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_MASK 0x0000ffff 491 492 /* Description TX_MSDU_EXTENSION_3_UDP_LENGTH 493 494 TXDMA is copies this field into MSDU START TLV 495 */ 496 #define TX_MSDU_EXTENSION_3_UDP_LENGTH_OFFSET 0x0000000c 497 #define TX_MSDU_EXTENSION_3_UDP_LENGTH_LSB 16 498 #define TX_MSDU_EXTENSION_3_UDP_LENGTH_MASK 0xffff0000 499 500 /* Description TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET 501 502 The calculated checksum from start offset to end offset 503 will be added to the checksum at the offset given by this 504 field<legal all> 505 */ 506 #define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_OFFSET 0x00000010 507 #define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_LSB 0 508 #define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_MASK 0x00003fff 509 510 /* Description TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN 511 512 Partial Checksum Enable Bit. 513 514 <legal 0-1> 515 */ 516 #define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010 517 #define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_LSB 14 518 #define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_MASK 0x00004000 519 520 /* Description TX_MSDU_EXTENSION_4_RESERVED_4A 521 522 <Legal 0> 523 */ 524 #define TX_MSDU_EXTENSION_4_RESERVED_4A_OFFSET 0x00000010 525 #define TX_MSDU_EXTENSION_4_RESERVED_4A_LSB 15 526 #define TX_MSDU_EXTENSION_4_RESERVED_4A_MASK 0x00008000 527 528 /* Description TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET 529 530 L4 checksum calculations will start fromt this offset 531 532 <Legal all> 533 */ 534 #define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_OFFSET 0x00000010 535 #define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_LSB 16 536 #define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_MASK 0x3fff0000 537 538 /* Description TX_MSDU_EXTENSION_4_RESERVED_4B 539 540 <Legal 0> 541 */ 542 #define TX_MSDU_EXTENSION_4_RESERVED_4B_OFFSET 0x00000010 543 #define TX_MSDU_EXTENSION_4_RESERVED_4B_LSB 30 544 #define TX_MSDU_EXTENSION_4_RESERVED_4B_MASK 0xc0000000 545 546 /* Description TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET 547 548 L4 checksum calculations will end at this offset. 549 550 <Legal all> 551 */ 552 #define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_OFFSET 0x00000014 553 #define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_LSB 0 554 #define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_MASK 0x00003fff 555 556 /* Description TX_MSDU_EXTENSION_5_RESERVED_5A 557 558 <Legal 0> 559 */ 560 #define TX_MSDU_EXTENSION_5_RESERVED_5A_OFFSET 0x00000014 561 #define TX_MSDU_EXTENSION_5_RESERVED_5A_LSB 14 562 #define TX_MSDU_EXTENSION_5_RESERVED_5A_MASK 0x0000c000 563 564 /* Description TX_MSDU_EXTENSION_5_WDS 565 566 If set the current packet is 4-address frame. Required 567 because an aggregate can include some frames with 3 address 568 format and other frames with 4 address format. Used by the 569 OLE during encapsulation. 570 571 Note: there is also global wds tx control in the 572 TX_PEER_ENTRY 573 574 <legal all> 575 */ 576 #define TX_MSDU_EXTENSION_5_WDS_OFFSET 0x00000014 577 #define TX_MSDU_EXTENSION_5_WDS_LSB 16 578 #define TX_MSDU_EXTENSION_5_WDS_MASK 0x00010000 579 580 /* Description TX_MSDU_EXTENSION_5_RESERVED_5B 581 582 <Legal 0> 583 */ 584 #define TX_MSDU_EXTENSION_5_RESERVED_5B_OFFSET 0x00000014 585 #define TX_MSDU_EXTENSION_5_RESERVED_5B_LSB 17 586 #define TX_MSDU_EXTENSION_5_RESERVED_5B_MASK 0xfffe0000 587 588 /* Description TX_MSDU_EXTENSION_6_BUF0_PTR_31_0 589 590 Lower 32 bits of the first buffer pointer 591 592 593 594 NOTE: SW/FW manages the 'cookie' info related to this 595 buffer together with the 'cookie' info for this 596 MSDU_EXTENSION descriptor 597 598 <legal all> 599 */ 600 #define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET 0x00000018 601 #define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_LSB 0 602 #define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK 0xffffffff 603 604 /* Description TX_MSDU_EXTENSION_7_BUF0_PTR_39_32 605 606 Upper 8 bits of the first buffer pointer <legal all> 607 */ 608 #define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_OFFSET 0x0000001c 609 #define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_LSB 0 610 #define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK 0x000000ff 611 612 /* Description TX_MSDU_EXTENSION_7_RESERVED_7A 613 614 <Legal 0> 615 */ 616 #define TX_MSDU_EXTENSION_7_RESERVED_7A_OFFSET 0x0000001c 617 #define TX_MSDU_EXTENSION_7_RESERVED_7A_LSB 8 618 #define TX_MSDU_EXTENSION_7_RESERVED_7A_MASK 0x0000ff00 619 620 /* Description TX_MSDU_EXTENSION_7_BUF0_LEN 621 622 Length of the first buffer <legal all> 623 */ 624 #define TX_MSDU_EXTENSION_7_BUF0_LEN_OFFSET 0x0000001c 625 #define TX_MSDU_EXTENSION_7_BUF0_LEN_LSB 16 626 #define TX_MSDU_EXTENSION_7_BUF0_LEN_MASK 0xffff0000 627 628 /* Description TX_MSDU_EXTENSION_8_BUF1_PTR_31_0 629 630 Lower 32 bits of the second buffer pointer 631 632 633 634 NOTE: SW/FW manages the 'cookie' info related to this 635 buffer together with the 'cookie' info for this 636 MSDU_EXTENSION descriptor 637 638 <legal all> 639 */ 640 #define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_OFFSET 0x00000020 641 #define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_LSB 0 642 #define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_MASK 0xffffffff 643 644 /* Description TX_MSDU_EXTENSION_9_BUF1_PTR_39_32 645 646 Upper 8 bits of the second buffer pointer <legal all> 647 */ 648 #define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_OFFSET 0x00000024 649 #define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_LSB 0 650 #define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_MASK 0x000000ff 651 652 /* Description TX_MSDU_EXTENSION_9_RESERVED_9A 653 654 <Legal 0> 655 */ 656 #define TX_MSDU_EXTENSION_9_RESERVED_9A_OFFSET 0x00000024 657 #define TX_MSDU_EXTENSION_9_RESERVED_9A_LSB 8 658 #define TX_MSDU_EXTENSION_9_RESERVED_9A_MASK 0x0000ff00 659 660 /* Description TX_MSDU_EXTENSION_9_BUF1_LEN 661 662 Length of the second buffer <legal all> 663 */ 664 #define TX_MSDU_EXTENSION_9_BUF1_LEN_OFFSET 0x00000024 665 #define TX_MSDU_EXTENSION_9_BUF1_LEN_LSB 16 666 #define TX_MSDU_EXTENSION_9_BUF1_LEN_MASK 0xffff0000 667 668 /* Description TX_MSDU_EXTENSION_10_BUF2_PTR_31_0 669 670 Lower 32 bits of the third buffer pointer 671 672 NOTE: SW/FW manages the 'cookie' info related to this 673 buffer together with the 'cookie' info for this 674 MSDU_EXTENSION descriptor 675 676 <legal all> 677 */ 678 #define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_OFFSET 0x00000028 679 #define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_LSB 0 680 #define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_MASK 0xffffffff 681 682 /* Description TX_MSDU_EXTENSION_11_BUF2_PTR_39_32 683 684 Upper 8 bits of the third buffer pointer <legal all> 685 */ 686 #define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_OFFSET 0x0000002c 687 #define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_LSB 0 688 #define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_MASK 0x000000ff 689 690 /* Description TX_MSDU_EXTENSION_11_RESERVED_11A 691 692 <Legal 0> 693 */ 694 #define TX_MSDU_EXTENSION_11_RESERVED_11A_OFFSET 0x0000002c 695 #define TX_MSDU_EXTENSION_11_RESERVED_11A_LSB 8 696 #define TX_MSDU_EXTENSION_11_RESERVED_11A_MASK 0x0000ff00 697 698 /* Description TX_MSDU_EXTENSION_11_BUF2_LEN 699 700 Length of the third buffer <legal all> 701 */ 702 #define TX_MSDU_EXTENSION_11_BUF2_LEN_OFFSET 0x0000002c 703 #define TX_MSDU_EXTENSION_11_BUF2_LEN_LSB 16 704 #define TX_MSDU_EXTENSION_11_BUF2_LEN_MASK 0xffff0000 705 706 /* Description TX_MSDU_EXTENSION_12_BUF3_PTR_31_0 707 708 Lower 32 bits of the fourth buffer pointer 709 710 711 712 NOTE: SW/FW manages the 'cookie' info related to this 713 buffer together with the 'cookie' info for this 714 MSDU_EXTENSION descriptor 715 716 <legal all> 717 */ 718 #define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_OFFSET 0x00000030 719 #define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_LSB 0 720 #define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_MASK 0xffffffff 721 722 /* Description TX_MSDU_EXTENSION_13_BUF3_PTR_39_32 723 724 Upper 8 bits of the fourth buffer pointer <legal all> 725 */ 726 #define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_OFFSET 0x00000034 727 #define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_LSB 0 728 #define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_MASK 0x000000ff 729 730 /* Description TX_MSDU_EXTENSION_13_RESERVED_13A 731 732 <Legal 0> 733 */ 734 #define TX_MSDU_EXTENSION_13_RESERVED_13A_OFFSET 0x00000034 735 #define TX_MSDU_EXTENSION_13_RESERVED_13A_LSB 8 736 #define TX_MSDU_EXTENSION_13_RESERVED_13A_MASK 0x0000ff00 737 738 /* Description TX_MSDU_EXTENSION_13_BUF3_LEN 739 740 Length of the fourth buffer <legal all> 741 */ 742 #define TX_MSDU_EXTENSION_13_BUF3_LEN_OFFSET 0x00000034 743 #define TX_MSDU_EXTENSION_13_BUF3_LEN_LSB 16 744 #define TX_MSDU_EXTENSION_13_BUF3_LEN_MASK 0xffff0000 745 746 /* Description TX_MSDU_EXTENSION_14_BUF4_PTR_31_0 747 748 Lower 32 bits of the fifth buffer pointer 749 750 751 752 NOTE: SW/FW manages the 'cookie' info related to this 753 buffer together with the 'cookie' info for this 754 MSDU_EXTENSION descriptor 755 756 <legal all> 757 */ 758 #define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_OFFSET 0x00000038 759 #define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_LSB 0 760 #define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_MASK 0xffffffff 761 762 /* Description TX_MSDU_EXTENSION_15_BUF4_PTR_39_32 763 764 Upper 8 bits of the fifth buffer pointer <legal all> 765 */ 766 #define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_OFFSET 0x0000003c 767 #define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_LSB 0 768 #define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_MASK 0x000000ff 769 770 /* Description TX_MSDU_EXTENSION_15_RESERVED_15A 771 772 <Legal 0> 773 */ 774 #define TX_MSDU_EXTENSION_15_RESERVED_15A_OFFSET 0x0000003c 775 #define TX_MSDU_EXTENSION_15_RESERVED_15A_LSB 8 776 #define TX_MSDU_EXTENSION_15_RESERVED_15A_MASK 0x0000ff00 777 778 /* Description TX_MSDU_EXTENSION_15_BUF4_LEN 779 780 Length of the fifth buffer <legal all> 781 */ 782 #define TX_MSDU_EXTENSION_15_BUF4_LEN_OFFSET 0x0000003c 783 #define TX_MSDU_EXTENSION_15_BUF4_LEN_LSB 16 784 #define TX_MSDU_EXTENSION_15_BUF4_LEN_MASK 0xffff0000 785 786 /* Description TX_MSDU_EXTENSION_16_BUF5_PTR_31_0 787 788 Lower 32 bits of the sixth buffer pointer 789 790 791 792 NOTE: SW/FW manages the 'cookie' info related to this 793 buffer together with the 'cookie' info for this 794 MSDU_EXTENSION descriptor 795 796 <legal all> 797 */ 798 #define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_OFFSET 0x00000040 799 #define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_LSB 0 800 #define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_MASK 0xffffffff 801 802 /* Description TX_MSDU_EXTENSION_17_BUF5_PTR_39_32 803 804 Upper 8 bits of the sixth buffer pointer <legal all> 805 */ 806 #define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_OFFSET 0x00000044 807 #define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_LSB 0 808 #define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_MASK 0x000000ff 809 810 /* Description TX_MSDU_EXTENSION_17_RESERVED_17A 811 812 <Legal 0> 813 */ 814 #define TX_MSDU_EXTENSION_17_RESERVED_17A_OFFSET 0x00000044 815 #define TX_MSDU_EXTENSION_17_RESERVED_17A_LSB 8 816 #define TX_MSDU_EXTENSION_17_RESERVED_17A_MASK 0x0000ff00 817 818 /* Description TX_MSDU_EXTENSION_17_BUF5_LEN 819 820 Length of the sixth buffer <legal all> 821 */ 822 #define TX_MSDU_EXTENSION_17_BUF5_LEN_OFFSET 0x00000044 823 #define TX_MSDU_EXTENSION_17_BUF5_LEN_LSB 16 824 #define TX_MSDU_EXTENSION_17_BUF5_LEN_MASK 0xffff0000 825 826 827 #endif // _TX_MSDU_EXTENSION_H_ 828