1 /* 2 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 /////////////////////////////////////////////////////////////////////////////////////////////// 18 // 19 // mac_tcl_reg_seq_hwioreg.h : automatically generated by Autoseq 3.1 5/20/2018 20 // User Name:vakkati 21 // 22 // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. 23 // 24 /////////////////////////////////////////////////////////////////////////////////////////////// 25 26 #ifndef __MAC_TCL_REG_SEQ_REG_H__ 27 #define __MAC_TCL_REG_SEQ_REG_H__ 28 29 #include "seq_hwio.h" 30 #include "mac_tcl_reg_seq_hwiobase.h" 31 #ifdef SCALE_INCLUDES 32 #include "HALhwio.h" 33 #else 34 #include "msmhwio.h" 35 #endif 36 37 38 /////////////////////////////////////////////////////////////////////////////////////////////// 39 // Register Data for Block MAC_TCL_REG 40 /////////////////////////////////////////////////////////////////////////////////////////////// 41 42 //// Register TCL_R0_SW2TCL1_RING_CTRL //// 43 44 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x) (x+0x00000000) 45 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_PHYS(x) (x+0x00000000) 46 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK 0x0003ffe0 47 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_SHFT 5 48 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x) \ 49 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK) 50 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_INM(x, mask) \ 51 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), mask) 52 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUT(x, val) \ 53 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), val) 54 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUTM(x, mask, val) \ 55 do {\ 56 HWIO_INTLOCK(); \ 57 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x)); \ 58 HWIO_INTFREE();\ 59 } while (0) 60 61 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 62 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 63 64 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x00000020 65 #define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_SHFT 0x5 66 67 //// Register TCL_R0_SW2TCL2_RING_CTRL //// 68 69 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x) (x+0x00000004) 70 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_PHYS(x) (x+0x00000004) 71 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK 0x0003ffe0 72 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_SHFT 5 73 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x) \ 74 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK) 75 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_INM(x, mask) \ 76 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), mask) 77 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUT(x, val) \ 78 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), val) 79 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUTM(x, mask, val) \ 80 do {\ 81 HWIO_INTLOCK(); \ 82 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x)); \ 83 HWIO_INTFREE();\ 84 } while (0) 85 86 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 87 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 88 89 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_BMSK 0x00000020 90 #define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_SHFT 0x5 91 92 //// Register TCL_R0_SW2TCL3_RING_CTRL //// 93 94 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x) (x+0x00000008) 95 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_PHYS(x) (x+0x00000008) 96 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK 0x0003ffe0 97 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_SHFT 5 98 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x) \ 99 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK) 100 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_INM(x, mask) \ 101 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), mask) 102 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUT(x, val) \ 103 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), val) 104 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUTM(x, mask, val) \ 105 do {\ 106 HWIO_INTLOCK(); \ 107 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x)); \ 108 HWIO_INTFREE();\ 109 } while (0) 110 111 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 112 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 113 114 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_BMSK 0x00000020 115 #define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_SHFT 0x5 116 117 //// Register TCL_R0_FW2TCL1_RING_CTRL //// 118 119 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x) (x+0x0000000c) 120 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_PHYS(x) (x+0x0000000c) 121 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK 0x0003ffe0 122 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_SHFT 5 123 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x) \ 124 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK) 125 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_INM(x, mask) \ 126 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), mask) 127 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUT(x, val) \ 128 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), val) 129 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUTM(x, mask, val) \ 130 do {\ 131 HWIO_INTLOCK(); \ 132 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x)); \ 133 HWIO_INTFREE();\ 134 } while (0) 135 136 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 137 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 138 139 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x00000020 140 #define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_SHFT 0x5 141 142 //// Register TCL_R0_SW2TCL_CMD_RING_CTRL //// 143 144 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x) (x+0x00000010) 145 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_PHYS(x) (x+0x00000010) 146 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RMSK 0x0003ffe0 147 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_SHFT 5 148 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_IN(x) \ 149 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RMSK) 150 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_INM(x, mask) \ 151 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), mask) 152 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_OUT(x, val) \ 153 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), val) 154 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_OUTM(x, mask, val) \ 155 do {\ 156 HWIO_INTLOCK(); \ 157 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_IN(x)); \ 158 HWIO_INTFREE();\ 159 } while (0) 160 161 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 162 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 163 164 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_PRTY_BMSK 0x00000020 165 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_PRTY_SHFT 0x5 166 167 //// Register TCL_R0_CONS_RING_CMN_CTRL_REG //// 168 169 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x) (x+0x00000014) 170 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PHYS(x) (x+0x00000014) 171 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK 0x000fffff 172 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SHFT 0 173 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x) \ 174 in_dword_masked ( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK) 175 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_INM(x, mask) \ 176 in_dword_masked ( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), mask) 177 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUT(x, val) \ 178 out_dword( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), val) 179 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUTM(x, mask, val) \ 180 do {\ 181 HWIO_INTLOCK(); \ 182 out_dword_masked_ns(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), mask, val, HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x)); \ 183 HWIO_INTFREE();\ 184 } while (0) 185 186 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_STOP_META_RD_AT_8B_BDRY_BMSK 0x00080000 187 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_STOP_META_RD_AT_8B_BDRY_SHFT 0x13 188 189 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ENABLE_C9D1_BMSK 0x00040000 190 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ENABLE_C9D1_SHFT 0x12 191 192 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK 0x00020000 193 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT 0x11 194 195 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_EXTN_NUM_BUF_RD_BMSK 0x0001c000 196 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_EXTN_NUM_BUF_RD_SHFT 0xe 197 198 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_TCL_IDLE_BMSK 0x00002000 199 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_TCL_IDLE_SHFT 0xd 200 201 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CMD_RNG_HALT_STAT_BMSK 0x00001000 202 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CMD_RNG_HALT_STAT_SHFT 0xc 203 204 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_STAT_BMSK 0x00000800 205 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_STAT_SHFT 0xb 206 207 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_STAT_BMSK 0x00000400 208 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_STAT_SHFT 0xa 209 210 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_STAT_BMSK 0x00000200 211 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_STAT_SHFT 0x9 212 213 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_STAT_BMSK 0x00000100 214 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_STAT_SHFT 0x8 215 216 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CMD_RNG_HALT_BMSK 0x00000080 217 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CMD_RNG_HALT_SHFT 0x7 218 219 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_BMSK 0x00000040 220 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_SHFT 0x6 221 222 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_BMSK 0x00000020 223 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_SHFT 0x5 224 225 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_BMSK 0x00000010 226 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_SHFT 0x4 227 228 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_BMSK 0x00000008 229 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_SHFT 0x3 230 231 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_BMSK 0x00000004 232 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_SHFT 0x2 233 234 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_HDR_LEN_SEL_BMSK 0x00000002 235 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_HDR_LEN_SEL_SHFT 0x1 236 237 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_CLFY_DIS_BMSK 0x00000001 238 #define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_CLFY_DIS_SHFT 0x0 239 240 //// Register TCL_R0_TCL2TQM_RING_CTRL //// 241 242 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x) (x+0x00000018) 243 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_PHYS(x) (x+0x00000018) 244 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_RMSK 0x00003fff 245 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_SHFT 0 246 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x) \ 247 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_CTRL_RMSK) 248 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_INM(x, mask) \ 249 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), mask) 250 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUT(x, val) \ 251 out_dword( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), val) 252 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUTM(x, mask, val) \ 253 do {\ 254 HWIO_INTLOCK(); \ 255 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x)); \ 256 HWIO_INTFREE();\ 257 } while (0) 258 259 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_RING_BMSK 0x00002000 260 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_RING_SHFT 0xd 261 262 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_REQUIRED_BMSK 0x00001000 263 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_REQUIRED_SHFT 0xc 264 265 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff 266 #define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 267 268 //// Register TCL_R0_TCL2FW_RING_CTRL //// 269 270 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x) (x+0x0000001c) 271 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_PHYS(x) (x+0x0000001c) 272 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_RMSK 0x00000fff 273 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_SHFT 0 274 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x) \ 275 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_CTRL_RMSK) 276 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_INM(x, mask) \ 277 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), mask) 278 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUT(x, val) \ 279 out_dword( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), val) 280 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUTM(x, mask, val) \ 281 do {\ 282 HWIO_INTLOCK(); \ 283 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x)); \ 284 HWIO_INTFREE();\ 285 } while (0) 286 287 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff 288 #define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 289 290 //// Register TCL_R0_TCL_STATUS1_RING_CTRL //// 291 292 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x) (x+0x00000020) 293 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_PHYS(x) (x+0x00000020) 294 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_RMSK 0x00000fff 295 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_SHFT 0 296 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x) \ 297 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_RMSK) 298 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_INM(x, mask) \ 299 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), mask) 300 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUT(x, val) \ 301 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), val) 302 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUTM(x, mask, val) \ 303 do {\ 304 HWIO_INTLOCK(); \ 305 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x)); \ 306 HWIO_INTFREE();\ 307 } while (0) 308 309 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff 310 #define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 311 312 //// Register TCL_R0_TCL_STATUS2_RING_CTRL //// 313 314 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x) (x+0x00000024) 315 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_PHYS(x) (x+0x00000024) 316 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_RMSK 0x00000fff 317 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_SHFT 0 318 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_IN(x) \ 319 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_RMSK) 320 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_INM(x, mask) \ 321 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), mask) 322 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_OUT(x, val) \ 323 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), val) 324 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_OUTM(x, mask, val) \ 325 do {\ 326 HWIO_INTLOCK(); \ 327 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_IN(x)); \ 328 HWIO_INTFREE();\ 329 } while (0) 330 331 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff 332 #define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 333 334 //// Register TCL_R0_GEN_CTRL //// 335 336 #define HWIO_TCL_R0_GEN_CTRL_ADDR(x) (x+0x00000028) 337 #define HWIO_TCL_R0_GEN_CTRL_PHYS(x) (x+0x00000028) 338 #define HWIO_TCL_R0_GEN_CTRL_RMSK 0xfffff1fb 339 #define HWIO_TCL_R0_GEN_CTRL_SHFT 0 340 #define HWIO_TCL_R0_GEN_CTRL_IN(x) \ 341 in_dword_masked ( HWIO_TCL_R0_GEN_CTRL_ADDR(x), HWIO_TCL_R0_GEN_CTRL_RMSK) 342 #define HWIO_TCL_R0_GEN_CTRL_INM(x, mask) \ 343 in_dword_masked ( HWIO_TCL_R0_GEN_CTRL_ADDR(x), mask) 344 #define HWIO_TCL_R0_GEN_CTRL_OUT(x, val) \ 345 out_dword( HWIO_TCL_R0_GEN_CTRL_ADDR(x), val) 346 #define HWIO_TCL_R0_GEN_CTRL_OUTM(x, mask, val) \ 347 do {\ 348 HWIO_INTLOCK(); \ 349 out_dword_masked_ns(HWIO_TCL_R0_GEN_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_GEN_CTRL_IN(x)); \ 350 HWIO_INTFREE();\ 351 } while (0) 352 353 #define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_BMSK 0xffff0000 354 #define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_SHFT 0x10 355 356 #define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_L4_BMSK 0x00008000 357 #define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_L4_SHFT 0xf 358 359 #define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_ESP_BMSK 0x00004000 360 #define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_ESP_SHFT 0xe 361 362 #define HWIO_TCL_R0_GEN_CTRL_FLOW_TOEPLITZ_5_SEL_BMSK 0x00002000 363 #define HWIO_TCL_R0_GEN_CTRL_FLOW_TOEPLITZ_5_SEL_SHFT 0xd 364 365 #define HWIO_TCL_R0_GEN_CTRL_CCE_STAT_UP_DIS_BMSK 0x00001000 366 #define HWIO_TCL_R0_GEN_CTRL_CCE_STAT_UP_DIS_SHFT 0xc 367 368 #define HWIO_TCL_R0_GEN_CTRL_CCE_UPDATE_DIS_BMSK 0x00000100 369 #define HWIO_TCL_R0_GEN_CTRL_CCE_UPDATE_DIS_SHFT 0x8 370 371 #define HWIO_TCL_R0_GEN_CTRL_FSE_UPDATE_DIS_BMSK 0x00000080 372 #define HWIO_TCL_R0_GEN_CTRL_FSE_UPDATE_DIS_SHFT 0x7 373 374 #define HWIO_TCL_R0_GEN_CTRL_ADDRY_UPDATE_DIS_BMSK 0x00000040 375 #define HWIO_TCL_R0_GEN_CTRL_ADDRY_UPDATE_DIS_SHFT 0x6 376 377 #define HWIO_TCL_R0_GEN_CTRL_ADDRX_UPDATE_DIS_BMSK 0x00000020 378 #define HWIO_TCL_R0_GEN_CTRL_ADDRX_UPDATE_DIS_SHFT 0x5 379 380 #define HWIO_TCL_R0_GEN_CTRL_FSE_EN_BMSK 0x00000010 381 #define HWIO_TCL_R0_GEN_CTRL_FSE_EN_SHFT 0x4 382 383 #define HWIO_TCL_R0_GEN_CTRL_CCE_EN_BMSK 0x00000008 384 #define HWIO_TCL_R0_GEN_CTRL_CCE_EN_SHFT 0x3 385 386 #define HWIO_TCL_R0_GEN_CTRL_TO_FW_BMSK 0x00000002 387 #define HWIO_TCL_R0_GEN_CTRL_TO_FW_SHFT 0x1 388 389 #define HWIO_TCL_R0_GEN_CTRL_EN_11AH_BMSK 0x00000001 390 #define HWIO_TCL_R0_GEN_CTRL_EN_11AH_SHFT 0x0 391 392 //// Register TCL_R0_DSCP_TID_MAP_n //// 393 394 #define HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n) (base+0x2C+0x4*n) 395 #define HWIO_TCL_R0_DSCP_TID_MAP_n_PHYS(base, n) (base+0x2C+0x4*n) 396 #define HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK 0xffffffff 397 #define HWIO_TCL_R0_DSCP_TID_MAP_n_SHFT 0 398 #define HWIO_TCL_R0_DSCP_TID_MAP_n_MAXn 287 399 #define HWIO_TCL_R0_DSCP_TID_MAP_n_INI(base, n) \ 400 in_dword_masked ( HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n), HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK) 401 #define HWIO_TCL_R0_DSCP_TID_MAP_n_INMI(base, n, mask) \ 402 in_dword_masked ( HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n), mask) 403 #define HWIO_TCL_R0_DSCP_TID_MAP_n_OUTI(base, n, val) \ 404 out_dword( HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n), val) 405 #define HWIO_TCL_R0_DSCP_TID_MAP_n_OUTMI(base, n, mask, val) \ 406 do {\ 407 HWIO_INTLOCK(); \ 408 out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n), mask, val, HWIO_TCL_R0_DSCP_TID_MAP_n_INI(base, n)); \ 409 HWIO_INTFREE();\ 410 } while (0) 411 412 #define HWIO_TCL_R0_DSCP_TID_MAP_n_VAL_BMSK 0xffffffff 413 #define HWIO_TCL_R0_DSCP_TID_MAP_n_VAL_SHFT 0x0 414 415 //// Register TCL_R0_PCP_TID_MAP //// 416 417 #define HWIO_TCL_R0_PCP_TID_MAP_ADDR(x) (x+0x000004ac) 418 #define HWIO_TCL_R0_PCP_TID_MAP_PHYS(x) (x+0x000004ac) 419 #define HWIO_TCL_R0_PCP_TID_MAP_RMSK 0x00ffffff 420 #define HWIO_TCL_R0_PCP_TID_MAP_SHFT 0 421 #define HWIO_TCL_R0_PCP_TID_MAP_IN(x) \ 422 in_dword_masked ( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), HWIO_TCL_R0_PCP_TID_MAP_RMSK) 423 #define HWIO_TCL_R0_PCP_TID_MAP_INM(x, mask) \ 424 in_dword_masked ( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), mask) 425 #define HWIO_TCL_R0_PCP_TID_MAP_OUT(x, val) \ 426 out_dword( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), val) 427 #define HWIO_TCL_R0_PCP_TID_MAP_OUTM(x, mask, val) \ 428 do {\ 429 HWIO_INTLOCK(); \ 430 out_dword_masked_ns(HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), mask, val, HWIO_TCL_R0_PCP_TID_MAP_IN(x)); \ 431 HWIO_INTFREE();\ 432 } while (0) 433 434 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_BMSK 0x00e00000 435 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT 0x15 436 437 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_BMSK 0x001c0000 438 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT 0x12 439 440 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_BMSK 0x00038000 441 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT 0xf 442 443 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_BMSK 0x00007000 444 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT 0xc 445 446 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_BMSK 0x00000e00 447 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT 0x9 448 449 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_BMSK 0x000001c0 450 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT 0x6 451 452 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_BMSK 0x00000038 453 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT 0x3 454 455 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_BMSK 0x00000007 456 #define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_SHFT 0x0 457 458 //// Register TCL_R0_ASE_HASH_KEY_31_0 //// 459 460 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x) (x+0x000004b0) 461 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_PHYS(x) (x+0x000004b0) 462 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_RMSK 0xffffffff 463 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_SHFT 0 464 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x) \ 465 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_31_0_RMSK) 466 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_INM(x, mask) \ 467 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), mask) 468 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUT(x, val) \ 469 out_dword( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), val) 470 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUTM(x, mask, val) \ 471 do {\ 472 HWIO_INTLOCK(); \ 473 out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x)); \ 474 HWIO_INTFREE();\ 475 } while (0) 476 477 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_BMSK 0xffffffff 478 #define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_SHFT 0x0 479 480 //// Register TCL_R0_ASE_HASH_KEY_63_32 //// 481 482 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x) (x+0x000004b4) 483 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_PHYS(x) (x+0x000004b4) 484 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_RMSK 0xffffffff 485 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_SHFT 0 486 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x) \ 487 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_63_32_RMSK) 488 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_INM(x, mask) \ 489 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), mask) 490 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUT(x, val) \ 491 out_dword( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), val) 492 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUTM(x, mask, val) \ 493 do {\ 494 HWIO_INTLOCK(); \ 495 out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x)); \ 496 HWIO_INTFREE();\ 497 } while (0) 498 499 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_BMSK 0xffffffff 500 #define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_SHFT 0x0 501 502 //// Register TCL_R0_ASE_HASH_KEY_64 //// 503 504 #define HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x) (x+0x000004b8) 505 #define HWIO_TCL_R0_ASE_HASH_KEY_64_PHYS(x) (x+0x000004b8) 506 #define HWIO_TCL_R0_ASE_HASH_KEY_64_RMSK 0x00000001 507 #define HWIO_TCL_R0_ASE_HASH_KEY_64_SHFT 0 508 #define HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x) \ 509 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_64_RMSK) 510 #define HWIO_TCL_R0_ASE_HASH_KEY_64_INM(x, mask) \ 511 in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), mask) 512 #define HWIO_TCL_R0_ASE_HASH_KEY_64_OUT(x, val) \ 513 out_dword( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), val) 514 #define HWIO_TCL_R0_ASE_HASH_KEY_64_OUTM(x, mask, val) \ 515 do {\ 516 HWIO_INTLOCK(); \ 517 out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x)); \ 518 HWIO_INTFREE();\ 519 } while (0) 520 521 #define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_BMSK 0x00000001 522 #define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_SHFT 0x0 523 524 //// Register TCL_R0_FSE_HASH_KEY_31_0 //// 525 526 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x) (x+0x000004bc) 527 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_PHYS(x) (x+0x000004bc) 528 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_RMSK 0xffffffff 529 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_SHFT 0 530 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_IN(x) \ 531 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_31_0_RMSK) 532 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_INM(x, mask) \ 533 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), mask) 534 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_OUT(x, val) \ 535 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), val) 536 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_OUTM(x, mask, val) \ 537 do {\ 538 HWIO_INTLOCK(); \ 539 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_31_0_IN(x)); \ 540 HWIO_INTFREE();\ 541 } while (0) 542 543 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_VAL_BMSK 0xffffffff 544 #define HWIO_TCL_R0_FSE_HASH_KEY_31_0_VAL_SHFT 0x0 545 546 //// Register TCL_R0_FSE_HASH_KEY_63_32 //// 547 548 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x) (x+0x000004c0) 549 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_PHYS(x) (x+0x000004c0) 550 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_RMSK 0xffffffff 551 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_SHFT 0 552 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_IN(x) \ 553 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_63_32_RMSK) 554 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_INM(x, mask) \ 555 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), mask) 556 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_OUT(x, val) \ 557 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), val) 558 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_OUTM(x, mask, val) \ 559 do {\ 560 HWIO_INTLOCK(); \ 561 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_63_32_IN(x)); \ 562 HWIO_INTFREE();\ 563 } while (0) 564 565 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_VAL_BMSK 0xffffffff 566 #define HWIO_TCL_R0_FSE_HASH_KEY_63_32_VAL_SHFT 0x0 567 568 //// Register TCL_R0_FSE_HASH_KEY_95_64 //// 569 570 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x) (x+0x000004c4) 571 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_PHYS(x) (x+0x000004c4) 572 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_RMSK 0xffffffff 573 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_SHFT 0 574 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_IN(x) \ 575 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_95_64_RMSK) 576 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_INM(x, mask) \ 577 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), mask) 578 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_OUT(x, val) \ 579 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), val) 580 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_OUTM(x, mask, val) \ 581 do {\ 582 HWIO_INTLOCK(); \ 583 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_95_64_IN(x)); \ 584 HWIO_INTFREE();\ 585 } while (0) 586 587 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_VAL_BMSK 0xffffffff 588 #define HWIO_TCL_R0_FSE_HASH_KEY_95_64_VAL_SHFT 0x0 589 590 //// Register TCL_R0_FSE_HASH_KEY_127_96 //// 591 592 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x) (x+0x000004c8) 593 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_PHYS(x) (x+0x000004c8) 594 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_RMSK 0xffffffff 595 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_SHFT 0 596 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_IN(x) \ 597 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_127_96_RMSK) 598 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_INM(x, mask) \ 599 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), mask) 600 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_OUT(x, val) \ 601 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), val) 602 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_OUTM(x, mask, val) \ 603 do {\ 604 HWIO_INTLOCK(); \ 605 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_127_96_IN(x)); \ 606 HWIO_INTFREE();\ 607 } while (0) 608 609 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_VAL_BMSK 0xffffffff 610 #define HWIO_TCL_R0_FSE_HASH_KEY_127_96_VAL_SHFT 0x0 611 612 //// Register TCL_R0_FSE_HASH_KEY_159_128 //// 613 614 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x) (x+0x000004cc) 615 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_PHYS(x) (x+0x000004cc) 616 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_RMSK 0xffffffff 617 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_SHFT 0 618 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_IN(x) \ 619 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_159_128_RMSK) 620 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_INM(x, mask) \ 621 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), mask) 622 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_OUT(x, val) \ 623 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), val) 624 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_OUTM(x, mask, val) \ 625 do {\ 626 HWIO_INTLOCK(); \ 627 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_159_128_IN(x)); \ 628 HWIO_INTFREE();\ 629 } while (0) 630 631 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_VAL_BMSK 0xffffffff 632 #define HWIO_TCL_R0_FSE_HASH_KEY_159_128_VAL_SHFT 0x0 633 634 //// Register TCL_R0_FSE_HASH_KEY_191_160 //// 635 636 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x) (x+0x000004d0) 637 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_PHYS(x) (x+0x000004d0) 638 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_RMSK 0xffffffff 639 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_SHFT 0 640 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_IN(x) \ 641 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_191_160_RMSK) 642 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_INM(x, mask) \ 643 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), mask) 644 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_OUT(x, val) \ 645 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), val) 646 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_OUTM(x, mask, val) \ 647 do {\ 648 HWIO_INTLOCK(); \ 649 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_191_160_IN(x)); \ 650 HWIO_INTFREE();\ 651 } while (0) 652 653 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_VAL_BMSK 0xffffffff 654 #define HWIO_TCL_R0_FSE_HASH_KEY_191_160_VAL_SHFT 0x0 655 656 //// Register TCL_R0_FSE_HASH_KEY_223_192 //// 657 658 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x) (x+0x000004d4) 659 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_PHYS(x) (x+0x000004d4) 660 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_RMSK 0xffffffff 661 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_SHFT 0 662 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_IN(x) \ 663 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_223_192_RMSK) 664 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_INM(x, mask) \ 665 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), mask) 666 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_OUT(x, val) \ 667 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), val) 668 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_OUTM(x, mask, val) \ 669 do {\ 670 HWIO_INTLOCK(); \ 671 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_223_192_IN(x)); \ 672 HWIO_INTFREE();\ 673 } while (0) 674 675 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_VAL_BMSK 0xffffffff 676 #define HWIO_TCL_R0_FSE_HASH_KEY_223_192_VAL_SHFT 0x0 677 678 //// Register TCL_R0_FSE_HASH_KEY_255_224 //// 679 680 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x) (x+0x000004d8) 681 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_PHYS(x) (x+0x000004d8) 682 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_RMSK 0xffffffff 683 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_SHFT 0 684 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_IN(x) \ 685 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_255_224_RMSK) 686 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_INM(x, mask) \ 687 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), mask) 688 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_OUT(x, val) \ 689 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), val) 690 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_OUTM(x, mask, val) \ 691 do {\ 692 HWIO_INTLOCK(); \ 693 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_255_224_IN(x)); \ 694 HWIO_INTFREE();\ 695 } while (0) 696 697 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_VAL_BMSK 0xffffffff 698 #define HWIO_TCL_R0_FSE_HASH_KEY_255_224_VAL_SHFT 0x0 699 700 //// Register TCL_R0_FSE_HASH_KEY_287_256 //// 701 702 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x) (x+0x000004dc) 703 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_PHYS(x) (x+0x000004dc) 704 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_RMSK 0xffffffff 705 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_SHFT 0 706 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_IN(x) \ 707 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_287_256_RMSK) 708 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_INM(x, mask) \ 709 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), mask) 710 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_OUT(x, val) \ 711 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), val) 712 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_OUTM(x, mask, val) \ 713 do {\ 714 HWIO_INTLOCK(); \ 715 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_287_256_IN(x)); \ 716 HWIO_INTFREE();\ 717 } while (0) 718 719 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_VAL_BMSK 0xffffffff 720 #define HWIO_TCL_R0_FSE_HASH_KEY_287_256_VAL_SHFT 0x0 721 722 //// Register TCL_R0_FSE_HASH_KEY_314_288 //// 723 724 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x) (x+0x000004e0) 725 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_PHYS(x) (x+0x000004e0) 726 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_RMSK 0x07ffffff 727 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_SHFT 0 728 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_IN(x) \ 729 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_314_288_RMSK) 730 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_INM(x, mask) \ 731 in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), mask) 732 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_OUT(x, val) \ 733 out_dword( HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), val) 734 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_OUTM(x, mask, val) \ 735 do {\ 736 HWIO_INTLOCK(); \ 737 out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_314_288_IN(x)); \ 738 HWIO_INTFREE();\ 739 } while (0) 740 741 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_VAL_BMSK 0x07ffffff 742 #define HWIO_TCL_R0_FSE_HASH_KEY_314_288_VAL_SHFT 0x0 743 744 //// Register TCL_R0_CONFIG_SEARCH_QUEUE //// 745 746 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x) (x+0x000004e4) 747 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PHYS(x) (x+0x000004e4) 748 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_RMSK 0x00fffdfc 749 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_SHFT 2 750 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x) \ 751 in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_RMSK) 752 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_INM(x, mask) \ 753 in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), mask) 754 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUT(x, val) \ 755 out_dword( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), val) 756 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUTM(x, mask, val) \ 757 do {\ 758 HWIO_INTLOCK(); \ 759 out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), mask, val, HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x)); \ 760 HWIO_INTFREE();\ 761 } while (0) 762 763 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_MSDU_LEN_ERR_TO_FW_EN_BMSK 0x00800000 764 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_MSDU_LEN_ERR_TO_FW_EN_SHFT 0x17 765 766 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_M0_FW_SEL_BMSK 0x00700000 767 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_M0_FW_SEL_SHFT 0x14 768 769 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ASE_M0_FW_SEL_BMSK 0x000e0000 770 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ASE_M0_FW_SEL_SHFT 0x11 771 772 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_M0_FW_SEL_BMSK 0x0001c000 773 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_M0_FW_SEL_SHFT 0xe 774 775 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_BMSK 0x00002000 776 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_SHFT 0xd 777 778 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_DROP_BMSK 0x00001000 779 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_DROP_SHFT 0xc 780 781 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_LOOP_BMSK 0x00000800 782 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_LOOP_SHFT 0xb 783 784 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_LOOP_BMSK 0x00000400 785 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_LOOP_SHFT 0xa 786 787 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PRIORITY_BMSK 0x000001c0 788 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PRIORITY_SHFT 0x6 789 790 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_HANDLER_BMSK 0x00000030 791 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_HANDLER_SHFT 0x4 792 793 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_HANDLER_BMSK 0x0000000c 794 #define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_HANDLER_SHFT 0x2 795 796 //// Register TCL_R0_FSE_FAIL_QUEUE_NUM_LOW //// 797 798 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x) (x+0x000004e8) 799 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_PHYS(x) (x+0x000004e8) 800 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_RMSK 0xffffffff 801 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_SHFT 0 802 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x) \ 803 in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_RMSK) 804 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_INM(x, mask) \ 805 in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask) 806 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUT(x, val) \ 807 out_dword( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), val) 808 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUTM(x, mask, val) \ 809 do {\ 810 HWIO_INTLOCK(); \ 811 out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask, val, HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x)); \ 812 HWIO_INTFREE();\ 813 } while (0) 814 815 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_BMSK 0xffffffff 816 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_SHFT 0x0 817 818 //// Register TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH //// 819 820 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x) (x+0x000004ec) 821 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_PHYS(x) (x+0x000004ec) 822 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_RMSK 0x000000ff 823 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_SHFT 0 824 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x) \ 825 in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_RMSK) 826 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_INM(x, mask) \ 827 in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask) 828 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUT(x, val) \ 829 out_dword( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), val) 830 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUTM(x, mask, val) \ 831 do {\ 832 HWIO_INTLOCK(); \ 833 out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x)); \ 834 HWIO_INTFREE();\ 835 } while (0) 836 837 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK 0x000000ff 838 #define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT 0x0 839 840 //// Register TCL_R0_CCE_FAIL_QUEUE_NUM_LOW //// 841 842 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x) (x+0x000004f0) 843 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_PHYS(x) (x+0x000004f0) 844 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_RMSK 0xffffffff 845 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_SHFT 0 846 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x) \ 847 in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_RMSK) 848 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_INM(x, mask) \ 849 in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask) 850 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUT(x, val) \ 851 out_dword( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), val) 852 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUTM(x, mask, val) \ 853 do {\ 854 HWIO_INTLOCK(); \ 855 out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask, val, HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x)); \ 856 HWIO_INTFREE();\ 857 } while (0) 858 859 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_BMSK 0xffffffff 860 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_SHFT 0x0 861 862 //// Register TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH //// 863 864 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x) (x+0x000004f4) 865 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_PHYS(x) (x+0x000004f4) 866 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_RMSK 0x000000ff 867 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_SHFT 0 868 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x) \ 869 in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_RMSK) 870 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_INM(x, mask) \ 871 in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask) 872 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUT(x, val) \ 873 out_dword( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), val) 874 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUTM(x, mask, val) \ 875 do {\ 876 HWIO_INTLOCK(); \ 877 out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x)); \ 878 HWIO_INTFREE();\ 879 } while (0) 880 881 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK 0x000000ff 882 #define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT 0x0 883 884 //// Register TCL_R0_CONFIG_SEARCH_METADATA //// 885 886 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x) (x+0x000004f8) 887 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_PHYS(x) (x+0x000004f8) 888 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_RMSK 0xffffffff 889 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_SHFT 0 890 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x) \ 891 in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), HWIO_TCL_R0_CONFIG_SEARCH_METADATA_RMSK) 892 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_INM(x, mask) \ 893 in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), mask) 894 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUT(x, val) \ 895 out_dword( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), val) 896 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUTM(x, mask, val) \ 897 do {\ 898 HWIO_INTLOCK(); \ 899 out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), mask, val, HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x)); \ 900 HWIO_INTFREE();\ 901 } while (0) 902 903 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_BMSK 0xffff0000 904 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_SHFT 0x10 905 906 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_CCE_FAIL_NUM_BMSK 0x0000ffff 907 #define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_CCE_FAIL_NUM_SHFT 0x0 908 909 //// Register TCL_R0_TID_MAP_PRTY //// 910 911 #define HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x) (x+0x000004fc) 912 #define HWIO_TCL_R0_TID_MAP_PRTY_PHYS(x) (x+0x000004fc) 913 #define HWIO_TCL_R0_TID_MAP_PRTY_RMSK 0x000000ef 914 #define HWIO_TCL_R0_TID_MAP_PRTY_SHFT 0 915 #define HWIO_TCL_R0_TID_MAP_PRTY_IN(x) \ 916 in_dword_masked ( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), HWIO_TCL_R0_TID_MAP_PRTY_RMSK) 917 #define HWIO_TCL_R0_TID_MAP_PRTY_INM(x, mask) \ 918 in_dword_masked ( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), mask) 919 #define HWIO_TCL_R0_TID_MAP_PRTY_OUT(x, val) \ 920 out_dword( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), val) 921 #define HWIO_TCL_R0_TID_MAP_PRTY_OUTM(x, mask, val) \ 922 do {\ 923 HWIO_INTLOCK(); \ 924 out_dword_masked_ns(HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), mask, val, HWIO_TCL_R0_TID_MAP_PRTY_IN(x)); \ 925 HWIO_INTFREE();\ 926 } while (0) 927 928 #define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_BMSK 0x000000e0 929 #define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_SHFT 0x5 930 931 #define HWIO_TCL_R0_TID_MAP_PRTY_VAL_BMSK 0x0000000f 932 #define HWIO_TCL_R0_TID_MAP_PRTY_VAL_SHFT 0x0 933 934 //// Register TCL_R0_INVALID_APB_ACC_ADDR //// 935 936 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x) (x+0x00000500) 937 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_PHYS(x) (x+0x00000500) 938 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_RMSK 0xffffffff 939 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_SHFT 0 940 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_IN(x) \ 941 in_dword_masked ( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), HWIO_TCL_R0_INVALID_APB_ACC_ADDR_RMSK) 942 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_INM(x, mask) \ 943 in_dword_masked ( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask) 944 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_OUT(x, val) \ 945 out_dword( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), val) 946 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_OUTM(x, mask, val) \ 947 do {\ 948 HWIO_INTLOCK(); \ 949 out_dword_masked_ns(HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask, val, HWIO_TCL_R0_INVALID_APB_ACC_ADDR_IN(x)); \ 950 HWIO_INTFREE();\ 951 } while (0) 952 953 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_BMSK 0xffffffff 954 #define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_SHFT 0x0 955 956 //// Register TCL_R0_WATCHDOG //// 957 958 #define HWIO_TCL_R0_WATCHDOG_ADDR(x) (x+0x00000504) 959 #define HWIO_TCL_R0_WATCHDOG_PHYS(x) (x+0x00000504) 960 #define HWIO_TCL_R0_WATCHDOG_RMSK 0xffffffff 961 #define HWIO_TCL_R0_WATCHDOG_SHFT 0 962 #define HWIO_TCL_R0_WATCHDOG_IN(x) \ 963 in_dword_masked ( HWIO_TCL_R0_WATCHDOG_ADDR(x), HWIO_TCL_R0_WATCHDOG_RMSK) 964 #define HWIO_TCL_R0_WATCHDOG_INM(x, mask) \ 965 in_dword_masked ( HWIO_TCL_R0_WATCHDOG_ADDR(x), mask) 966 #define HWIO_TCL_R0_WATCHDOG_OUT(x, val) \ 967 out_dword( HWIO_TCL_R0_WATCHDOG_ADDR(x), val) 968 #define HWIO_TCL_R0_WATCHDOG_OUTM(x, mask, val) \ 969 do {\ 970 HWIO_INTLOCK(); \ 971 out_dword_masked_ns(HWIO_TCL_R0_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_WATCHDOG_IN(x)); \ 972 HWIO_INTFREE();\ 973 } while (0) 974 975 #define HWIO_TCL_R0_WATCHDOG_STATUS_BMSK 0xffff0000 976 #define HWIO_TCL_R0_WATCHDOG_STATUS_SHFT 0x10 977 978 #define HWIO_TCL_R0_WATCHDOG_LIMIT_BMSK 0x0000ffff 979 #define HWIO_TCL_R0_WATCHDOG_LIMIT_SHFT 0x0 980 981 //// Register TCL_R0_CLKGATE_DISABLE //// 982 983 #define HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x) (x+0x00000508) 984 #define HWIO_TCL_R0_CLKGATE_DISABLE_PHYS(x) (x+0x00000508) 985 #define HWIO_TCL_R0_CLKGATE_DISABLE_RMSK 0xffffffff 986 #define HWIO_TCL_R0_CLKGATE_DISABLE_SHFT 0 987 #define HWIO_TCL_R0_CLKGATE_DISABLE_IN(x) \ 988 in_dword_masked ( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_CLKGATE_DISABLE_RMSK) 989 #define HWIO_TCL_R0_CLKGATE_DISABLE_INM(x, mask) \ 990 in_dword_masked ( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), mask) 991 #define HWIO_TCL_R0_CLKGATE_DISABLE_OUT(x, val) \ 992 out_dword( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), val) 993 #define HWIO_TCL_R0_CLKGATE_DISABLE_OUTM(x, mask, val) \ 994 do {\ 995 HWIO_INTLOCK(); \ 996 out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_CLKGATE_DISABLE_IN(x)); \ 997 HWIO_INTFREE();\ 998 } while (0) 999 1000 #define HWIO_TCL_R0_CLKGATE_DISABLE_CLK_ENS_EXTEND_BMSK 0x80000000 1001 #define HWIO_TCL_R0_CLKGATE_DISABLE_CLK_ENS_EXTEND_SHFT 0x1f 1002 1003 #define HWIO_TCL_R0_CLKGATE_DISABLE_CPU_IF_EXTEND_BMSK 0x40000000 1004 #define HWIO_TCL_R0_CLKGATE_DISABLE_CPU_IF_EXTEND_SHFT 0x1e 1005 1006 #define HWIO_TCL_R0_CLKGATE_DISABLE_APB_CLK_BMSK 0x20000000 1007 #define HWIO_TCL_R0_CLKGATE_DISABLE_APB_CLK_SHFT 0x1d 1008 1009 #define HWIO_TCL_R0_CLKGATE_DISABLE_FSE_BMSK 0x10000000 1010 #define HWIO_TCL_R0_CLKGATE_DISABLE_FSE_SHFT 0x1c 1011 1012 #define HWIO_TCL_R0_CLKGATE_DISABLE_CLFY_RES_MEM_BMSK 0x08000000 1013 #define HWIO_TCL_R0_CLKGATE_DISABLE_CLFY_RES_MEM_SHFT 0x1b 1014 1015 #define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CTRL_BMSK 0x04000000 1016 #define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CTRL_SHFT 0x1a 1017 1018 #define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CCE_RES_BMSK 0x02000000 1019 #define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CCE_RES_SHFT 0x19 1020 1021 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS2_PROD_RING_BMSK 0x01000000 1022 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS2_PROD_RING_SHFT 0x18 1023 1024 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS1_PROD_RING_BMSK 0x00800000 1025 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS1_PROD_RING_SHFT 0x17 1026 1027 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2FW_PROD_RING_BMSK 0x00400000 1028 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2FW_PROD_RING_SHFT 0x16 1029 1030 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2TQM_PROD_RING_BMSK 0x00200000 1031 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2TQM_PROD_RING_SHFT 0x15 1032 1033 #define HWIO_TCL_R0_CLKGATE_DISABLE_PROD_RING_CTRL_BMSK 0x00100000 1034 #define HWIO_TCL_R0_CLKGATE_DISABLE_PROD_RING_CTRL_SHFT 0x14 1035 1036 #define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_DECODE_BMSK 0x00080000 1037 #define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_DECODE_SHFT 0x13 1038 1039 #define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_GEN_BMSK 0x00040000 1040 #define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_GEN_SHFT 0x12 1041 1042 #define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_FETCH_BMSK 0x00020000 1043 #define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_FETCH_SHFT 0x11 1044 1045 #define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_BUF_BMSK 0x00010000 1046 #define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_BUF_SHFT 0x10 1047 1048 #define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_BUF_BMSK 0x00008000 1049 #define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_BUF_SHFT 0xf 1050 1051 #define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_BMSK 0x00004000 1052 #define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_SHFT 0xe 1053 1054 #define HWIO_TCL_R0_CLKGATE_DISABLE_ASE_BMSK 0x00002000 1055 #define HWIO_TCL_R0_CLKGATE_DISABLE_ASE_SHFT 0xd 1056 1057 #define HWIO_TCL_R0_CLKGATE_DISABLE_GXI_BMSK 0x00001000 1058 #define HWIO_TCL_R0_CLKGATE_DISABLE_GXI_SHFT 0xc 1059 1060 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_3_BMSK 0x00000800 1061 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_3_SHFT 0xb 1062 1063 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_2_BMSK 0x00000400 1064 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_2_SHFT 0xa 1065 1066 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_1_BMSK 0x00000200 1067 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_1_SHFT 0x9 1068 1069 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_0_BMSK 0x00000100 1070 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_0_SHFT 0x8 1071 1072 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_4_BMSK 0x00000080 1073 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_4_SHFT 0x7 1074 1075 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_3_BMSK 0x00000040 1076 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_3_SHFT 0x6 1077 1078 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_2_BMSK 0x00000020 1079 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_2_SHFT 0x5 1080 1081 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_1_BMSK 0x00000010 1082 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_1_SHFT 0x4 1083 1084 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_0_BMSK 0x00000008 1085 #define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_0_SHFT 0x3 1086 1087 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL_IDLE_REQ_SM_BMSK 0x00000004 1088 #define HWIO_TCL_R0_CLKGATE_DISABLE_TCL_IDLE_REQ_SM_SHFT 0x2 1089 1090 #define HWIO_TCL_R0_CLKGATE_DISABLE_CCE_BMSK 0x00000002 1091 #define HWIO_TCL_R0_CLKGATE_DISABLE_CCE_SHFT 0x1 1092 1093 #define HWIO_TCL_R0_CLKGATE_DISABLE_PARSER_BMSK 0x00000001 1094 #define HWIO_TCL_R0_CLKGATE_DISABLE_PARSER_SHFT 0x0 1095 1096 //// Register TCL_R0_S_PARE_REGISTER //// 1097 1098 #define HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x) (x+0x0000050c) 1099 #define HWIO_TCL_R0_S_PARE_REGISTER_PHYS(x) (x+0x0000050c) 1100 #define HWIO_TCL_R0_S_PARE_REGISTER_RMSK 0xffffffff 1101 #define HWIO_TCL_R0_S_PARE_REGISTER_SHFT 0 1102 #define HWIO_TCL_R0_S_PARE_REGISTER_IN(x) \ 1103 in_dword_masked ( HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x), HWIO_TCL_R0_S_PARE_REGISTER_RMSK) 1104 #define HWIO_TCL_R0_S_PARE_REGISTER_INM(x, mask) \ 1105 in_dword_masked ( HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x), mask) 1106 #define HWIO_TCL_R0_S_PARE_REGISTER_OUT(x, val) \ 1107 out_dword( HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x), val) 1108 #define HWIO_TCL_R0_S_PARE_REGISTER_OUTM(x, mask, val) \ 1109 do {\ 1110 HWIO_INTLOCK(); \ 1111 out_dword_masked_ns(HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x), mask, val, HWIO_TCL_R0_S_PARE_REGISTER_IN(x)); \ 1112 HWIO_INTFREE();\ 1113 } while (0) 1114 1115 #define HWIO_TCL_R0_S_PARE_REGISTER_VAL_BMSK 0xffffffff 1116 #define HWIO_TCL_R0_S_PARE_REGISTER_VAL_SHFT 0x0 1117 1118 //// Register TCL_R0_SW2TCL1_RING_BASE_LSB //// 1119 1120 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x) (x+0x00000510) 1121 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_PHYS(x) (x+0x00000510) 1122 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RMSK 0xffffffff 1123 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_SHFT 0 1124 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x) \ 1125 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RMSK) 1126 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_INM(x, mask) \ 1127 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), mask) 1128 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUT(x, val) \ 1129 out_dword( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), val) 1130 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUTM(x, mask, val) \ 1131 do {\ 1132 HWIO_INTLOCK(); \ 1133 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x)); \ 1134 HWIO_INTFREE();\ 1135 } while (0) 1136 1137 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1138 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1139 1140 //// Register TCL_R0_SW2TCL1_RING_BASE_MSB //// 1141 1142 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x) (x+0x00000514) 1143 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_PHYS(x) (x+0x00000514) 1144 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RMSK 0x0fffffff 1145 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_SHFT 0 1146 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x) \ 1147 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RMSK) 1148 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_INM(x, mask) \ 1149 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), mask) 1150 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUT(x, val) \ 1151 out_dword( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), val) 1152 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUTM(x, mask, val) \ 1153 do {\ 1154 HWIO_INTLOCK(); \ 1155 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x)); \ 1156 HWIO_INTFREE();\ 1157 } while (0) 1158 1159 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 1160 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1161 1162 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1163 #define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1164 1165 //// Register TCL_R0_SW2TCL1_RING_ID //// 1166 1167 #define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x) (x+0x00000518) 1168 #define HWIO_TCL_R0_SW2TCL1_RING_ID_PHYS(x) (x+0x00000518) 1169 #define HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK 0x000000ff 1170 #define HWIO_TCL_R0_SW2TCL1_RING_ID_SHFT 0 1171 #define HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x) \ 1172 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK) 1173 #define HWIO_TCL_R0_SW2TCL1_RING_ID_INM(x, mask) \ 1174 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), mask) 1175 #define HWIO_TCL_R0_SW2TCL1_RING_ID_OUT(x, val) \ 1176 out_dword( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), val) 1177 #define HWIO_TCL_R0_SW2TCL1_RING_ID_OUTM(x, mask, val) \ 1178 do {\ 1179 HWIO_INTLOCK(); \ 1180 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x)); \ 1181 HWIO_INTFREE();\ 1182 } while (0) 1183 1184 #define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1185 #define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0x0 1186 1187 //// Register TCL_R0_SW2TCL1_RING_STATUS //// 1188 1189 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x) (x+0x0000051c) 1190 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_PHYS(x) (x+0x0000051c) 1191 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_RMSK 0xffffffff 1192 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_SHFT 0 1193 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x) \ 1194 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_STATUS_RMSK) 1195 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_INM(x, mask) \ 1196 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), mask) 1197 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_OUT(x, val) \ 1198 out_dword( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), val) 1199 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_OUTM(x, mask, val) \ 1200 do {\ 1201 HWIO_INTLOCK(); \ 1202 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x)); \ 1203 HWIO_INTFREE();\ 1204 } while (0) 1205 1206 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1207 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1208 1209 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1210 #define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1211 1212 //// Register TCL_R0_SW2TCL1_RING_MISC //// 1213 1214 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x) (x+0x00000520) 1215 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_PHYS(x) (x+0x00000520) 1216 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_RMSK 0x003fffff 1217 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SHFT 0 1218 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x) \ 1219 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MISC_RMSK) 1220 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_INM(x, mask) \ 1221 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), mask) 1222 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUT(x, val) \ 1223 out_dword( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), val) 1224 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUTM(x, mask, val) \ 1225 do {\ 1226 HWIO_INTLOCK(); \ 1227 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x)); \ 1228 HWIO_INTFREE();\ 1229 } while (0) 1230 1231 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 1232 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SPARE_CONTROL_SHFT 0xe 1233 1234 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 1235 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 1236 1237 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 1238 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 1239 1240 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 1241 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 1242 1243 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 1244 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_ENABLE_SHFT 0x6 1245 1246 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 1247 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1248 1249 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 1250 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1251 1252 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 1253 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1254 1255 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 1256 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_SHFT 0x2 1257 1258 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 1259 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1260 1261 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 1262 #define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1263 1264 //// Register TCL_R0_SW2TCL1_RING_TP_ADDR_LSB //// 1265 1266 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x) (x+0x0000052c) 1267 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_PHYS(x) (x+0x0000052c) 1268 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff 1269 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_SHFT 0 1270 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x) \ 1271 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_RMSK) 1272 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_INM(x, mask) \ 1273 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask) 1274 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUT(x, val) \ 1275 out_dword( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), val) 1276 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 1277 do {\ 1278 HWIO_INTLOCK(); \ 1279 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x)); \ 1280 HWIO_INTFREE();\ 1281 } while (0) 1282 1283 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 1284 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 1285 1286 //// Register TCL_R0_SW2TCL1_RING_TP_ADDR_MSB //// 1287 1288 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000530) 1289 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000530) 1290 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_RMSK 0x000000ff 1291 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_SHFT 0 1292 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x) \ 1293 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_RMSK) 1294 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_INM(x, mask) \ 1295 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask) 1296 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUT(x, val) \ 1297 out_dword( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), val) 1298 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 1299 do {\ 1300 HWIO_INTLOCK(); \ 1301 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x)); \ 1302 HWIO_INTFREE();\ 1303 } while (0) 1304 1305 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 1306 #define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 1307 1308 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0 //// 1309 1310 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000540) 1311 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000540) 1312 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 1313 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 1314 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 1315 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK) 1316 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 1317 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 1318 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 1319 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 1320 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 1321 do {\ 1322 HWIO_INTLOCK(); \ 1323 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 1324 HWIO_INTFREE();\ 1325 } while (0) 1326 1327 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 1328 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 1329 1330 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 1331 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 1332 1333 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 1334 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 1335 1336 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1 //// 1337 1338 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000544) 1339 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000544) 1340 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 1341 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 1342 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 1343 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK) 1344 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 1345 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 1346 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 1347 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 1348 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 1349 do {\ 1350 HWIO_INTLOCK(); \ 1351 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 1352 HWIO_INTFREE();\ 1353 } while (0) 1354 1355 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 1356 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 1357 1358 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS //// 1359 1360 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000548) 1361 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000548) 1362 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 1363 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_SHFT 0 1364 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ 1365 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_RMSK) 1366 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 1367 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 1368 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 1369 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), val) 1370 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 1371 do {\ 1372 HWIO_INTLOCK(); \ 1373 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)); \ 1374 HWIO_INTFREE();\ 1375 } while (0) 1376 1377 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 1378 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 1379 1380 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 1381 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 1382 1383 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 1384 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 1385 1386 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER //// 1387 1388 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000054c) 1389 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000054c) 1390 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 1391 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 1392 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 1393 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK) 1394 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 1395 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 1396 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 1397 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 1398 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 1399 do {\ 1400 HWIO_INTLOCK(); \ 1401 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 1402 HWIO_INTFREE();\ 1403 } while (0) 1404 1405 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 1406 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 1407 1408 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER //// 1409 1410 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000550) 1411 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000550) 1412 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 1413 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 1414 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 1415 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK) 1416 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 1417 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 1418 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 1419 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 1420 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 1421 do {\ 1422 HWIO_INTLOCK(); \ 1423 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 1424 HWIO_INTFREE();\ 1425 } while (0) 1426 1427 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 1428 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 1429 1430 //// Register TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS //// 1431 1432 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000554) 1433 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000554) 1434 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x0fffffff 1435 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 1436 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 1437 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK) 1438 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 1439 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 1440 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 1441 out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 1442 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 1443 do {\ 1444 HWIO_INTLOCK(); \ 1445 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 1446 HWIO_INTFREE();\ 1447 } while (0) 1448 1449 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x0ff00000 1450 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x14 1451 1452 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x000fffff 1453 #define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 1454 1455 //// Register TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB //// 1456 1457 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000558) 1458 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000558) 1459 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 1460 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_SHFT 0 1461 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x) \ 1462 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_RMSK) 1463 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_INM(x, mask) \ 1464 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask) 1465 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUT(x, val) \ 1466 out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), val) 1467 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 1468 do {\ 1469 HWIO_INTLOCK(); \ 1470 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x)); \ 1471 HWIO_INTFREE();\ 1472 } while (0) 1473 1474 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 1475 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 1476 1477 //// Register TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB //// 1478 1479 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x0000055c) 1480 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x0000055c) 1481 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 1482 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_SHFT 0 1483 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x) \ 1484 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_RMSK) 1485 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_INM(x, mask) \ 1486 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask) 1487 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUT(x, val) \ 1488 out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), val) 1489 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 1490 do {\ 1491 HWIO_INTLOCK(); \ 1492 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x)); \ 1493 HWIO_INTFREE();\ 1494 } while (0) 1495 1496 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 1497 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 1498 1499 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 1500 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 1501 1502 //// Register TCL_R0_SW2TCL1_RING_MSI1_DATA //// 1503 1504 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x) (x+0x00000560) 1505 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_PHYS(x) (x+0x00000560) 1506 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_RMSK 0xffffffff 1507 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_SHFT 0 1508 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x) \ 1509 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_RMSK) 1510 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_INM(x, mask) \ 1511 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), mask) 1512 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUT(x, val) \ 1513 out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), val) 1514 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUTM(x, mask, val) \ 1515 do {\ 1516 HWIO_INTLOCK(); \ 1517 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x)); \ 1518 HWIO_INTFREE();\ 1519 } while (0) 1520 1521 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1522 #define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_SHFT 0x0 1523 1524 //// Register TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET //// 1525 1526 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000564) 1527 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000564) 1528 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 1529 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_SHFT 0 1530 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ 1531 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK) 1532 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1533 in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 1534 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 1535 out_dword( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 1536 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 1537 do {\ 1538 HWIO_INTLOCK(); \ 1539 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)); \ 1540 HWIO_INTFREE();\ 1541 } while (0) 1542 1543 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 1544 #define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1545 1546 //// Register TCL_R0_SW2TCL2_RING_BASE_LSB //// 1547 1548 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x) (x+0x00000568) 1549 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_PHYS(x) (x+0x00000568) 1550 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RMSK 0xffffffff 1551 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_SHFT 0 1552 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x) \ 1553 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RMSK) 1554 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_INM(x, mask) \ 1555 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), mask) 1556 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUT(x, val) \ 1557 out_dword( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), val) 1558 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUTM(x, mask, val) \ 1559 do {\ 1560 HWIO_INTLOCK(); \ 1561 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x)); \ 1562 HWIO_INTFREE();\ 1563 } while (0) 1564 1565 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1566 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1567 1568 //// Register TCL_R0_SW2TCL2_RING_BASE_MSB //// 1569 1570 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x) (x+0x0000056c) 1571 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_PHYS(x) (x+0x0000056c) 1572 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RMSK 0x0fffffff 1573 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_SHFT 0 1574 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x) \ 1575 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RMSK) 1576 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_INM(x, mask) \ 1577 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), mask) 1578 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUT(x, val) \ 1579 out_dword( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), val) 1580 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUTM(x, mask, val) \ 1581 do {\ 1582 HWIO_INTLOCK(); \ 1583 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x)); \ 1584 HWIO_INTFREE();\ 1585 } while (0) 1586 1587 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 1588 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1589 1590 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1591 #define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1592 1593 //// Register TCL_R0_SW2TCL2_RING_ID //// 1594 1595 #define HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x) (x+0x00000570) 1596 #define HWIO_TCL_R0_SW2TCL2_RING_ID_PHYS(x) (x+0x00000570) 1597 #define HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK 0x000000ff 1598 #define HWIO_TCL_R0_SW2TCL2_RING_ID_SHFT 0 1599 #define HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x) \ 1600 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK) 1601 #define HWIO_TCL_R0_SW2TCL2_RING_ID_INM(x, mask) \ 1602 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), mask) 1603 #define HWIO_TCL_R0_SW2TCL2_RING_ID_OUT(x, val) \ 1604 out_dword( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), val) 1605 #define HWIO_TCL_R0_SW2TCL2_RING_ID_OUTM(x, mask, val) \ 1606 do {\ 1607 HWIO_INTLOCK(); \ 1608 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x)); \ 1609 HWIO_INTFREE();\ 1610 } while (0) 1611 1612 #define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1613 #define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_SHFT 0x0 1614 1615 //// Register TCL_R0_SW2TCL2_RING_STATUS //// 1616 1617 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x) (x+0x00000574) 1618 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_PHYS(x) (x+0x00000574) 1619 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_RMSK 0xffffffff 1620 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_SHFT 0 1621 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x) \ 1622 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_STATUS_RMSK) 1623 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_INM(x, mask) \ 1624 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), mask) 1625 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_OUT(x, val) \ 1626 out_dword( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), val) 1627 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_OUTM(x, mask, val) \ 1628 do {\ 1629 HWIO_INTLOCK(); \ 1630 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x)); \ 1631 HWIO_INTFREE();\ 1632 } while (0) 1633 1634 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1635 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1636 1637 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1638 #define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1639 1640 //// Register TCL_R0_SW2TCL2_RING_MISC //// 1641 1642 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x) (x+0x00000578) 1643 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_PHYS(x) (x+0x00000578) 1644 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_RMSK 0x003fffff 1645 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SHFT 0 1646 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x) \ 1647 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MISC_RMSK) 1648 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_INM(x, mask) \ 1649 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), mask) 1650 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUT(x, val) \ 1651 out_dword( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), val) 1652 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUTM(x, mask, val) \ 1653 do {\ 1654 HWIO_INTLOCK(); \ 1655 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x)); \ 1656 HWIO_INTFREE();\ 1657 } while (0) 1658 1659 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 1660 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SPARE_CONTROL_SHFT 0xe 1661 1662 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 1663 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 1664 1665 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 1666 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 1667 1668 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 1669 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 1670 1671 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 1672 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_ENABLE_SHFT 0x6 1673 1674 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 1675 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1676 1677 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 1678 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1679 1680 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 1681 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1682 1683 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 1684 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_SHFT 0x2 1685 1686 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 1687 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1688 1689 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 1690 #define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1691 1692 //// Register TCL_R0_SW2TCL2_RING_TP_ADDR_LSB //// 1693 1694 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000584) 1695 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000584) 1696 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_RMSK 0xffffffff 1697 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_SHFT 0 1698 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x) \ 1699 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_RMSK) 1700 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_INM(x, mask) \ 1701 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), mask) 1702 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUT(x, val) \ 1703 out_dword( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), val) 1704 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 1705 do {\ 1706 HWIO_INTLOCK(); \ 1707 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x)); \ 1708 HWIO_INTFREE();\ 1709 } while (0) 1710 1711 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 1712 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 1713 1714 //// Register TCL_R0_SW2TCL2_RING_TP_ADDR_MSB //// 1715 1716 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000588) 1717 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000588) 1718 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_RMSK 0x000000ff 1719 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_SHFT 0 1720 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x) \ 1721 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_RMSK) 1722 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_INM(x, mask) \ 1723 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), mask) 1724 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUT(x, val) \ 1725 out_dword( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), val) 1726 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 1727 do {\ 1728 HWIO_INTLOCK(); \ 1729 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x)); \ 1730 HWIO_INTFREE();\ 1731 } while (0) 1732 1733 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 1734 #define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 1735 1736 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0 //// 1737 1738 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000598) 1739 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000598) 1740 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 1741 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 1742 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 1743 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_RMSK) 1744 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 1745 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 1746 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 1747 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 1748 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 1749 do {\ 1750 HWIO_INTLOCK(); \ 1751 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 1752 HWIO_INTFREE();\ 1753 } while (0) 1754 1755 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 1756 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 1757 1758 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 1759 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 1760 1761 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 1762 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 1763 1764 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1 //// 1765 1766 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x0000059c) 1767 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x0000059c) 1768 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 1769 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 1770 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 1771 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_RMSK) 1772 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 1773 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 1774 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 1775 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 1776 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 1777 do {\ 1778 HWIO_INTLOCK(); \ 1779 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 1780 HWIO_INTFREE();\ 1781 } while (0) 1782 1783 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 1784 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 1785 1786 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS //// 1787 1788 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000005a0) 1789 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000005a0) 1790 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 1791 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_SHFT 0 1792 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x) \ 1793 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_RMSK) 1794 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 1795 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 1796 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 1797 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), val) 1798 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 1799 do {\ 1800 HWIO_INTLOCK(); \ 1801 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x)); \ 1802 HWIO_INTFREE();\ 1803 } while (0) 1804 1805 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 1806 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 1807 1808 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 1809 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 1810 1811 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 1812 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 1813 1814 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER //// 1815 1816 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000005a4) 1817 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000005a4) 1818 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 1819 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 1820 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 1821 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK) 1822 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 1823 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 1824 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 1825 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 1826 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 1827 do {\ 1828 HWIO_INTLOCK(); \ 1829 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 1830 HWIO_INTFREE();\ 1831 } while (0) 1832 1833 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 1834 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 1835 1836 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER //// 1837 1838 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000005a8) 1839 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000005a8) 1840 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 1841 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 1842 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 1843 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_RMSK) 1844 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 1845 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 1846 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 1847 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 1848 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 1849 do {\ 1850 HWIO_INTLOCK(); \ 1851 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 1852 HWIO_INTFREE();\ 1853 } while (0) 1854 1855 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 1856 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 1857 1858 //// Register TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS //// 1859 1860 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000005ac) 1861 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000005ac) 1862 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x0fffffff 1863 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 1864 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 1865 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_RMSK) 1866 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 1867 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 1868 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 1869 out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 1870 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 1871 do {\ 1872 HWIO_INTLOCK(); \ 1873 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 1874 HWIO_INTFREE();\ 1875 } while (0) 1876 1877 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x0ff00000 1878 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x14 1879 1880 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x000fffff 1881 #define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 1882 1883 //// Register TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB //// 1884 1885 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000005b0) 1886 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000005b0) 1887 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_RMSK 0xffffffff 1888 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_SHFT 0 1889 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x) \ 1890 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_RMSK) 1891 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_INM(x, mask) \ 1892 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), mask) 1893 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUT(x, val) \ 1894 out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), val) 1895 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 1896 do {\ 1897 HWIO_INTLOCK(); \ 1898 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x)); \ 1899 HWIO_INTFREE();\ 1900 } while (0) 1901 1902 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 1903 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 1904 1905 //// Register TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB //// 1906 1907 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000005b4) 1908 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000005b4) 1909 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_RMSK 0x000001ff 1910 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_SHFT 0 1911 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x) \ 1912 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_RMSK) 1913 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_INM(x, mask) \ 1914 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), mask) 1915 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUT(x, val) \ 1916 out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), val) 1917 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 1918 do {\ 1919 HWIO_INTLOCK(); \ 1920 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x)); \ 1921 HWIO_INTFREE();\ 1922 } while (0) 1923 1924 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 1925 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 1926 1927 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 1928 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 1929 1930 //// Register TCL_R0_SW2TCL2_RING_MSI1_DATA //// 1931 1932 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x) (x+0x000005b8) 1933 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_PHYS(x) (x+0x000005b8) 1934 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_RMSK 0xffffffff 1935 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_SHFT 0 1936 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x) \ 1937 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_RMSK) 1938 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_INM(x, mask) \ 1939 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), mask) 1940 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUT(x, val) \ 1941 out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), val) 1942 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUTM(x, mask, val) \ 1943 do {\ 1944 HWIO_INTLOCK(); \ 1945 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x)); \ 1946 HWIO_INTFREE();\ 1947 } while (0) 1948 1949 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1950 #define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_SHFT 0x0 1951 1952 //// Register TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET //// 1953 1954 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000005bc) 1955 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000005bc) 1956 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 1957 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_SHFT 0 1958 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x) \ 1959 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK) 1960 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1961 in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 1962 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 1963 out_dword( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), val) 1964 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 1965 do {\ 1966 HWIO_INTLOCK(); \ 1967 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x)); \ 1968 HWIO_INTFREE();\ 1969 } while (0) 1970 1971 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 1972 #define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1973 1974 //// Register TCL_R0_SW2TCL3_RING_BASE_LSB //// 1975 1976 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x) (x+0x000005c0) 1977 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_PHYS(x) (x+0x000005c0) 1978 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RMSK 0xffffffff 1979 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_SHFT 0 1980 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x) \ 1981 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RMSK) 1982 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_INM(x, mask) \ 1983 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), mask) 1984 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUT(x, val) \ 1985 out_dword( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), val) 1986 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUTM(x, mask, val) \ 1987 do {\ 1988 HWIO_INTLOCK(); \ 1989 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x)); \ 1990 HWIO_INTFREE();\ 1991 } while (0) 1992 1993 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1994 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1995 1996 //// Register TCL_R0_SW2TCL3_RING_BASE_MSB //// 1997 1998 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x) (x+0x000005c4) 1999 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_PHYS(x) (x+0x000005c4) 2000 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RMSK 0x0fffffff 2001 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_SHFT 0 2002 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x) \ 2003 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RMSK) 2004 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_INM(x, mask) \ 2005 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), mask) 2006 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUT(x, val) \ 2007 out_dword( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), val) 2008 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUTM(x, mask, val) \ 2009 do {\ 2010 HWIO_INTLOCK(); \ 2011 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x)); \ 2012 HWIO_INTFREE();\ 2013 } while (0) 2014 2015 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 2016 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2017 2018 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 2019 #define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2020 2021 //// Register TCL_R0_SW2TCL3_RING_ID //// 2022 2023 #define HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x) (x+0x000005c8) 2024 #define HWIO_TCL_R0_SW2TCL3_RING_ID_PHYS(x) (x+0x000005c8) 2025 #define HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK 0x000000ff 2026 #define HWIO_TCL_R0_SW2TCL3_RING_ID_SHFT 0 2027 #define HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x) \ 2028 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK) 2029 #define HWIO_TCL_R0_SW2TCL3_RING_ID_INM(x, mask) \ 2030 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), mask) 2031 #define HWIO_TCL_R0_SW2TCL3_RING_ID_OUT(x, val) \ 2032 out_dword( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), val) 2033 #define HWIO_TCL_R0_SW2TCL3_RING_ID_OUTM(x, mask, val) \ 2034 do {\ 2035 HWIO_INTLOCK(); \ 2036 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x)); \ 2037 HWIO_INTFREE();\ 2038 } while (0) 2039 2040 #define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 2041 #define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_SHFT 0x0 2042 2043 //// Register TCL_R0_SW2TCL3_RING_STATUS //// 2044 2045 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x) (x+0x000005cc) 2046 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_PHYS(x) (x+0x000005cc) 2047 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_RMSK 0xffffffff 2048 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_SHFT 0 2049 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x) \ 2050 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_STATUS_RMSK) 2051 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_INM(x, mask) \ 2052 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), mask) 2053 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_OUT(x, val) \ 2054 out_dword( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), val) 2055 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_OUTM(x, mask, val) \ 2056 do {\ 2057 HWIO_INTLOCK(); \ 2058 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x)); \ 2059 HWIO_INTFREE();\ 2060 } while (0) 2061 2062 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2063 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2064 2065 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 2066 #define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2067 2068 //// Register TCL_R0_SW2TCL3_RING_MISC //// 2069 2070 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x) (x+0x000005d0) 2071 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_PHYS(x) (x+0x000005d0) 2072 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_RMSK 0x003fffff 2073 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SHFT 0 2074 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x) \ 2075 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MISC_RMSK) 2076 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_INM(x, mask) \ 2077 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), mask) 2078 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUT(x, val) \ 2079 out_dword( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), val) 2080 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUTM(x, mask, val) \ 2081 do {\ 2082 HWIO_INTLOCK(); \ 2083 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x)); \ 2084 HWIO_INTFREE();\ 2085 } while (0) 2086 2087 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 2088 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SPARE_CONTROL_SHFT 0xe 2089 2090 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 2091 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2092 2093 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 2094 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2095 2096 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 2097 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2098 2099 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 2100 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_ENABLE_SHFT 0x6 2101 2102 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2103 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2104 2105 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2106 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2107 2108 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2109 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2110 2111 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2112 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_SHFT 0x2 2113 2114 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2115 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2116 2117 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2118 #define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2119 2120 //// Register TCL_R0_SW2TCL3_RING_TP_ADDR_LSB //// 2121 2122 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x) (x+0x000005dc) 2123 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_PHYS(x) (x+0x000005dc) 2124 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_RMSK 0xffffffff 2125 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_SHFT 0 2126 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x) \ 2127 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_RMSK) 2128 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_INM(x, mask) \ 2129 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), mask) 2130 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUT(x, val) \ 2131 out_dword( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), val) 2132 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2133 do {\ 2134 HWIO_INTLOCK(); \ 2135 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x)); \ 2136 HWIO_INTFREE();\ 2137 } while (0) 2138 2139 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2140 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2141 2142 //// Register TCL_R0_SW2TCL3_RING_TP_ADDR_MSB //// 2143 2144 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x) (x+0x000005e0) 2145 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_PHYS(x) (x+0x000005e0) 2146 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_RMSK 0x000000ff 2147 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_SHFT 0 2148 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x) \ 2149 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_RMSK) 2150 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_INM(x, mask) \ 2151 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), mask) 2152 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUT(x, val) \ 2153 out_dword( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), val) 2154 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2155 do {\ 2156 HWIO_INTLOCK(); \ 2157 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x)); \ 2158 HWIO_INTFREE();\ 2159 } while (0) 2160 2161 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 2162 #define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2163 2164 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0 //// 2165 2166 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000005f0) 2167 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000005f0) 2168 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2169 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 2170 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 2171 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2172 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 2173 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 2174 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 2175 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 2176 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 2177 do {\ 2178 HWIO_INTLOCK(); \ 2179 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 2180 HWIO_INTFREE();\ 2181 } while (0) 2182 2183 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2184 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2185 2186 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 2187 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2188 2189 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2190 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2191 2192 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1 //// 2193 2194 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000005f4) 2195 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000005f4) 2196 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 2197 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 2198 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 2199 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2200 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 2201 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 2202 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 2203 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 2204 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 2205 do {\ 2206 HWIO_INTLOCK(); \ 2207 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 2208 HWIO_INTFREE();\ 2209 } while (0) 2210 2211 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 2212 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2213 2214 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS //// 2215 2216 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000005f8) 2217 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000005f8) 2218 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2219 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_SHFT 0 2220 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x) \ 2221 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_RMSK) 2222 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 2223 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 2224 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 2225 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), val) 2226 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 2227 do {\ 2228 HWIO_INTLOCK(); \ 2229 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x)); \ 2230 HWIO_INTFREE();\ 2231 } while (0) 2232 2233 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2234 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2235 2236 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 2237 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2238 2239 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2240 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2241 2242 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER //// 2243 2244 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000005fc) 2245 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000005fc) 2246 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 2247 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 2248 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 2249 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2250 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 2251 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 2252 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 2253 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 2254 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 2255 do {\ 2256 HWIO_INTLOCK(); \ 2257 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 2258 HWIO_INTFREE();\ 2259 } while (0) 2260 2261 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 2262 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2263 2264 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER //// 2265 2266 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000600) 2267 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000600) 2268 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 2269 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 2270 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 2271 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2272 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 2273 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 2274 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 2275 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 2276 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 2277 do {\ 2278 HWIO_INTLOCK(); \ 2279 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 2280 HWIO_INTFREE();\ 2281 } while (0) 2282 2283 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 2284 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2285 2286 //// Register TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS //// 2287 2288 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000604) 2289 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000604) 2290 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x0fffffff 2291 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 2292 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 2293 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2294 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 2295 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 2296 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 2297 out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 2298 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 2299 do {\ 2300 HWIO_INTLOCK(); \ 2301 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 2302 HWIO_INTFREE();\ 2303 } while (0) 2304 2305 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x0ff00000 2306 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x14 2307 2308 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x000fffff 2309 #define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 2310 2311 //// Register TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB //// 2312 2313 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000608) 2314 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000608) 2315 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_RMSK 0xffffffff 2316 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_SHFT 0 2317 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x) \ 2318 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_RMSK) 2319 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_INM(x, mask) \ 2320 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), mask) 2321 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUT(x, val) \ 2322 out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), val) 2323 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 2324 do {\ 2325 HWIO_INTLOCK(); \ 2326 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x)); \ 2327 HWIO_INTFREE();\ 2328 } while (0) 2329 2330 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 2331 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 2332 2333 //// Register TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB //// 2334 2335 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x) (x+0x0000060c) 2336 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_PHYS(x) (x+0x0000060c) 2337 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_RMSK 0x000001ff 2338 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_SHFT 0 2339 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x) \ 2340 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_RMSK) 2341 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_INM(x, mask) \ 2342 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), mask) 2343 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUT(x, val) \ 2344 out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), val) 2345 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 2346 do {\ 2347 HWIO_INTLOCK(); \ 2348 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x)); \ 2349 HWIO_INTFREE();\ 2350 } while (0) 2351 2352 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 2353 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 2354 2355 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 2356 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 2357 2358 //// Register TCL_R0_SW2TCL3_RING_MSI1_DATA //// 2359 2360 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x) (x+0x00000610) 2361 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_PHYS(x) (x+0x00000610) 2362 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_RMSK 0xffffffff 2363 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_SHFT 0 2364 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x) \ 2365 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_RMSK) 2366 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_INM(x, mask) \ 2367 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), mask) 2368 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUT(x, val) \ 2369 out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), val) 2370 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUTM(x, mask, val) \ 2371 do {\ 2372 HWIO_INTLOCK(); \ 2373 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x)); \ 2374 HWIO_INTFREE();\ 2375 } while (0) 2376 2377 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 2378 #define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_SHFT 0x0 2379 2380 //// Register TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET //// 2381 2382 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000614) 2383 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000614) 2384 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 2385 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_SHFT 0 2386 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x) \ 2387 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK) 2388 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 2389 in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 2390 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 2391 out_dword( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), val) 2392 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 2393 do {\ 2394 HWIO_INTLOCK(); \ 2395 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x)); \ 2396 HWIO_INTFREE();\ 2397 } while (0) 2398 2399 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 2400 #define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 2401 2402 //// Register TCL_R0_SW2TCL_CMD_RING_BASE_LSB //// 2403 2404 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x) (x+0x00000618) 2405 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_PHYS(x) (x+0x00000618) 2406 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RMSK 0xffffffff 2407 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_SHFT 0 2408 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_IN(x) \ 2409 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RMSK) 2410 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_INM(x, mask) \ 2411 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), mask) 2412 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_OUT(x, val) \ 2413 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), val) 2414 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_OUTM(x, mask, val) \ 2415 do {\ 2416 HWIO_INTLOCK(); \ 2417 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_IN(x)); \ 2418 HWIO_INTFREE();\ 2419 } while (0) 2420 2421 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 2422 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 2423 2424 //// Register TCL_R0_SW2TCL_CMD_RING_BASE_MSB //// 2425 2426 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x) (x+0x0000061c) 2427 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_PHYS(x) (x+0x0000061c) 2428 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RMSK 0x0fffffff 2429 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_SHFT 0 2430 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_IN(x) \ 2431 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RMSK) 2432 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_INM(x, mask) \ 2433 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), mask) 2434 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_OUT(x, val) \ 2435 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), val) 2436 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_OUTM(x, mask, val) \ 2437 do {\ 2438 HWIO_INTLOCK(); \ 2439 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_IN(x)); \ 2440 HWIO_INTFREE();\ 2441 } while (0) 2442 2443 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 2444 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2445 2446 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 2447 #define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2448 2449 //// Register TCL_R0_SW2TCL_CMD_RING_ID //// 2450 2451 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x) (x+0x00000620) 2452 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_PHYS(x) (x+0x00000620) 2453 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RMSK 0x000000ff 2454 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_SHFT 0 2455 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_IN(x) \ 2456 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RMSK) 2457 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_INM(x, mask) \ 2458 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), mask) 2459 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_OUT(x, val) \ 2460 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), val) 2461 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_OUTM(x, mask, val) \ 2462 do {\ 2463 HWIO_INTLOCK(); \ 2464 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_ID_IN(x)); \ 2465 HWIO_INTFREE();\ 2466 } while (0) 2467 2468 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 2469 #define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ENTRY_SIZE_SHFT 0x0 2470 2471 //// Register TCL_R0_SW2TCL_CMD_RING_STATUS //// 2472 2473 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x) (x+0x00000624) 2474 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_PHYS(x) (x+0x00000624) 2475 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_RMSK 0xffffffff 2476 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_SHFT 0 2477 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_IN(x) \ 2478 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_RMSK) 2479 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_INM(x, mask) \ 2480 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), mask) 2481 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_OUT(x, val) \ 2482 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), val) 2483 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_OUTM(x, mask, val) \ 2484 do {\ 2485 HWIO_INTLOCK(); \ 2486 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_IN(x)); \ 2487 HWIO_INTFREE();\ 2488 } while (0) 2489 2490 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2491 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2492 2493 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 2494 #define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2495 2496 //// Register TCL_R0_SW2TCL_CMD_RING_MISC //// 2497 2498 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x) (x+0x00000628) 2499 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_PHYS(x) (x+0x00000628) 2500 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RMSK 0x003fffff 2501 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SHFT 0 2502 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_IN(x) \ 2503 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RMSK) 2504 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_INM(x, mask) \ 2505 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), mask) 2506 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_OUT(x, val) \ 2507 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), val) 2508 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_OUTM(x, mask, val) \ 2509 do {\ 2510 HWIO_INTLOCK(); \ 2511 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_IN(x)); \ 2512 HWIO_INTFREE();\ 2513 } while (0) 2514 2515 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 2516 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SPARE_CONTROL_SHFT 0xe 2517 2518 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 2519 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2520 2521 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 2522 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2523 2524 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 2525 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2526 2527 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 2528 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SRNG_ENABLE_SHFT 0x6 2529 2530 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2531 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2532 2533 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2534 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2535 2536 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2537 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2538 2539 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2540 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SECURITY_BIT_SHFT 0x2 2541 2542 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2543 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2544 2545 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2546 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2547 2548 //// Register TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB //// 2549 2550 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000634) 2551 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000634) 2552 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_RMSK 0xffffffff 2553 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_SHFT 0 2554 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_IN(x) \ 2555 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_RMSK) 2556 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_INM(x, mask) \ 2557 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), mask) 2558 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_OUT(x, val) \ 2559 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), val) 2560 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2561 do {\ 2562 HWIO_INTLOCK(); \ 2563 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_IN(x)); \ 2564 HWIO_INTFREE();\ 2565 } while (0) 2566 2567 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2568 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2569 2570 //// Register TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB //// 2571 2572 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000638) 2573 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000638) 2574 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_RMSK 0x000000ff 2575 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_SHFT 0 2576 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_IN(x) \ 2577 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_RMSK) 2578 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_INM(x, mask) \ 2579 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), mask) 2580 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_OUT(x, val) \ 2581 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), val) 2582 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 2583 do {\ 2584 HWIO_INTLOCK(); \ 2585 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_IN(x)); \ 2586 HWIO_INTFREE();\ 2587 } while (0) 2588 2589 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 2590 #define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 2591 2592 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0 //// 2593 2594 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000648) 2595 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000648) 2596 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 2597 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 2598 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 2599 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK) 2600 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 2601 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 2602 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 2603 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 2604 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 2605 do {\ 2606 HWIO_INTLOCK(); \ 2607 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 2608 HWIO_INTFREE();\ 2609 } while (0) 2610 2611 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 2612 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 2613 2614 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 2615 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 2616 2617 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 2618 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 2619 2620 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1 //// 2621 2622 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x0000064c) 2623 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x0000064c) 2624 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 2625 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 2626 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 2627 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK) 2628 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 2629 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 2630 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 2631 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 2632 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 2633 do {\ 2634 HWIO_INTLOCK(); \ 2635 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 2636 HWIO_INTFREE();\ 2637 } while (0) 2638 2639 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 2640 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 2641 2642 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS //// 2643 2644 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000650) 2645 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000650) 2646 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 2647 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_SHFT 0 2648 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_IN(x) \ 2649 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_RMSK) 2650 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 2651 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 2652 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 2653 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), val) 2654 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 2655 do {\ 2656 HWIO_INTLOCK(); \ 2657 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_IN(x)); \ 2658 HWIO_INTFREE();\ 2659 } while (0) 2660 2661 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 2662 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 2663 2664 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 2665 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 2666 2667 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 2668 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 2669 2670 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER //// 2671 2672 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000654) 2673 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000654) 2674 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 2675 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 2676 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 2677 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK) 2678 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 2679 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 2680 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 2681 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 2682 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 2683 do {\ 2684 HWIO_INTLOCK(); \ 2685 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 2686 HWIO_INTFREE();\ 2687 } while (0) 2688 2689 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 2690 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 2691 2692 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER //// 2693 2694 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000658) 2695 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000658) 2696 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 2697 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 2698 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 2699 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK) 2700 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 2701 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 2702 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 2703 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 2704 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 2705 do {\ 2706 HWIO_INTLOCK(); \ 2707 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 2708 HWIO_INTFREE();\ 2709 } while (0) 2710 2711 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 2712 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 2713 2714 //// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS //// 2715 2716 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x0000065c) 2717 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x0000065c) 2718 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x0fffffff 2719 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 2720 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 2721 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK) 2722 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 2723 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 2724 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 2725 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 2726 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 2727 do {\ 2728 HWIO_INTLOCK(); \ 2729 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 2730 HWIO_INTFREE();\ 2731 } while (0) 2732 2733 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x0ff00000 2734 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x14 2735 2736 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x000fffff 2737 #define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 2738 2739 //// Register TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB //// 2740 2741 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000660) 2742 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000660) 2743 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_RMSK 0xffffffff 2744 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_SHFT 0 2745 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_IN(x) \ 2746 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_RMSK) 2747 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_INM(x, mask) \ 2748 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask) 2749 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_OUT(x, val) \ 2750 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), val) 2751 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 2752 do {\ 2753 HWIO_INTLOCK(); \ 2754 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_IN(x)); \ 2755 HWIO_INTFREE();\ 2756 } while (0) 2757 2758 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 2759 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 2760 2761 //// Register TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB //// 2762 2763 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000664) 2764 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000664) 2765 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_RMSK 0x000001ff 2766 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_SHFT 0 2767 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_IN(x) \ 2768 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_RMSK) 2769 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_INM(x, mask) \ 2770 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask) 2771 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_OUT(x, val) \ 2772 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), val) 2773 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 2774 do {\ 2775 HWIO_INTLOCK(); \ 2776 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_IN(x)); \ 2777 HWIO_INTFREE();\ 2778 } while (0) 2779 2780 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 2781 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 2782 2783 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 2784 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 2785 2786 //// Register TCL_R0_SW2TCL_CMD_RING_MSI1_DATA //// 2787 2788 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x) (x+0x00000668) 2789 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_PHYS(x) (x+0x00000668) 2790 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_RMSK 0xffffffff 2791 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_SHFT 0 2792 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_IN(x) \ 2793 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_RMSK) 2794 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_INM(x, mask) \ 2795 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), mask) 2796 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_OUT(x, val) \ 2797 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), val) 2798 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_OUTM(x, mask, val) \ 2799 do {\ 2800 HWIO_INTLOCK(); \ 2801 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_IN(x)); \ 2802 HWIO_INTFREE();\ 2803 } while (0) 2804 2805 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 2806 #define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_VALUE_SHFT 0x0 2807 2808 //// Register TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET //// 2809 2810 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000066c) 2811 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000066c) 2812 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 2813 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_SHFT 0 2814 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_IN(x) \ 2815 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_RMSK) 2816 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 2817 in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 2818 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 2819 out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), val) 2820 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 2821 do {\ 2822 HWIO_INTLOCK(); \ 2823 out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_IN(x)); \ 2824 HWIO_INTFREE();\ 2825 } while (0) 2826 2827 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 2828 #define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 2829 2830 //// Register TCL_R0_FW2TCL1_RING_BASE_LSB //// 2831 2832 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x) (x+0x00000670) 2833 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_PHYS(x) (x+0x00000670) 2834 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RMSK 0xffffffff 2835 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_SHFT 0 2836 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x) \ 2837 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RMSK) 2838 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_INM(x, mask) \ 2839 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), mask) 2840 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUT(x, val) \ 2841 out_dword( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), val) 2842 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUTM(x, mask, val) \ 2843 do {\ 2844 HWIO_INTLOCK(); \ 2845 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x)); \ 2846 HWIO_INTFREE();\ 2847 } while (0) 2848 2849 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 2850 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 2851 2852 //// Register TCL_R0_FW2TCL1_RING_BASE_MSB //// 2853 2854 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x) (x+0x00000674) 2855 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_PHYS(x) (x+0x00000674) 2856 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RMSK 0x00ffffff 2857 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_SHFT 0 2858 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x) \ 2859 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RMSK) 2860 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_INM(x, mask) \ 2861 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), mask) 2862 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUT(x, val) \ 2863 out_dword( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), val) 2864 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUTM(x, mask, val) \ 2865 do {\ 2866 HWIO_INTLOCK(); \ 2867 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x)); \ 2868 HWIO_INTFREE();\ 2869 } while (0) 2870 2871 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 2872 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 2873 2874 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 2875 #define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 2876 2877 //// Register TCL_R0_FW2TCL1_RING_ID //// 2878 2879 #define HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x) (x+0x00000678) 2880 #define HWIO_TCL_R0_FW2TCL1_RING_ID_PHYS(x) (x+0x00000678) 2881 #define HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK 0x000000ff 2882 #define HWIO_TCL_R0_FW2TCL1_RING_ID_SHFT 0 2883 #define HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x) \ 2884 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK) 2885 #define HWIO_TCL_R0_FW2TCL1_RING_ID_INM(x, mask) \ 2886 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), mask) 2887 #define HWIO_TCL_R0_FW2TCL1_RING_ID_OUT(x, val) \ 2888 out_dword( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), val) 2889 #define HWIO_TCL_R0_FW2TCL1_RING_ID_OUTM(x, mask, val) \ 2890 do {\ 2891 HWIO_INTLOCK(); \ 2892 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x)); \ 2893 HWIO_INTFREE();\ 2894 } while (0) 2895 2896 #define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 2897 #define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0x0 2898 2899 //// Register TCL_R0_FW2TCL1_RING_STATUS //// 2900 2901 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x) (x+0x0000067c) 2902 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_PHYS(x) (x+0x0000067c) 2903 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_RMSK 0xffffffff 2904 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_SHFT 0 2905 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_IN(x) \ 2906 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_STATUS_RMSK) 2907 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_INM(x, mask) \ 2908 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), mask) 2909 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_OUT(x, val) \ 2910 out_dword( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), val) 2911 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_OUTM(x, mask, val) \ 2912 do {\ 2913 HWIO_INTLOCK(); \ 2914 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_STATUS_IN(x)); \ 2915 HWIO_INTFREE();\ 2916 } while (0) 2917 2918 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 2919 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 2920 2921 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 2922 #define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 2923 2924 //// Register TCL_R0_FW2TCL1_RING_MISC //// 2925 2926 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x) (x+0x00000680) 2927 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_PHYS(x) (x+0x00000680) 2928 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_RMSK 0x003fffff 2929 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SHFT 0 2930 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x) \ 2931 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MISC_RMSK) 2932 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_INM(x, mask) \ 2933 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), mask) 2934 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUT(x, val) \ 2935 out_dword( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), val) 2936 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUTM(x, mask, val) \ 2937 do {\ 2938 HWIO_INTLOCK(); \ 2939 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x)); \ 2940 HWIO_INTFREE();\ 2941 } while (0) 2942 2943 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 2944 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SPARE_CONTROL_SHFT 0xe 2945 2946 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 2947 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 2948 2949 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 2950 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 2951 2952 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 2953 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 2954 2955 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 2956 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_ENABLE_SHFT 0x6 2957 2958 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 2959 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 2960 2961 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 2962 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 2963 2964 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 2965 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 2966 2967 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 2968 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_SECURITY_BIT_SHFT 0x2 2969 2970 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 2971 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 2972 2973 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 2974 #define HWIO_TCL_R0_FW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 2975 2976 //// Register TCL_R0_FW2TCL1_RING_TP_ADDR_LSB //// 2977 2978 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x) (x+0x0000068c) 2979 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_PHYS(x) (x+0x0000068c) 2980 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff 2981 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_SHFT 0 2982 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x) \ 2983 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_RMSK) 2984 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_INM(x, mask) \ 2985 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask) 2986 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUT(x, val) \ 2987 out_dword( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), val) 2988 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 2989 do {\ 2990 HWIO_INTLOCK(); \ 2991 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x)); \ 2992 HWIO_INTFREE();\ 2993 } while (0) 2994 2995 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 2996 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 2997 2998 //// Register TCL_R0_FW2TCL1_RING_TP_ADDR_MSB //// 2999 3000 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000690) 3001 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000690) 3002 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_RMSK 0x000000ff 3003 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_SHFT 0 3004 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x) \ 3005 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_RMSK) 3006 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_INM(x, mask) \ 3007 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask) 3008 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUT(x, val) \ 3009 out_dword( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), val) 3010 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 3011 do {\ 3012 HWIO_INTLOCK(); \ 3013 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x)); \ 3014 HWIO_INTFREE();\ 3015 } while (0) 3016 3017 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 3018 #define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 3019 3020 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0 //// 3021 3022 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000006a0) 3023 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000006a0) 3024 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 3025 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 3026 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 3027 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK) 3028 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 3029 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 3030 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 3031 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 3032 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 3033 do {\ 3034 HWIO_INTLOCK(); \ 3035 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 3036 HWIO_INTFREE();\ 3037 } while (0) 3038 3039 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3040 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3041 3042 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 3043 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 3044 3045 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3046 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3047 3048 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1 //// 3049 3050 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000006a4) 3051 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000006a4) 3052 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 3053 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 3054 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 3055 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK) 3056 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 3057 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 3058 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 3059 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 3060 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 3061 do {\ 3062 HWIO_INTLOCK(); \ 3063 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 3064 HWIO_INTFREE();\ 3065 } while (0) 3066 3067 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 3068 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 3069 3070 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS //// 3071 3072 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000006a8) 3073 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000006a8) 3074 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 3075 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_SHFT 0 3076 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ 3077 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_RMSK) 3078 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 3079 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 3080 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 3081 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), val) 3082 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 3083 do {\ 3084 HWIO_INTLOCK(); \ 3085 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)); \ 3086 HWIO_INTFREE();\ 3087 } while (0) 3088 3089 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3090 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3091 3092 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 3093 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 3094 3095 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3096 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3097 3098 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER //// 3099 3100 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000006ac) 3101 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000006ac) 3102 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 3103 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 3104 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 3105 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK) 3106 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 3107 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 3108 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 3109 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 3110 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 3111 do {\ 3112 HWIO_INTLOCK(); \ 3113 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 3114 HWIO_INTFREE();\ 3115 } while (0) 3116 3117 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 3118 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 3119 3120 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER //// 3121 3122 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000006b0) 3123 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000006b0) 3124 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 3125 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 3126 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 3127 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK) 3128 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 3129 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 3130 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 3131 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 3132 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 3133 do {\ 3134 HWIO_INTLOCK(); \ 3135 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 3136 HWIO_INTFREE();\ 3137 } while (0) 3138 3139 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 3140 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 3141 3142 //// Register TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS //// 3143 3144 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000006b4) 3145 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000006b4) 3146 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 3147 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 3148 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 3149 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK) 3150 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 3151 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 3152 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 3153 out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 3154 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 3155 do {\ 3156 HWIO_INTLOCK(); \ 3157 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 3158 HWIO_INTFREE();\ 3159 } while (0) 3160 3161 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 3162 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 3163 3164 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 3165 #define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 3166 3167 //// Register TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB //// 3168 3169 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000006b8) 3170 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000006b8) 3171 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3172 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_SHFT 0 3173 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x) \ 3174 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_RMSK) 3175 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_INM(x, mask) \ 3176 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask) 3177 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUT(x, val) \ 3178 out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), val) 3179 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3180 do {\ 3181 HWIO_INTLOCK(); \ 3182 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x)); \ 3183 HWIO_INTFREE();\ 3184 } while (0) 3185 3186 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3187 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3188 3189 //// Register TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB //// 3190 3191 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000006bc) 3192 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000006bc) 3193 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3194 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_SHFT 0 3195 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x) \ 3196 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_RMSK) 3197 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_INM(x, mask) \ 3198 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask) 3199 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUT(x, val) \ 3200 out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), val) 3201 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3202 do {\ 3203 HWIO_INTLOCK(); \ 3204 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x)); \ 3205 HWIO_INTFREE();\ 3206 } while (0) 3207 3208 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3209 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3210 3211 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3212 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3213 3214 //// Register TCL_R0_FW2TCL1_RING_MSI1_DATA //// 3215 3216 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x) (x+0x000006c0) 3217 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_PHYS(x) (x+0x000006c0) 3218 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_RMSK 0xffffffff 3219 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_SHFT 0 3220 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x) \ 3221 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_RMSK) 3222 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_INM(x, mask) \ 3223 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), mask) 3224 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUT(x, val) \ 3225 out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), val) 3226 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUTM(x, mask, val) \ 3227 do {\ 3228 HWIO_INTLOCK(); \ 3229 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x)); \ 3230 HWIO_INTFREE();\ 3231 } while (0) 3232 3233 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3234 #define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_SHFT 0x0 3235 3236 //// Register TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET //// 3237 3238 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000006c4) 3239 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000006c4) 3240 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3241 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_SHFT 0 3242 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ 3243 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK) 3244 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3245 in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3246 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3247 out_dword( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3248 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3249 do {\ 3250 HWIO_INTLOCK(); \ 3251 out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)); \ 3252 HWIO_INTFREE();\ 3253 } while (0) 3254 3255 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3256 #define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3257 3258 //// Register TCL_R0_TCL2TQM_RING_BASE_LSB //// 3259 3260 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x) (x+0x000006c8) 3261 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_PHYS(x) (x+0x000006c8) 3262 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RMSK 0xffffffff 3263 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_SHFT 0 3264 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x) \ 3265 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RMSK) 3266 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_INM(x, mask) \ 3267 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), mask) 3268 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUT(x, val) \ 3269 out_dword( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), val) 3270 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUTM(x, mask, val) \ 3271 do {\ 3272 HWIO_INTLOCK(); \ 3273 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x)); \ 3274 HWIO_INTFREE();\ 3275 } while (0) 3276 3277 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3278 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3279 3280 //// Register TCL_R0_TCL2TQM_RING_BASE_MSB //// 3281 3282 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x) (x+0x000006cc) 3283 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_PHYS(x) (x+0x000006cc) 3284 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RMSK 0x00ffffff 3285 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_SHFT 0 3286 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x) \ 3287 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RMSK) 3288 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_INM(x, mask) \ 3289 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), mask) 3290 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUT(x, val) \ 3291 out_dword( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), val) 3292 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUTM(x, mask, val) \ 3293 do {\ 3294 HWIO_INTLOCK(); \ 3295 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x)); \ 3296 HWIO_INTFREE();\ 3297 } while (0) 3298 3299 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 3300 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3301 3302 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3303 #define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3304 3305 //// Register TCL_R0_TCL2TQM_RING_ID //// 3306 3307 #define HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x) (x+0x000006d0) 3308 #define HWIO_TCL_R0_TCL2TQM_RING_ID_PHYS(x) (x+0x000006d0) 3309 #define HWIO_TCL_R0_TCL2TQM_RING_ID_RMSK 0x0000ffff 3310 #define HWIO_TCL_R0_TCL2TQM_RING_ID_SHFT 0 3311 #define HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x) \ 3312 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_ID_RMSK) 3313 #define HWIO_TCL_R0_TCL2TQM_RING_ID_INM(x, mask) \ 3314 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), mask) 3315 #define HWIO_TCL_R0_TCL2TQM_RING_ID_OUT(x, val) \ 3316 out_dword( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), val) 3317 #define HWIO_TCL_R0_TCL2TQM_RING_ID_OUTM(x, mask, val) \ 3318 do {\ 3319 HWIO_INTLOCK(); \ 3320 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x)); \ 3321 HWIO_INTFREE();\ 3322 } while (0) 3323 3324 #define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_BMSK 0x0000ff00 3325 #define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_SHFT 0x8 3326 3327 #define HWIO_TCL_R0_TCL2TQM_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3328 #define HWIO_TCL_R0_TCL2TQM_RING_ID_ENTRY_SIZE_SHFT 0x0 3329 3330 //// Register TCL_R0_TCL2TQM_RING_STATUS //// 3331 3332 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x) (x+0x000006d4) 3333 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_PHYS(x) (x+0x000006d4) 3334 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_RMSK 0xffffffff 3335 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_SHFT 0 3336 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_IN(x) \ 3337 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_STATUS_RMSK) 3338 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_INM(x, mask) \ 3339 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), mask) 3340 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_OUT(x, val) \ 3341 out_dword( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), val) 3342 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_OUTM(x, mask, val) \ 3343 do {\ 3344 HWIO_INTLOCK(); \ 3345 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_STATUS_IN(x)); \ 3346 HWIO_INTFREE();\ 3347 } while (0) 3348 3349 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3350 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3351 3352 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3353 #define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3354 3355 //// Register TCL_R0_TCL2TQM_RING_MISC //// 3356 3357 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x) (x+0x000006d8) 3358 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_PHYS(x) (x+0x000006d8) 3359 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_RMSK 0x03ffffff 3360 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SHFT 0 3361 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x) \ 3362 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_MISC_RMSK) 3363 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_INM(x, mask) \ 3364 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), mask) 3365 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUT(x, val) \ 3366 out_dword( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), val) 3367 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUTM(x, mask, val) \ 3368 do {\ 3369 HWIO_INTLOCK(); \ 3370 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x)); \ 3371 HWIO_INTFREE();\ 3372 } while (0) 3373 3374 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOP_CNT_BMSK 0x03c00000 3375 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOP_CNT_SHFT 0x16 3376 3377 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 3378 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SPARE_CONTROL_SHFT 0xe 3379 3380 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 3381 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3382 3383 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 3384 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3385 3386 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 3387 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3388 3389 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 3390 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_ENABLE_SHFT 0x6 3391 3392 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3393 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3394 3395 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3396 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3397 3398 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3399 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3400 3401 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3402 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_SECURITY_BIT_SHFT 0x2 3403 3404 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3405 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3406 3407 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3408 #define HWIO_TCL_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3409 3410 //// Register TCL_R0_TCL2TQM_RING_HP_ADDR_LSB //// 3411 3412 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x) (x+0x000006dc) 3413 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_PHYS(x) (x+0x000006dc) 3414 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_RMSK 0xffffffff 3415 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_SHFT 0 3416 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x) \ 3417 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_RMSK) 3418 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_INM(x, mask) \ 3419 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), mask) 3420 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUT(x, val) \ 3421 out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), val) 3422 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 3423 do {\ 3424 HWIO_INTLOCK(); \ 3425 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x)); \ 3426 HWIO_INTFREE();\ 3427 } while (0) 3428 3429 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 3430 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 3431 3432 //// Register TCL_R0_TCL2TQM_RING_HP_ADDR_MSB //// 3433 3434 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x) (x+0x000006e0) 3435 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_PHYS(x) (x+0x000006e0) 3436 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_RMSK 0x000000ff 3437 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_SHFT 0 3438 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x) \ 3439 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_RMSK) 3440 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_INM(x, mask) \ 3441 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), mask) 3442 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUT(x, val) \ 3443 out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), val) 3444 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 3445 do {\ 3446 HWIO_INTLOCK(); \ 3447 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x)); \ 3448 HWIO_INTFREE();\ 3449 } while (0) 3450 3451 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 3452 #define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 3453 3454 //// Register TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP //// 3455 3456 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000006ec) 3457 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000006ec) 3458 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 3459 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SHFT 0 3460 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x) \ 3461 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_RMSK) 3462 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 3463 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 3464 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 3465 out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), val) 3466 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 3467 do {\ 3468 HWIO_INTLOCK(); \ 3469 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x)); \ 3470 HWIO_INTFREE();\ 3471 } while (0) 3472 3473 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3474 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3475 3476 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 3477 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 3478 3479 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3480 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3481 3482 //// Register TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS //// 3483 3484 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000006f0) 3485 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000006f0) 3486 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 3487 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_SHFT 0 3488 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_IN(x) \ 3489 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_RMSK) 3490 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 3491 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 3492 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 3493 out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), val) 3494 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 3495 do {\ 3496 HWIO_INTLOCK(); \ 3497 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_IN(x)); \ 3498 HWIO_INTFREE();\ 3499 } while (0) 3500 3501 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3502 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3503 3504 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 3505 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 3506 3507 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3508 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3509 3510 //// Register TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER //// 3511 3512 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000006f4) 3513 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000006f4) 3514 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 3515 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_SHFT 0 3516 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x) \ 3517 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK) 3518 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 3519 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 3520 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 3521 out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 3522 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 3523 do {\ 3524 HWIO_INTLOCK(); \ 3525 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 3526 HWIO_INTFREE();\ 3527 } while (0) 3528 3529 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 3530 #define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 3531 3532 //// Register TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET //// 3533 3534 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000071c) 3535 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000071c) 3536 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3537 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_SHFT 0 3538 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x) \ 3539 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK) 3540 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3541 in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3542 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3543 out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3544 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3545 do {\ 3546 HWIO_INTLOCK(); \ 3547 out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x)); \ 3548 HWIO_INTFREE();\ 3549 } while (0) 3550 3551 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3552 #define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3553 3554 //// Register TCL_R0_TCL_STATUS1_RING_BASE_LSB //// 3555 3556 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x) (x+0x00000720) 3557 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_PHYS(x) (x+0x00000720) 3558 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RMSK 0xffffffff 3559 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_SHFT 0 3560 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x) \ 3561 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RMSK) 3562 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_INM(x, mask) \ 3563 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), mask) 3564 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUT(x, val) \ 3565 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), val) 3566 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUTM(x, mask, val) \ 3567 do {\ 3568 HWIO_INTLOCK(); \ 3569 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x)); \ 3570 HWIO_INTFREE();\ 3571 } while (0) 3572 3573 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3574 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3575 3576 //// Register TCL_R0_TCL_STATUS1_RING_BASE_MSB //// 3577 3578 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x) (x+0x00000724) 3579 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_PHYS(x) (x+0x00000724) 3580 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RMSK 0x00ffffff 3581 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_SHFT 0 3582 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x) \ 3583 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RMSK) 3584 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_INM(x, mask) \ 3585 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), mask) 3586 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUT(x, val) \ 3587 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), val) 3588 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUTM(x, mask, val) \ 3589 do {\ 3590 HWIO_INTLOCK(); \ 3591 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x)); \ 3592 HWIO_INTFREE();\ 3593 } while (0) 3594 3595 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 3596 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3597 3598 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3599 #define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3600 3601 //// Register TCL_R0_TCL_STATUS1_RING_ID //// 3602 3603 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x) (x+0x00000728) 3604 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_PHYS(x) (x+0x00000728) 3605 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RMSK 0x0000ffff 3606 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_SHFT 0 3607 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x) \ 3608 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_ID_RMSK) 3609 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_INM(x, mask) \ 3610 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), mask) 3611 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUT(x, val) \ 3612 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), val) 3613 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUTM(x, mask, val) \ 3614 do {\ 3615 HWIO_INTLOCK(); \ 3616 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x)); \ 3617 HWIO_INTFREE();\ 3618 } while (0) 3619 3620 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_BMSK 0x0000ff00 3621 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_SHFT 0x8 3622 3623 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3624 #define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_SHFT 0x0 3625 3626 //// Register TCL_R0_TCL_STATUS1_RING_STATUS //// 3627 3628 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x) (x+0x0000072c) 3629 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_PHYS(x) (x+0x0000072c) 3630 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_RMSK 0xffffffff 3631 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_SHFT 0 3632 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x) \ 3633 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_RMSK) 3634 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_INM(x, mask) \ 3635 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), mask) 3636 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_OUT(x, val) \ 3637 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), val) 3638 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_OUTM(x, mask, val) \ 3639 do {\ 3640 HWIO_INTLOCK(); \ 3641 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x)); \ 3642 HWIO_INTFREE();\ 3643 } while (0) 3644 3645 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 3646 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 3647 3648 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 3649 #define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 3650 3651 //// Register TCL_R0_TCL_STATUS1_RING_MISC //// 3652 3653 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x) (x+0x00000730) 3654 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_PHYS(x) (x+0x00000730) 3655 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RMSK 0x03ffffff 3656 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SHFT 0 3657 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x) \ 3658 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RMSK) 3659 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_INM(x, mask) \ 3660 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), mask) 3661 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUT(x, val) \ 3662 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), val) 3663 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUTM(x, mask, val) \ 3664 do {\ 3665 HWIO_INTLOCK(); \ 3666 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x)); \ 3667 HWIO_INTFREE();\ 3668 } while (0) 3669 3670 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOP_CNT_BMSK 0x03c00000 3671 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOP_CNT_SHFT 0x16 3672 3673 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 3674 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SPARE_CONTROL_SHFT 0xe 3675 3676 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 3677 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 3678 3679 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 3680 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 3681 3682 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 3683 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 3684 3685 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 3686 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_ENABLE_SHFT 0x6 3687 3688 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 3689 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 3690 3691 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 3692 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 3693 3694 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 3695 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 3696 3697 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 3698 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_SHFT 0x2 3699 3700 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 3701 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 3702 3703 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 3704 #define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 3705 3706 //// Register TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB //// 3707 3708 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000734) 3709 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000734) 3710 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_RMSK 0xffffffff 3711 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_SHFT 0 3712 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x) \ 3713 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_RMSK) 3714 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_INM(x, mask) \ 3715 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), mask) 3716 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUT(x, val) \ 3717 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), val) 3718 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 3719 do {\ 3720 HWIO_INTLOCK(); \ 3721 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x)); \ 3722 HWIO_INTFREE();\ 3723 } while (0) 3724 3725 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 3726 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 3727 3728 //// Register TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB //// 3729 3730 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000738) 3731 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000738) 3732 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_RMSK 0x000000ff 3733 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_SHFT 0 3734 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x) \ 3735 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_RMSK) 3736 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_INM(x, mask) \ 3737 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), mask) 3738 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUT(x, val) \ 3739 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), val) 3740 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 3741 do {\ 3742 HWIO_INTLOCK(); \ 3743 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x)); \ 3744 HWIO_INTFREE();\ 3745 } while (0) 3746 3747 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 3748 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 3749 3750 //// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP //// 3751 3752 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000744) 3753 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000744) 3754 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 3755 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SHFT 0 3756 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x) \ 3757 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_RMSK) 3758 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 3759 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 3760 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 3761 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), val) 3762 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 3763 do {\ 3764 HWIO_INTLOCK(); \ 3765 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x)); \ 3766 HWIO_INTFREE();\ 3767 } while (0) 3768 3769 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 3770 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 3771 3772 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 3773 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 3774 3775 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 3776 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 3777 3778 //// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS //// 3779 3780 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000748) 3781 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000748) 3782 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 3783 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_SHFT 0 3784 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x) \ 3785 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_RMSK) 3786 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 3787 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 3788 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 3789 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), val) 3790 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 3791 do {\ 3792 HWIO_INTLOCK(); \ 3793 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x)); \ 3794 HWIO_INTFREE();\ 3795 } while (0) 3796 3797 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 3798 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 3799 3800 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 3801 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 3802 3803 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 3804 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 3805 3806 //// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER //// 3807 3808 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x0000074c) 3809 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x0000074c) 3810 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 3811 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_SHFT 0 3812 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x) \ 3813 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK) 3814 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 3815 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 3816 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 3817 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 3818 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 3819 do {\ 3820 HWIO_INTLOCK(); \ 3821 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 3822 HWIO_INTFREE();\ 3823 } while (0) 3824 3825 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 3826 #define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 3827 3828 //// Register TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB //// 3829 3830 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000768) 3831 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000768) 3832 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_RMSK 0xffffffff 3833 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_SHFT 0 3834 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x) \ 3835 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_RMSK) 3836 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_INM(x, mask) \ 3837 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), mask) 3838 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUT(x, val) \ 3839 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), val) 3840 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 3841 do {\ 3842 HWIO_INTLOCK(); \ 3843 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x)); \ 3844 HWIO_INTFREE();\ 3845 } while (0) 3846 3847 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 3848 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 3849 3850 //// Register TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB //// 3851 3852 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x0000076c) 3853 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x0000076c) 3854 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_RMSK 0x000001ff 3855 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_SHFT 0 3856 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x) \ 3857 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_RMSK) 3858 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_INM(x, mask) \ 3859 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), mask) 3860 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUT(x, val) \ 3861 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), val) 3862 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 3863 do {\ 3864 HWIO_INTLOCK(); \ 3865 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x)); \ 3866 HWIO_INTFREE();\ 3867 } while (0) 3868 3869 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 3870 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 3871 3872 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 3873 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 3874 3875 //// Register TCL_R0_TCL_STATUS1_RING_MSI1_DATA //// 3876 3877 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x) (x+0x00000770) 3878 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_PHYS(x) (x+0x00000770) 3879 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_RMSK 0xffffffff 3880 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_SHFT 0 3881 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x) \ 3882 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_RMSK) 3883 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_INM(x, mask) \ 3884 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), mask) 3885 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUT(x, val) \ 3886 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), val) 3887 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUTM(x, mask, val) \ 3888 do {\ 3889 HWIO_INTLOCK(); \ 3890 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x)); \ 3891 HWIO_INTFREE();\ 3892 } while (0) 3893 3894 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 3895 #define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_SHFT 0x0 3896 3897 //// Register TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET //// 3898 3899 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000774) 3900 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000774) 3901 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 3902 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_SHFT 0 3903 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x) \ 3904 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK) 3905 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 3906 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 3907 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 3908 out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), val) 3909 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 3910 do {\ 3911 HWIO_INTLOCK(); \ 3912 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x)); \ 3913 HWIO_INTFREE();\ 3914 } while (0) 3915 3916 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 3917 #define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 3918 3919 //// Register TCL_R0_TCL_STATUS2_RING_BASE_LSB //// 3920 3921 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x) (x+0x00000778) 3922 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_PHYS(x) (x+0x00000778) 3923 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RMSK 0xffffffff 3924 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_SHFT 0 3925 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_IN(x) \ 3926 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RMSK) 3927 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_INM(x, mask) \ 3928 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), mask) 3929 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_OUT(x, val) \ 3930 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), val) 3931 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_OUTM(x, mask, val) \ 3932 do {\ 3933 HWIO_INTLOCK(); \ 3934 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_IN(x)); \ 3935 HWIO_INTFREE();\ 3936 } while (0) 3937 3938 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 3939 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 3940 3941 //// Register TCL_R0_TCL_STATUS2_RING_BASE_MSB //// 3942 3943 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x) (x+0x0000077c) 3944 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_PHYS(x) (x+0x0000077c) 3945 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RMSK 0x00ffffff 3946 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_SHFT 0 3947 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_IN(x) \ 3948 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RMSK) 3949 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_INM(x, mask) \ 3950 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), mask) 3951 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_OUT(x, val) \ 3952 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), val) 3953 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_OUTM(x, mask, val) \ 3954 do {\ 3955 HWIO_INTLOCK(); \ 3956 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_IN(x)); \ 3957 HWIO_INTFREE();\ 3958 } while (0) 3959 3960 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 3961 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 3962 3963 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 3964 #define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 3965 3966 //// Register TCL_R0_TCL_STATUS2_RING_ID //// 3967 3968 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x) (x+0x00000780) 3969 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_PHYS(x) (x+0x00000780) 3970 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RMSK 0x0000ffff 3971 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_SHFT 0 3972 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_IN(x) \ 3973 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_ID_RMSK) 3974 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_INM(x, mask) \ 3975 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), mask) 3976 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_OUT(x, val) \ 3977 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), val) 3978 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_OUTM(x, mask, val) \ 3979 do {\ 3980 HWIO_INTLOCK(); \ 3981 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_ID_IN(x)); \ 3982 HWIO_INTFREE();\ 3983 } while (0) 3984 3985 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RING_ID_BMSK 0x0000ff00 3986 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RING_ID_SHFT 0x8 3987 3988 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 3989 #define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ENTRY_SIZE_SHFT 0x0 3990 3991 //// Register TCL_R0_TCL_STATUS2_RING_STATUS //// 3992 3993 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x) (x+0x00000784) 3994 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_PHYS(x) (x+0x00000784) 3995 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_RMSK 0xffffffff 3996 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_SHFT 0 3997 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_IN(x) \ 3998 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_RMSK) 3999 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_INM(x, mask) \ 4000 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), mask) 4001 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_OUT(x, val) \ 4002 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), val) 4003 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_OUTM(x, mask, val) \ 4004 do {\ 4005 HWIO_INTLOCK(); \ 4006 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_IN(x)); \ 4007 HWIO_INTFREE();\ 4008 } while (0) 4009 4010 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 4011 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 4012 4013 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 4014 #define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 4015 4016 //// Register TCL_R0_TCL_STATUS2_RING_MISC //// 4017 4018 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x) (x+0x00000788) 4019 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_PHYS(x) (x+0x00000788) 4020 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RMSK 0x03ffffff 4021 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SHFT 0 4022 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_IN(x) \ 4023 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RMSK) 4024 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_INM(x, mask) \ 4025 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), mask) 4026 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_OUT(x, val) \ 4027 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), val) 4028 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_OUTM(x, mask, val) \ 4029 do {\ 4030 HWIO_INTLOCK(); \ 4031 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MISC_IN(x)); \ 4032 HWIO_INTFREE();\ 4033 } while (0) 4034 4035 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOP_CNT_BMSK 0x03c00000 4036 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOP_CNT_SHFT 0x16 4037 4038 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 4039 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SPARE_CONTROL_SHFT 0xe 4040 4041 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 4042 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 4043 4044 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 4045 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 4046 4047 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 4048 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 4049 4050 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 4051 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_ENABLE_SHFT 0x6 4052 4053 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 4054 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 4055 4056 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 4057 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 4058 4059 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 4060 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 4061 4062 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 4063 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SECURITY_BIT_SHFT 0x2 4064 4065 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 4066 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 4067 4068 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 4069 #define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 4070 4071 //// Register TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB //// 4072 4073 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x) (x+0x0000078c) 4074 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_PHYS(x) (x+0x0000078c) 4075 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_RMSK 0xffffffff 4076 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_SHFT 0 4077 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_IN(x) \ 4078 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_RMSK) 4079 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_INM(x, mask) \ 4080 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), mask) 4081 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_OUT(x, val) \ 4082 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), val) 4083 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4084 do {\ 4085 HWIO_INTLOCK(); \ 4086 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_IN(x)); \ 4087 HWIO_INTFREE();\ 4088 } while (0) 4089 4090 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4091 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4092 4093 //// Register TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB //// 4094 4095 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000790) 4096 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000790) 4097 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_RMSK 0x000000ff 4098 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_SHFT 0 4099 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_IN(x) \ 4100 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_RMSK) 4101 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_INM(x, mask) \ 4102 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), mask) 4103 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_OUT(x, val) \ 4104 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), val) 4105 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4106 do {\ 4107 HWIO_INTLOCK(); \ 4108 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_IN(x)); \ 4109 HWIO_INTFREE();\ 4110 } while (0) 4111 4112 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4113 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4114 4115 //// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP //// 4116 4117 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x0000079c) 4118 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x0000079c) 4119 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4120 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SHFT 0 4121 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_IN(x) \ 4122 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_RMSK) 4123 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4124 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4125 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4126 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4127 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4128 do {\ 4129 HWIO_INTLOCK(); \ 4130 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_IN(x)); \ 4131 HWIO_INTFREE();\ 4132 } while (0) 4133 4134 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4135 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4136 4137 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4138 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4139 4140 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4141 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4142 4143 //// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS //// 4144 4145 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000007a0) 4146 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000007a0) 4147 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4148 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_SHFT 0 4149 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_IN(x) \ 4150 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_RMSK) 4151 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4152 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4153 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4154 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4155 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4156 do {\ 4157 HWIO_INTLOCK(); \ 4158 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_IN(x)); \ 4159 HWIO_INTFREE();\ 4160 } while (0) 4161 4162 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4163 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4164 4165 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4166 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4167 4168 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4169 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4170 4171 //// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER //// 4172 4173 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000007a4) 4174 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000007a4) 4175 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4176 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_SHFT 0 4177 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4178 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK) 4179 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4180 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4181 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4182 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4183 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4184 do {\ 4185 HWIO_INTLOCK(); \ 4186 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4187 HWIO_INTFREE();\ 4188 } while (0) 4189 4190 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4191 #define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4192 4193 //// Register TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB //// 4194 4195 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000007c0) 4196 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000007c0) 4197 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_RMSK 0xffffffff 4198 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_SHFT 0 4199 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_IN(x) \ 4200 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_RMSK) 4201 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_INM(x, mask) \ 4202 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), mask) 4203 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_OUT(x, val) \ 4204 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), val) 4205 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 4206 do {\ 4207 HWIO_INTLOCK(); \ 4208 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_IN(x)); \ 4209 HWIO_INTFREE();\ 4210 } while (0) 4211 4212 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 4213 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 4214 4215 //// Register TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB //// 4216 4217 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000007c4) 4218 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000007c4) 4219 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_RMSK 0x000001ff 4220 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_SHFT 0 4221 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_IN(x) \ 4222 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_RMSK) 4223 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_INM(x, mask) \ 4224 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), mask) 4225 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_OUT(x, val) \ 4226 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), val) 4227 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 4228 do {\ 4229 HWIO_INTLOCK(); \ 4230 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_IN(x)); \ 4231 HWIO_INTFREE();\ 4232 } while (0) 4233 4234 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 4235 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 4236 4237 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 4238 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 4239 4240 //// Register TCL_R0_TCL_STATUS2_RING_MSI1_DATA //// 4241 4242 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x) (x+0x000007c8) 4243 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_PHYS(x) (x+0x000007c8) 4244 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_RMSK 0xffffffff 4245 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_SHFT 0 4246 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_IN(x) \ 4247 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_RMSK) 4248 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_INM(x, mask) \ 4249 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), mask) 4250 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_OUT(x, val) \ 4251 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), val) 4252 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_OUTM(x, mask, val) \ 4253 do {\ 4254 HWIO_INTLOCK(); \ 4255 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_IN(x)); \ 4256 HWIO_INTFREE();\ 4257 } while (0) 4258 4259 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 4260 #define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_VALUE_SHFT 0x0 4261 4262 //// Register TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET //// 4263 4264 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000007cc) 4265 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000007cc) 4266 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4267 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_SHFT 0 4268 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_IN(x) \ 4269 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK) 4270 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4271 in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4272 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4273 out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4274 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4275 do {\ 4276 HWIO_INTLOCK(); \ 4277 out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_IN(x)); \ 4278 HWIO_INTFREE();\ 4279 } while (0) 4280 4281 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4282 #define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4283 4284 //// Register TCL_R0_TCL2FW_RING_BASE_LSB //// 4285 4286 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x) (x+0x000007d0) 4287 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_PHYS(x) (x+0x000007d0) 4288 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RMSK 0xffffffff 4289 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_SHFT 0 4290 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x) \ 4291 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RMSK) 4292 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_INM(x, mask) \ 4293 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), mask) 4294 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUT(x, val) \ 4295 out_dword( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), val) 4296 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUTM(x, mask, val) \ 4297 do {\ 4298 HWIO_INTLOCK(); \ 4299 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x)); \ 4300 HWIO_INTFREE();\ 4301 } while (0) 4302 4303 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 4304 #define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 4305 4306 //// Register TCL_R0_TCL2FW_RING_BASE_MSB //// 4307 4308 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x) (x+0x000007d4) 4309 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_PHYS(x) (x+0x000007d4) 4310 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RMSK 0x00ffffff 4311 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_SHFT 0 4312 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x) \ 4313 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RMSK) 4314 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_INM(x, mask) \ 4315 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), mask) 4316 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUT(x, val) \ 4317 out_dword( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), val) 4318 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUTM(x, mask, val) \ 4319 do {\ 4320 HWIO_INTLOCK(); \ 4321 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x)); \ 4322 HWIO_INTFREE();\ 4323 } while (0) 4324 4325 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 4326 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_SHFT 0x8 4327 4328 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 4329 #define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 4330 4331 //// Register TCL_R0_TCL2FW_RING_ID //// 4332 4333 #define HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x) (x+0x000007d8) 4334 #define HWIO_TCL_R0_TCL2FW_RING_ID_PHYS(x) (x+0x000007d8) 4335 #define HWIO_TCL_R0_TCL2FW_RING_ID_RMSK 0x0000ffff 4336 #define HWIO_TCL_R0_TCL2FW_RING_ID_SHFT 0 4337 #define HWIO_TCL_R0_TCL2FW_RING_ID_IN(x) \ 4338 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_ID_RMSK) 4339 #define HWIO_TCL_R0_TCL2FW_RING_ID_INM(x, mask) \ 4340 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), mask) 4341 #define HWIO_TCL_R0_TCL2FW_RING_ID_OUT(x, val) \ 4342 out_dword( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), val) 4343 #define HWIO_TCL_R0_TCL2FW_RING_ID_OUTM(x, mask, val) \ 4344 do {\ 4345 HWIO_INTLOCK(); \ 4346 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_ID_IN(x)); \ 4347 HWIO_INTFREE();\ 4348 } while (0) 4349 4350 #define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_BMSK 0x0000ff00 4351 #define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_SHFT 0x8 4352 4353 #define HWIO_TCL_R0_TCL2FW_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 4354 #define HWIO_TCL_R0_TCL2FW_RING_ID_ENTRY_SIZE_SHFT 0x0 4355 4356 //// Register TCL_R0_TCL2FW_RING_STATUS //// 4357 4358 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x) (x+0x000007dc) 4359 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_PHYS(x) (x+0x000007dc) 4360 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_RMSK 0xffffffff 4361 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_SHFT 0 4362 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_IN(x) \ 4363 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_STATUS_RMSK) 4364 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_INM(x, mask) \ 4365 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), mask) 4366 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_OUT(x, val) \ 4367 out_dword( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), val) 4368 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_OUTM(x, mask, val) \ 4369 do {\ 4370 HWIO_INTLOCK(); \ 4371 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_STATUS_IN(x)); \ 4372 HWIO_INTFREE();\ 4373 } while (0) 4374 4375 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 4376 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 4377 4378 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 4379 #define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 4380 4381 //// Register TCL_R0_TCL2FW_RING_MISC //// 4382 4383 #define HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x) (x+0x000007e0) 4384 #define HWIO_TCL_R0_TCL2FW_RING_MISC_PHYS(x) (x+0x000007e0) 4385 #define HWIO_TCL_R0_TCL2FW_RING_MISC_RMSK 0x03ffffff 4386 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SHFT 0 4387 #define HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x) \ 4388 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_MISC_RMSK) 4389 #define HWIO_TCL_R0_TCL2FW_RING_MISC_INM(x, mask) \ 4390 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), mask) 4391 #define HWIO_TCL_R0_TCL2FW_RING_MISC_OUT(x, val) \ 4392 out_dword( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), val) 4393 #define HWIO_TCL_R0_TCL2FW_RING_MISC_OUTM(x, mask, val) \ 4394 do {\ 4395 HWIO_INTLOCK(); \ 4396 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x)); \ 4397 HWIO_INTFREE();\ 4398 } while (0) 4399 4400 #define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOP_CNT_BMSK 0x03c00000 4401 #define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOP_CNT_SHFT 0x16 4402 4403 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 4404 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SPARE_CONTROL_SHFT 0xe 4405 4406 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 4407 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 4408 4409 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 4410 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 4411 4412 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 4413 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 4414 4415 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 4416 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_ENABLE_SHFT 0x6 4417 4418 #define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 4419 #define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 4420 4421 #define HWIO_TCL_R0_TCL2FW_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 4422 #define HWIO_TCL_R0_TCL2FW_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 4423 4424 #define HWIO_TCL_R0_TCL2FW_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 4425 #define HWIO_TCL_R0_TCL2FW_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 4426 4427 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SECURITY_BIT_BMSK 0x00000004 4428 #define HWIO_TCL_R0_TCL2FW_RING_MISC_SECURITY_BIT_SHFT 0x2 4429 4430 #define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 4431 #define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 4432 4433 #define HWIO_TCL_R0_TCL2FW_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 4434 #define HWIO_TCL_R0_TCL2FW_RING_MISC_RING_ID_DISABLE_SHFT 0x0 4435 4436 //// Register TCL_R0_TCL2FW_RING_HP_ADDR_LSB //// 4437 4438 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x) (x+0x000007e4) 4439 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_PHYS(x) (x+0x000007e4) 4440 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_RMSK 0xffffffff 4441 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_SHFT 0 4442 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x) \ 4443 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_RMSK) 4444 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_INM(x, mask) \ 4445 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), mask) 4446 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUT(x, val) \ 4447 out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), val) 4448 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 4449 do {\ 4450 HWIO_INTLOCK(); \ 4451 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x)); \ 4452 HWIO_INTFREE();\ 4453 } while (0) 4454 4455 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 4456 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 4457 4458 //// Register TCL_R0_TCL2FW_RING_HP_ADDR_MSB //// 4459 4460 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x) (x+0x000007e8) 4461 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_PHYS(x) (x+0x000007e8) 4462 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_RMSK 0x000000ff 4463 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_SHFT 0 4464 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x) \ 4465 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_RMSK) 4466 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_INM(x, mask) \ 4467 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), mask) 4468 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUT(x, val) \ 4469 out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), val) 4470 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 4471 do {\ 4472 HWIO_INTLOCK(); \ 4473 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x)); \ 4474 HWIO_INTFREE();\ 4475 } while (0) 4476 4477 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 4478 #define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 4479 4480 //// Register TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP //// 4481 4482 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000007f4) 4483 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000007f4) 4484 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 4485 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SHFT 0 4486 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x) \ 4487 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_RMSK) 4488 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 4489 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 4490 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 4491 out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), val) 4492 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 4493 do {\ 4494 HWIO_INTLOCK(); \ 4495 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x)); \ 4496 HWIO_INTFREE();\ 4497 } while (0) 4498 4499 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 4500 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 4501 4502 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 4503 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 4504 4505 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 4506 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 4507 4508 //// Register TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS //// 4509 4510 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000007f8) 4511 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000007f8) 4512 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 4513 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_SHFT 0 4514 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_IN(x) \ 4515 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_RMSK) 4516 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 4517 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 4518 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 4519 out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), val) 4520 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 4521 do {\ 4522 HWIO_INTLOCK(); \ 4523 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_IN(x)); \ 4524 HWIO_INTFREE();\ 4525 } while (0) 4526 4527 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 4528 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 4529 4530 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 4531 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 4532 4533 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 4534 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 4535 4536 //// Register TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER //// 4537 4538 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000007fc) 4539 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000007fc) 4540 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 4541 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_SHFT 0 4542 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x) \ 4543 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK) 4544 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 4545 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 4546 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 4547 out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 4548 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 4549 do {\ 4550 HWIO_INTLOCK(); \ 4551 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 4552 HWIO_INTFREE();\ 4553 } while (0) 4554 4555 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 4556 #define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 4557 4558 //// Register TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET //// 4559 4560 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000824) 4561 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000824) 4562 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 4563 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_SHFT 0 4564 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x) \ 4565 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK) 4566 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 4567 in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 4568 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 4569 out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), val) 4570 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 4571 do {\ 4572 HWIO_INTLOCK(); \ 4573 out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x)); \ 4574 HWIO_INTFREE();\ 4575 } while (0) 4576 4577 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 4578 #define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 4579 4580 //// Register TCL_R0_GXI_TESTBUS_LOWER //// 4581 4582 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x) (x+0x00000828) 4583 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_PHYS(x) (x+0x00000828) 4584 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_RMSK 0xffffffff 4585 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_SHFT 0 4586 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_IN(x) \ 4587 in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_TCL_R0_GXI_TESTBUS_LOWER_RMSK) 4588 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_INM(x, mask) \ 4589 in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) 4590 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_OUT(x, val) \ 4591 out_dword( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), val) 4592 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val) \ 4593 do {\ 4594 HWIO_INTLOCK(); \ 4595 out_dword_masked_ns(HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_TCL_R0_GXI_TESTBUS_LOWER_IN(x)); \ 4596 HWIO_INTFREE();\ 4597 } while (0) 4598 4599 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_VALUE_BMSK 0xffffffff 4600 #define HWIO_TCL_R0_GXI_TESTBUS_LOWER_VALUE_SHFT 0x0 4601 4602 //// Register TCL_R0_GXI_TESTBUS_UPPER //// 4603 4604 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x) (x+0x0000082c) 4605 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_PHYS(x) (x+0x0000082c) 4606 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_RMSK 0x000000ff 4607 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_SHFT 0 4608 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_IN(x) \ 4609 in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_TCL_R0_GXI_TESTBUS_UPPER_RMSK) 4610 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_INM(x, mask) \ 4611 in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) 4612 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_OUT(x, val) \ 4613 out_dword( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), val) 4614 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val) \ 4615 do {\ 4616 HWIO_INTLOCK(); \ 4617 out_dword_masked_ns(HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_TCL_R0_GXI_TESTBUS_UPPER_IN(x)); \ 4618 HWIO_INTFREE();\ 4619 } while (0) 4620 4621 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_VALUE_BMSK 0x000000ff 4622 #define HWIO_TCL_R0_GXI_TESTBUS_UPPER_VALUE_SHFT 0x0 4623 4624 //// Register TCL_R0_GXI_SM_STATES_IX_0 //// 4625 4626 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x) (x+0x00000830) 4627 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_PHYS(x) (x+0x00000830) 4628 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_RMSK 0x00000fff 4629 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SHFT 0 4630 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_IN(x) \ 4631 in_dword_masked ( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_TCL_R0_GXI_SM_STATES_IX_0_RMSK) 4632 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_INM(x, mask) \ 4633 in_dword_masked ( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) 4634 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_OUT(x, val) \ 4635 out_dword( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), val) 4636 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val) \ 4637 do {\ 4638 HWIO_INTLOCK(); \ 4639 out_dword_masked_ns(HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_TCL_R0_GXI_SM_STATES_IX_0_IN(x)); \ 4640 HWIO_INTFREE();\ 4641 } while (0) 4642 4643 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00 4644 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 4645 4646 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0 4647 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4 4648 4649 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f 4650 #define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0 4651 4652 //// Register TCL_R0_GXI_END_OF_TEST_CHECK //// 4653 4654 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x) (x+0x00000834) 4655 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_PHYS(x) (x+0x00000834) 4656 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_RMSK 0x00000001 4657 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_SHFT 0 4658 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_IN(x) \ 4659 in_dword_masked ( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_RMSK) 4660 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_INM(x, mask) \ 4661 in_dword_masked ( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) 4662 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_OUT(x, val) \ 4663 out_dword( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val) 4664 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 4665 do {\ 4666 HWIO_INTLOCK(); \ 4667 out_dword_masked_ns(HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_IN(x)); \ 4668 HWIO_INTFREE();\ 4669 } while (0) 4670 4671 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 4672 #define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 4673 4674 //// Register TCL_R0_GXI_CLOCK_GATE_DISABLE //// 4675 4676 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x) (x+0x00000838) 4677 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x) (x+0x00000838) 4678 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RMSK 0x80000fff 4679 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_SHFT 0 4680 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_IN(x) \ 4681 in_dword_masked ( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RMSK) 4682 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask) \ 4683 in_dword_masked ( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) 4684 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val) \ 4685 out_dword( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val) 4686 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ 4687 do {\ 4688 HWIO_INTLOCK(); \ 4689 out_dword_masked_ns(HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \ 4690 HWIO_INTFREE();\ 4691 } while (0) 4692 4693 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 4694 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f 4695 4696 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_SPARE_BMSK 0x00000800 4697 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_SPARE_SHFT 0xb 4698 4699 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_BMSK 0x00000400 4700 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_SHFT 0xa 4701 4702 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_BMSK 0x00000200 4703 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_SHFT 0x9 4704 4705 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_BMSK 0x00000100 4706 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_SHFT 0x8 4707 4708 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_BMSK 0x00000080 4709 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_SHFT 0x7 4710 4711 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_BMSK 0x00000040 4712 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_SHFT 0x6 4713 4714 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_BMSK 0x00000020 4715 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_SHFT 0x5 4716 4717 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_BMSK 0x00000010 4718 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_SHFT 0x4 4719 4720 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_BMSK 0x00000008 4721 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_SHFT 0x3 4722 4723 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_BMSK 0x00000004 4724 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_SHFT 0x2 4725 4726 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_BMSK 0x00000002 4727 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_SHFT 0x1 4728 4729 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CORE_BMSK 0x00000001 4730 #define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CORE_SHFT 0x0 4731 4732 //// Register TCL_R0_GXI_GXI_ERR_INTS //// 4733 4734 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x) (x+0x0000083c) 4735 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_PHYS(x) (x+0x0000083c) 4736 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_RMSK 0x01010101 4737 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_SHFT 0 4738 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_IN(x) \ 4739 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_TCL_R0_GXI_GXI_ERR_INTS_RMSK) 4740 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_INM(x, mask) \ 4741 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) 4742 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_OUT(x, val) \ 4743 out_dword( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), val) 4744 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val) \ 4745 do {\ 4746 HWIO_INTLOCK(); \ 4747 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_ERR_INTS_IN(x)); \ 4748 HWIO_INTFREE();\ 4749 } while (0) 4750 4751 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000 4752 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 4753 4754 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000 4755 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10 4756 4757 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100 4758 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8 4759 4760 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001 4761 #define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0 4762 4763 //// Register TCL_R0_GXI_GXI_ERR_STATS //// 4764 4765 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x) (x+0x00000840) 4766 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_PHYS(x) (x+0x00000840) 4767 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_RMSK 0x003f3f3f 4768 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_SHFT 0 4769 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_IN(x) \ 4770 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_TCL_R0_GXI_GXI_ERR_STATS_RMSK) 4771 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_INM(x, mask) \ 4772 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) 4773 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_OUT(x, val) \ 4774 out_dword( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), val) 4775 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val) \ 4776 do {\ 4777 HWIO_INTLOCK(); \ 4778 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_ERR_STATS_IN(x)); \ 4779 HWIO_INTFREE();\ 4780 } while (0) 4781 4782 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000 4783 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 4784 4785 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00 4786 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8 4787 4788 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f 4789 #define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0 4790 4791 //// Register TCL_R0_GXI_GXI_DEFAULT_CONTROL //// 4792 4793 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x00000844) 4794 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x00000844) 4795 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f 4796 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_SHFT 0 4797 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_IN(x) \ 4798 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_RMSK) 4799 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask) \ 4800 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) 4801 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val) \ 4802 out_dword( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val) 4803 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ 4804 do {\ 4805 HWIO_INTLOCK(); \ 4806 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \ 4807 HWIO_INTFREE();\ 4808 } while (0) 4809 4810 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 4811 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 4812 4813 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 4814 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10 4815 4816 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00 4817 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8 4818 4819 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f 4820 #define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0 4821 4822 //// Register TCL_R0_GXI_GXI_REDUCED_CONTROL //// 4823 4824 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x) (x+0x00000848) 4825 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x) (x+0x00000848) 4826 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f 4827 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_SHFT 0 4828 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_IN(x) \ 4829 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_RMSK) 4830 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask) \ 4831 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) 4832 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val) \ 4833 out_dword( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val) 4834 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ 4835 do {\ 4836 HWIO_INTLOCK(); \ 4837 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \ 4838 HWIO_INTFREE();\ 4839 } while (0) 4840 4841 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 4842 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 4843 4844 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 4845 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10 4846 4847 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00 4848 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8 4849 4850 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f 4851 #define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0 4852 4853 //// Register TCL_R0_GXI_GXI_MISC_CONTROL //// 4854 4855 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x) (x+0x0000084c) 4856 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_PHYS(x) (x+0x0000084c) 4857 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_RMSK 0x0fffffff 4858 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_SHFT 0 4859 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_IN(x) \ 4860 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_RMSK) 4861 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_INM(x, mask) \ 4862 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) 4863 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_OUT(x, val) \ 4864 out_dword( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val) 4865 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val) \ 4866 do {\ 4867 HWIO_INTLOCK(); \ 4868 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_IN(x)); \ 4869 HWIO_INTFREE();\ 4870 } while (0) 4871 4872 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_BMSK 0x08000000 4873 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_SHFT 0x1b 4874 4875 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_BMSK 0x04000000 4876 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_SHFT 0x1a 4877 4878 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_BMSK 0x02000000 4879 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_SHFT 0x19 4880 4881 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_BMSK 0x01000000 4882 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_SHFT 0x18 4883 4884 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_BMSK 0x00800000 4885 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_SHFT 0x17 4886 4887 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000 4888 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 4889 4890 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000 4891 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11 4892 4893 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00 4894 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9 4895 4896 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe 4897 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1 4898 4899 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001 4900 #define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0 4901 4902 //// Register TCL_R0_GXI_GXI_WDOG_CONTROL //// 4903 4904 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x) (x+0x00000850) 4905 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_PHYS(x) (x+0x00000850) 4906 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_RMSK 0xffff0001 4907 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_SHFT 0 4908 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_IN(x) \ 4909 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_RMSK) 4910 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask) \ 4911 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) 4912 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val) \ 4913 out_dword( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val) 4914 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ 4915 do {\ 4916 HWIO_INTLOCK(); \ 4917 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \ 4918 HWIO_INTFREE();\ 4919 } while (0) 4920 4921 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 4922 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 4923 4924 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001 4925 #define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0 4926 4927 //// Register TCL_R0_GXI_GXI_WDOG_STATUS //// 4928 4929 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x) (x+0x00000854) 4930 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_PHYS(x) (x+0x00000854) 4931 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_RMSK 0x0000ffff 4932 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_SHFT 0 4933 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_IN(x) \ 4934 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_RMSK) 4935 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_INM(x, mask) \ 4936 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) 4937 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_OUT(x, val) \ 4938 out_dword( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val) 4939 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val) \ 4940 do {\ 4941 HWIO_INTLOCK(); \ 4942 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_IN(x)); \ 4943 HWIO_INTFREE();\ 4944 } while (0) 4945 4946 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff 4947 #define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 4948 4949 //// Register TCL_R0_GXI_GXI_IDLE_COUNTERS //// 4950 4951 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x) (x+0x00000858) 4952 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x) (x+0x00000858) 4953 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_RMSK 0xffffffff 4954 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_SHFT 0 4955 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_IN(x) \ 4956 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_RMSK) 4957 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask) \ 4958 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) 4959 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val) \ 4960 out_dword( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val) 4961 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ 4962 do {\ 4963 HWIO_INTLOCK(); \ 4964 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \ 4965 HWIO_INTFREE();\ 4966 } while (0) 4967 4968 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 4969 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 4970 4971 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff 4972 #define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0 4973 4974 //// Register TCL_R0_GXI_GXI_RD_LATENCY_CTRL //// 4975 4976 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x) (x+0x0000085c) 4977 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_PHYS(x) (x+0x0000085c) 4978 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_RMSK 0x000fffff 4979 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_SHFT 0 4980 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_IN(x) \ 4981 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_RMSK) 4982 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_INM(x, mask) \ 4983 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), mask) 4984 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_OUT(x, val) \ 4985 out_dword( HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), val) 4986 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_OUTM(x, mask, val) \ 4987 do {\ 4988 HWIO_INTLOCK(); \ 4989 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_IN(x)); \ 4990 HWIO_INTFREE();\ 4991 } while (0) 4992 4993 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0x000e0000 4994 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11 4995 4996 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x00010000 4997 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10 4998 4999 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0x0000ffff 5000 #define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0 5001 5002 //// Register TCL_R0_GXI_GXI_WR_LATENCY_CTRL //// 5003 5004 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x) (x+0x00000860) 5005 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_PHYS(x) (x+0x00000860) 5006 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_RMSK 0x000fffff 5007 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_SHFT 0 5008 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_IN(x) \ 5009 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_RMSK) 5010 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_INM(x, mask) \ 5011 in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), mask) 5012 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_OUT(x, val) \ 5013 out_dword( HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), val) 5014 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_OUTM(x, mask, val) \ 5015 do {\ 5016 HWIO_INTLOCK(); \ 5017 out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_IN(x)); \ 5018 HWIO_INTFREE();\ 5019 } while (0) 5020 5021 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0x000e0000 5022 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11 5023 5024 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x00010000 5025 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10 5026 5027 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0x0000ffff 5028 #define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0 5029 5030 //// Register TCL_R0_ASE_GST_BASE_ADDR_LOW //// 5031 5032 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x) (x+0x00000864) 5033 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_PHYS(x) (x+0x00000864) 5034 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_RMSK 0xffffffff 5035 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_SHFT 0 5036 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x) \ 5037 in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_RMSK) 5038 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_INM(x, mask) \ 5039 in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), mask) 5040 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUT(x, val) \ 5041 out_dword( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), val) 5042 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUTM(x, mask, val) \ 5043 do {\ 5044 HWIO_INTLOCK(); \ 5045 out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x)); \ 5046 HWIO_INTFREE();\ 5047 } while (0) 5048 5049 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_BMSK 0xffffffff 5050 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_SHFT 0x0 5051 5052 //// Register TCL_R0_ASE_GST_BASE_ADDR_HIGH //// 5053 5054 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x) (x+0x00000868) 5055 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_PHYS(x) (x+0x00000868) 5056 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_RMSK 0x000000ff 5057 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_SHFT 0 5058 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x) \ 5059 in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_RMSK) 5060 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_INM(x, mask) \ 5061 in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), mask) 5062 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUT(x, val) \ 5063 out_dword( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), val) 5064 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUTM(x, mask, val) \ 5065 do {\ 5066 HWIO_INTLOCK(); \ 5067 out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x)); \ 5068 HWIO_INTFREE();\ 5069 } while (0) 5070 5071 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_BMSK 0x000000ff 5072 #define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_SHFT 0x0 5073 5074 //// Register TCL_R0_ASE_GST_SIZE //// 5075 5076 #define HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x) (x+0x0000086c) 5077 #define HWIO_TCL_R0_ASE_GST_SIZE_PHYS(x) (x+0x0000086c) 5078 #define HWIO_TCL_R0_ASE_GST_SIZE_RMSK 0x000fffff 5079 #define HWIO_TCL_R0_ASE_GST_SIZE_SHFT 0 5080 #define HWIO_TCL_R0_ASE_GST_SIZE_IN(x) \ 5081 in_dword_masked ( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), HWIO_TCL_R0_ASE_GST_SIZE_RMSK) 5082 #define HWIO_TCL_R0_ASE_GST_SIZE_INM(x, mask) \ 5083 in_dword_masked ( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), mask) 5084 #define HWIO_TCL_R0_ASE_GST_SIZE_OUT(x, val) \ 5085 out_dword( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), val) 5086 #define HWIO_TCL_R0_ASE_GST_SIZE_OUTM(x, mask, val) \ 5087 do {\ 5088 HWIO_INTLOCK(); \ 5089 out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_SIZE_IN(x)); \ 5090 HWIO_INTFREE();\ 5091 } while (0) 5092 5093 #define HWIO_TCL_R0_ASE_GST_SIZE_VAL_BMSK 0x000fffff 5094 #define HWIO_TCL_R0_ASE_GST_SIZE_VAL_SHFT 0x0 5095 5096 //// Register TCL_R0_ASE_SEARCH_CTRL //// 5097 5098 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x) (x+0x00000870) 5099 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_PHYS(x) (x+0x00000870) 5100 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_RMSK 0xffff07ff 5101 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_SHFT 0 5102 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x) \ 5103 in_dword_masked ( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), HWIO_TCL_R0_ASE_SEARCH_CTRL_RMSK) 5104 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_INM(x, mask) \ 5105 in_dword_masked ( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), mask) 5106 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUT(x, val) \ 5107 out_dword( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), val) 5108 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUTM(x, mask, val) \ 5109 do {\ 5110 HWIO_INTLOCK(); \ 5111 out_dword_masked_ns(HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x)); \ 5112 HWIO_INTFREE();\ 5113 } while (0) 5114 5115 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_BMSK 0xffff0000 5116 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_SHFT 0x10 5117 5118 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_FAILURES_ENABLE_BMSK 0x00000400 5119 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_FAILURES_ENABLE_SHFT 0xa 5120 5121 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_DISABLE_BMSK 0x00000200 5122 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_DISABLE_SHFT 0x9 5123 5124 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_SEARCH_SWAP_BMSK 0x00000100 5125 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_SEARCH_SWAP_SHFT 0x8 5126 5127 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_MAX_SEARCH_BMSK 0x000000ff 5128 #define HWIO_TCL_R0_ASE_SEARCH_CTRL_MAX_SEARCH_SHFT 0x0 5129 5130 //// Register TCL_R0_ASE_WATCHDOG //// 5131 5132 #define HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x) (x+0x00000874) 5133 #define HWIO_TCL_R0_ASE_WATCHDOG_PHYS(x) (x+0x00000874) 5134 #define HWIO_TCL_R0_ASE_WATCHDOG_RMSK 0xffffffff 5135 #define HWIO_TCL_R0_ASE_WATCHDOG_SHFT 0 5136 #define HWIO_TCL_R0_ASE_WATCHDOG_IN(x) \ 5137 in_dword_masked ( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), HWIO_TCL_R0_ASE_WATCHDOG_RMSK) 5138 #define HWIO_TCL_R0_ASE_WATCHDOG_INM(x, mask) \ 5139 in_dword_masked ( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), mask) 5140 #define HWIO_TCL_R0_ASE_WATCHDOG_OUT(x, val) \ 5141 out_dword( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), val) 5142 #define HWIO_TCL_R0_ASE_WATCHDOG_OUTM(x, mask, val) \ 5143 do {\ 5144 HWIO_INTLOCK(); \ 5145 out_dword_masked_ns(HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_ASE_WATCHDOG_IN(x)); \ 5146 HWIO_INTFREE();\ 5147 } while (0) 5148 5149 #define HWIO_TCL_R0_ASE_WATCHDOG_STATUS_BMSK 0xffff0000 5150 #define HWIO_TCL_R0_ASE_WATCHDOG_STATUS_SHFT 0x10 5151 5152 #define HWIO_TCL_R0_ASE_WATCHDOG_LIMIT_BMSK 0x0000ffff 5153 #define HWIO_TCL_R0_ASE_WATCHDOG_LIMIT_SHFT 0x0 5154 5155 //// Register TCL_R0_ASE_CLKGATE_DISABLE //// 5156 5157 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x) (x+0x00000878) 5158 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PHYS(x) (x+0x00000878) 5159 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_RMSK 0xffffffff 5160 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SHFT 0 5161 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x) \ 5162 in_dword_masked ( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_ASE_CLKGATE_DISABLE_RMSK) 5163 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_INM(x, mask) \ 5164 in_dword_masked ( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), mask) 5165 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUT(x, val) \ 5166 out_dword( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), val) 5167 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUTM(x, mask, val) \ 5168 do {\ 5169 HWIO_INTLOCK(); \ 5170 out_dword_masked_ns(HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x)); \ 5171 HWIO_INTFREE();\ 5172 } while (0) 5173 5174 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CLK_EXTEND_BMSK 0x80000000 5175 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CLK_EXTEND_SHFT 0x1f 5176 5177 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CPU_IF_EXTEND_BMSK 0x40000000 5178 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CPU_IF_EXTEND_SHFT 0x1e 5179 5180 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_RSRVD_BMSK 0x3ffff800 5181 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_RSRVD_SHFT 0xb 5182 5183 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_TOP_BMSK 0x00000400 5184 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_TOP_SHFT 0xa 5185 5186 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CACHE_BMSK 0x00000200 5187 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CACHE_SHFT 0x9 5188 5189 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SLOTS_ARRAY_HASH_BMSK 0x00000100 5190 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SLOTS_ARRAY_HASH_SHFT 0x8 5191 5192 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_APP_RETURN_BMSK 0x00000080 5193 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_APP_RETURN_SHFT 0x7 5194 5195 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PEER_RESP_BMSK 0x00000040 5196 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PEER_RESP_SHFT 0x6 5197 5198 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PEER_ISS_BMSK 0x00000020 5199 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PEER_ISS_SHFT 0x5 5200 5201 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP2_BMSK 0x00000010 5202 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP2_SHFT 0x4 5203 5204 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP1_BMSK 0x00000008 5205 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP1_SHFT 0x3 5206 5207 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS2_BMSK 0x00000004 5208 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS2_SHFT 0x2 5209 5210 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS1_BMSK 0x00000002 5211 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS1_SHFT 0x1 5212 5213 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_CTL_BMSK 0x00000001 5214 #define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_CTL_SHFT 0x0 5215 5216 //// Register TCL_R0_ASE_WRITE_BACK_PENDING //// 5217 5218 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x) (x+0x0000087c) 5219 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_PHYS(x) (x+0x0000087c) 5220 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_RMSK 0x00000001 5221 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_SHFT 0 5222 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_IN(x) \ 5223 in_dword_masked ( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_RMSK) 5224 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_INM(x, mask) \ 5225 in_dword_masked ( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), mask) 5226 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_OUT(x, val) \ 5227 out_dword( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), val) 5228 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_OUTM(x, mask, val) \ 5229 do {\ 5230 HWIO_INTLOCK(); \ 5231 out_dword_masked_ns(HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), mask, val, HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_IN(x)); \ 5232 HWIO_INTFREE();\ 5233 } while (0) 5234 5235 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_BMSK 0x00000001 5236 #define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_SHFT 0x0 5237 5238 //// Register TCL_R0_FSE_GST_BASE_ADDR_LOW //// 5239 5240 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x) (x+0x00000880) 5241 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_PHYS(x) (x+0x00000880) 5242 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_RMSK 0xffffffff 5243 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_SHFT 0 5244 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_IN(x) \ 5245 in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_RMSK) 5246 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_INM(x, mask) \ 5247 in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), mask) 5248 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_OUT(x, val) \ 5249 out_dword( HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), val) 5250 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_OUTM(x, mask, val) \ 5251 do {\ 5252 HWIO_INTLOCK(); \ 5253 out_dword_masked_ns(HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), mask, val, HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_IN(x)); \ 5254 HWIO_INTFREE();\ 5255 } while (0) 5256 5257 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_VAL_BMSK 0xffffffff 5258 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_VAL_SHFT 0x0 5259 5260 //// Register TCL_R0_FSE_GST_BASE_ADDR_HIGH //// 5261 5262 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x) (x+0x00000884) 5263 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_PHYS(x) (x+0x00000884) 5264 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_RMSK 0x000000ff 5265 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_SHFT 0 5266 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_IN(x) \ 5267 in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_RMSK) 5268 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_INM(x, mask) \ 5269 in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), mask) 5270 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_OUT(x, val) \ 5271 out_dword( HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), val) 5272 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_OUTM(x, mask, val) \ 5273 do {\ 5274 HWIO_INTLOCK(); \ 5275 out_dword_masked_ns(HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_IN(x)); \ 5276 HWIO_INTFREE();\ 5277 } while (0) 5278 5279 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_VAL_BMSK 0x000000ff 5280 #define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_VAL_SHFT 0x0 5281 5282 //// Register TCL_R0_FSE_GST_SIZE //// 5283 5284 #define HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x) (x+0x00000888) 5285 #define HWIO_TCL_R0_FSE_GST_SIZE_PHYS(x) (x+0x00000888) 5286 #define HWIO_TCL_R0_FSE_GST_SIZE_RMSK 0x000fffff 5287 #define HWIO_TCL_R0_FSE_GST_SIZE_SHFT 0 5288 #define HWIO_TCL_R0_FSE_GST_SIZE_IN(x) \ 5289 in_dword_masked ( HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), HWIO_TCL_R0_FSE_GST_SIZE_RMSK) 5290 #define HWIO_TCL_R0_FSE_GST_SIZE_INM(x, mask) \ 5291 in_dword_masked ( HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), mask) 5292 #define HWIO_TCL_R0_FSE_GST_SIZE_OUT(x, val) \ 5293 out_dword( HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), val) 5294 #define HWIO_TCL_R0_FSE_GST_SIZE_OUTM(x, mask, val) \ 5295 do {\ 5296 HWIO_INTLOCK(); \ 5297 out_dword_masked_ns(HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), mask, val, HWIO_TCL_R0_FSE_GST_SIZE_IN(x)); \ 5298 HWIO_INTFREE();\ 5299 } while (0) 5300 5301 #define HWIO_TCL_R0_FSE_GST_SIZE_VAL_BMSK 0x000fffff 5302 #define HWIO_TCL_R0_FSE_GST_SIZE_VAL_SHFT 0x0 5303 5304 //// Register TCL_R0_FSE_SEARCH_CTRL //// 5305 5306 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x) (x+0x0000088c) 5307 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_PHYS(x) (x+0x0000088c) 5308 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_RMSK 0xffff07ff 5309 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_SHFT 0 5310 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_IN(x) \ 5311 in_dword_masked ( HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), HWIO_TCL_R0_FSE_SEARCH_CTRL_RMSK) 5312 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_INM(x, mask) \ 5313 in_dword_masked ( HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), mask) 5314 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_OUT(x, val) \ 5315 out_dword( HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), val) 5316 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_OUTM(x, mask, val) \ 5317 do {\ 5318 HWIO_INTLOCK(); \ 5319 out_dword_masked_ns(HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_FSE_SEARCH_CTRL_IN(x)); \ 5320 HWIO_INTFREE();\ 5321 } while (0) 5322 5323 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_TIMEOUT_THRESH_BMSK 0xffff0000 5324 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_TIMEOUT_THRESH_SHFT 0x10 5325 5326 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_CACHE_FAILURES_ENABLE_BMSK 0x00000400 5327 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_CACHE_FAILURES_ENABLE_SHFT 0xa 5328 5329 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_CACHE_DISABLE_BMSK 0x00000200 5330 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_CACHE_DISABLE_SHFT 0x9 5331 5332 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_SEARCH_SWAP_BMSK 0x00000100 5333 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_SEARCH_SWAP_SHFT 0x8 5334 5335 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_MAX_SEARCH_BMSK 0x000000ff 5336 #define HWIO_TCL_R0_FSE_SEARCH_CTRL_MAX_SEARCH_SHFT 0x0 5337 5338 //// Register TCL_R0_FSE_WATCHDOG //// 5339 5340 #define HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x) (x+0x00000890) 5341 #define HWIO_TCL_R0_FSE_WATCHDOG_PHYS(x) (x+0x00000890) 5342 #define HWIO_TCL_R0_FSE_WATCHDOG_RMSK 0xffffffff 5343 #define HWIO_TCL_R0_FSE_WATCHDOG_SHFT 0 5344 #define HWIO_TCL_R0_FSE_WATCHDOG_IN(x) \ 5345 in_dword_masked ( HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), HWIO_TCL_R0_FSE_WATCHDOG_RMSK) 5346 #define HWIO_TCL_R0_FSE_WATCHDOG_INM(x, mask) \ 5347 in_dword_masked ( HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), mask) 5348 #define HWIO_TCL_R0_FSE_WATCHDOG_OUT(x, val) \ 5349 out_dword( HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), val) 5350 #define HWIO_TCL_R0_FSE_WATCHDOG_OUTM(x, mask, val) \ 5351 do {\ 5352 HWIO_INTLOCK(); \ 5353 out_dword_masked_ns(HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_FSE_WATCHDOG_IN(x)); \ 5354 HWIO_INTFREE();\ 5355 } while (0) 5356 5357 #define HWIO_TCL_R0_FSE_WATCHDOG_STATUS_BMSK 0xffff0000 5358 #define HWIO_TCL_R0_FSE_WATCHDOG_STATUS_SHFT 0x10 5359 5360 #define HWIO_TCL_R0_FSE_WATCHDOG_LIMIT_BMSK 0x0000ffff 5361 #define HWIO_TCL_R0_FSE_WATCHDOG_LIMIT_SHFT 0x0 5362 5363 //// Register TCL_R0_FSE_CLKGATE_DISABLE //// 5364 5365 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x) (x+0x00000894) 5366 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_PHYS(x) (x+0x00000894) 5367 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_RMSK 0xffffffff 5368 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_SHFT 0 5369 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_IN(x) \ 5370 in_dword_masked ( HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_FSE_CLKGATE_DISABLE_RMSK) 5371 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_INM(x, mask) \ 5372 in_dword_masked ( HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), mask) 5373 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_OUT(x, val) \ 5374 out_dword( HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), val) 5375 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_OUTM(x, mask, val) \ 5376 do {\ 5377 HWIO_INTLOCK(); \ 5378 out_dword_masked_ns(HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_FSE_CLKGATE_DISABLE_IN(x)); \ 5379 HWIO_INTFREE();\ 5380 } while (0) 5381 5382 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_CLK_EXTEND_BMSK 0x80000000 5383 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_CLK_EXTEND_SHFT 0x1f 5384 5385 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_CPU_IF_EXTEND_BMSK 0x40000000 5386 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_CPU_IF_EXTEND_SHFT 0x1e 5387 5388 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_GSE_RSRVD_BMSK 0x3ffff800 5389 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_GSE_RSRVD_SHFT 0xb 5390 5391 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_GSE_TOP_BMSK 0x00000400 5392 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_GSE_TOP_SHFT 0xa 5393 5394 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_CACHE_BMSK 0x00000200 5395 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_CACHE_SHFT 0x9 5396 5397 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_SLOTS_ARRAY_HASH_BMSK 0x00000100 5398 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_SLOTS_ARRAY_HASH_SHFT 0x8 5399 5400 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_APP_RETURN_BMSK 0x00000080 5401 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_APP_RETURN_SHFT 0x7 5402 5403 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_PEER_RESP_BMSK 0x00000040 5404 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_PEER_RESP_SHFT 0x6 5405 5406 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_PEER_ISS_BMSK 0x00000020 5407 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_PEER_ISS_SHFT 0x5 5408 5409 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_MEM_RESP2_BMSK 0x00000010 5410 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_MEM_RESP2_SHFT 0x4 5411 5412 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_MEM_RESP1_BMSK 0x00000008 5413 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_MEM_RESP1_SHFT 0x3 5414 5415 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_MEM_ISS2_BMSK 0x00000004 5416 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_MEM_ISS2_SHFT 0x2 5417 5418 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_MEM_ISS1_BMSK 0x00000002 5419 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_MEM_ISS1_SHFT 0x1 5420 5421 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_GSE_CTL_BMSK 0x00000001 5422 #define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_GSE_CTL_SHFT 0x0 5423 5424 //// Register TCL_R0_FSE_WRITE_BACK_PENDING //// 5425 5426 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x) (x+0x00000898) 5427 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_PHYS(x) (x+0x00000898) 5428 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_RMSK 0x00000001 5429 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_SHFT 0 5430 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_IN(x) \ 5431 in_dword_masked ( HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_RMSK) 5432 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_INM(x, mask) \ 5433 in_dword_masked ( HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), mask) 5434 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_OUT(x, val) \ 5435 out_dword( HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), val) 5436 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_OUTM(x, mask, val) \ 5437 do {\ 5438 HWIO_INTLOCK(); \ 5439 out_dword_masked_ns(HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), mask, val, HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_IN(x)); \ 5440 HWIO_INTFREE();\ 5441 } while (0) 5442 5443 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_STATUS_BMSK 0x00000001 5444 #define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_STATUS_SHFT 0x0 5445 5446 //// Register TCL_R1_SM_STATES_IX_0 //// 5447 5448 #define HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x) (x+0x00001000) 5449 #define HWIO_TCL_R1_SM_STATES_IX_0_PHYS(x) (x+0x00001000) 5450 #define HWIO_TCL_R1_SM_STATES_IX_0_RMSK 0x07ffffff 5451 #define HWIO_TCL_R1_SM_STATES_IX_0_SHFT 0 5452 #define HWIO_TCL_R1_SM_STATES_IX_0_IN(x) \ 5453 in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), HWIO_TCL_R1_SM_STATES_IX_0_RMSK) 5454 #define HWIO_TCL_R1_SM_STATES_IX_0_INM(x, mask) \ 5455 in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), mask) 5456 #define HWIO_TCL_R1_SM_STATES_IX_0_OUT(x, val) \ 5457 out_dword( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), val) 5458 #define HWIO_TCL_R1_SM_STATES_IX_0_OUTM(x, mask, val) \ 5459 do {\ 5460 HWIO_INTLOCK(); \ 5461 out_dword_masked_ns(HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_TCL_R1_SM_STATES_IX_0_IN(x)); \ 5462 HWIO_INTFREE();\ 5463 } while (0) 5464 5465 #define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_BMSK 0x07000000 5466 #define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_SHFT 0x18 5467 5468 #define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_BMSK 0x00e00000 5469 #define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_SHFT 0x15 5470 5471 #define HWIO_TCL_R1_SM_STATES_IX_0_EXTN_DESC_FETCH_BMSK 0x001c0000 5472 #define HWIO_TCL_R1_SM_STATES_IX_0_EXTN_DESC_FETCH_SHFT 0x12 5473 5474 #define HWIO_TCL_R1_SM_STATES_IX_0_MSDU_FETCH_BMSK 0x00038000 5475 #define HWIO_TCL_R1_SM_STATES_IX_0_MSDU_FETCH_SHFT 0xf 5476 5477 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL_CMD_RING_BMSK 0x00007000 5478 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL_CMD_RING_SHFT 0xc 5479 5480 #define HWIO_TCL_R1_SM_STATES_IX_0_FW2TCL1_RING_BMSK 0x00000e00 5481 #define HWIO_TCL_R1_SM_STATES_IX_0_FW2TCL1_RING_SHFT 0x9 5482 5483 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL3_RING_BMSK 0x000001c0 5484 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL3_RING_SHFT 0x6 5485 5486 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL2_RING_BMSK 0x00000038 5487 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL2_RING_SHFT 0x3 5488 5489 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL1_RING_BMSK 0x00000007 5490 #define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL1_RING_SHFT 0x0 5491 5492 //// Register TCL_R1_SM_STATES_IX_1 //// 5493 5494 #define HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x) (x+0x00001004) 5495 #define HWIO_TCL_R1_SM_STATES_IX_1_PHYS(x) (x+0x00001004) 5496 #define HWIO_TCL_R1_SM_STATES_IX_1_RMSK 0x0003ffff 5497 #define HWIO_TCL_R1_SM_STATES_IX_1_SHFT 0 5498 #define HWIO_TCL_R1_SM_STATES_IX_1_IN(x) \ 5499 in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), HWIO_TCL_R1_SM_STATES_IX_1_RMSK) 5500 #define HWIO_TCL_R1_SM_STATES_IX_1_INM(x, mask) \ 5501 in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), mask) 5502 #define HWIO_TCL_R1_SM_STATES_IX_1_OUT(x, val) \ 5503 out_dword( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), val) 5504 #define HWIO_TCL_R1_SM_STATES_IX_1_OUTM(x, mask, val) \ 5505 do {\ 5506 HWIO_INTLOCK(); \ 5507 out_dword_masked_ns(HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_TCL_R1_SM_STATES_IX_1_IN(x)); \ 5508 HWIO_INTFREE();\ 5509 } while (0) 5510 5511 #define HWIO_TCL_R1_SM_STATES_IX_1_DSCP_TABLE_ACC_BMSK 0x00038000 5512 #define HWIO_TCL_R1_SM_STATES_IX_1_DSCP_TABLE_ACC_SHFT 0xf 5513 5514 #define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_BMSK 0x00007000 5515 #define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_SHFT 0xc 5516 5517 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS2_BMSK 0x00000e00 5518 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS2_SHFT 0x9 5519 5520 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS1_BMSK 0x000001c0 5521 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS1_SHFT 0x6 5522 5523 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL2FW_BMSK 0x00000038 5524 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL2FW_SHFT 0x3 5525 5526 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_BMSK 0x00000007 5527 #define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_SHFT 0x0 5528 5529 //// Register TCL_R1_TESTBUS_CTRL_0 //// 5530 5531 #define HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x) (x+0x00001008) 5532 #define HWIO_TCL_R1_TESTBUS_CTRL_0_PHYS(x) (x+0x00001008) 5533 #define HWIO_TCL_R1_TESTBUS_CTRL_0_RMSK 0x3fffffff 5534 #define HWIO_TCL_R1_TESTBUS_CTRL_0_SHFT 0 5535 #define HWIO_TCL_R1_TESTBUS_CTRL_0_IN(x) \ 5536 in_dword_masked ( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), HWIO_TCL_R1_TESTBUS_CTRL_0_RMSK) 5537 #define HWIO_TCL_R1_TESTBUS_CTRL_0_INM(x, mask) \ 5538 in_dword_masked ( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), mask) 5539 #define HWIO_TCL_R1_TESTBUS_CTRL_0_OUT(x, val) \ 5540 out_dword( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), val) 5541 #define HWIO_TCL_R1_TESTBUS_CTRL_0_OUTM(x, mask, val) \ 5542 do {\ 5543 HWIO_INTLOCK(); \ 5544 out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_CTRL_0_IN(x)); \ 5545 HWIO_INTFREE();\ 5546 } while (0) 5547 5548 #define HWIO_TCL_R1_TESTBUS_CTRL_0_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK 0x20000000 5549 #define HWIO_TCL_R1_TESTBUS_CTRL_0_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT 0x1d 5550 5551 #define HWIO_TCL_R1_TESTBUS_CTRL_0_TCL_MAIN_SELECT_BMSK 0x1f800000 5552 #define HWIO_TCL_R1_TESTBUS_CTRL_0_TCL_MAIN_SELECT_SHFT 0x17 5553 5554 #define HWIO_TCL_R1_TESTBUS_CTRL_0_GXI_SELECT_BMSK 0x007c0000 5555 #define HWIO_TCL_R1_TESTBUS_CTRL_0_GXI_SELECT_SHFT 0x12 5556 5557 #define HWIO_TCL_R1_TESTBUS_CTRL_0_FSE_SELECT_BMSK 0x0003c000 5558 #define HWIO_TCL_R1_TESTBUS_CTRL_0_FSE_SELECT_SHFT 0xe 5559 5560 #define HWIO_TCL_R1_TESTBUS_CTRL_0_ASE_SELECT_BMSK 0x00003c00 5561 #define HWIO_TCL_R1_TESTBUS_CTRL_0_ASE_SELECT_SHFT 0xa 5562 5563 #define HWIO_TCL_R1_TESTBUS_CTRL_0_PARSER_SELECT_BMSK 0x000003e0 5564 #define HWIO_TCL_R1_TESTBUS_CTRL_0_PARSER_SELECT_SHFT 0x5 5565 5566 #define HWIO_TCL_R1_TESTBUS_CTRL_0_CCE_SELECT_BMSK 0x0000001f 5567 #define HWIO_TCL_R1_TESTBUS_CTRL_0_CCE_SELECT_SHFT 0x0 5568 5569 //// Register TCL_R1_TESTBUS_LOW //// 5570 5571 #define HWIO_TCL_R1_TESTBUS_LOW_ADDR(x) (x+0x0000100c) 5572 #define HWIO_TCL_R1_TESTBUS_LOW_PHYS(x) (x+0x0000100c) 5573 #define HWIO_TCL_R1_TESTBUS_LOW_RMSK 0xffffffff 5574 #define HWIO_TCL_R1_TESTBUS_LOW_SHFT 0 5575 #define HWIO_TCL_R1_TESTBUS_LOW_IN(x) \ 5576 in_dword_masked ( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), HWIO_TCL_R1_TESTBUS_LOW_RMSK) 5577 #define HWIO_TCL_R1_TESTBUS_LOW_INM(x, mask) \ 5578 in_dword_masked ( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), mask) 5579 #define HWIO_TCL_R1_TESTBUS_LOW_OUT(x, val) \ 5580 out_dword( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), val) 5581 #define HWIO_TCL_R1_TESTBUS_LOW_OUTM(x, mask, val) \ 5582 do {\ 5583 HWIO_INTLOCK(); \ 5584 out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_LOW_IN(x)); \ 5585 HWIO_INTFREE();\ 5586 } while (0) 5587 5588 #define HWIO_TCL_R1_TESTBUS_LOW_VAL_BMSK 0xffffffff 5589 #define HWIO_TCL_R1_TESTBUS_LOW_VAL_SHFT 0x0 5590 5591 //// Register TCL_R1_TESTBUS_HIGH //// 5592 5593 #define HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x) (x+0x00001010) 5594 #define HWIO_TCL_R1_TESTBUS_HIGH_PHYS(x) (x+0x00001010) 5595 #define HWIO_TCL_R1_TESTBUS_HIGH_RMSK 0x000000ff 5596 #define HWIO_TCL_R1_TESTBUS_HIGH_SHFT 0 5597 #define HWIO_TCL_R1_TESTBUS_HIGH_IN(x) \ 5598 in_dword_masked ( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), HWIO_TCL_R1_TESTBUS_HIGH_RMSK) 5599 #define HWIO_TCL_R1_TESTBUS_HIGH_INM(x, mask) \ 5600 in_dword_masked ( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), mask) 5601 #define HWIO_TCL_R1_TESTBUS_HIGH_OUT(x, val) \ 5602 out_dword( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), val) 5603 #define HWIO_TCL_R1_TESTBUS_HIGH_OUTM(x, mask, val) \ 5604 do {\ 5605 HWIO_INTLOCK(); \ 5606 out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_HIGH_IN(x)); \ 5607 HWIO_INTFREE();\ 5608 } while (0) 5609 5610 #define HWIO_TCL_R1_TESTBUS_HIGH_VAL_BMSK 0x000000ff 5611 #define HWIO_TCL_R1_TESTBUS_HIGH_VAL_SHFT 0x0 5612 5613 //// Register TCL_R1_EVENTMASK_IX_0 //// 5614 5615 #define HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x) (x+0x00001014) 5616 #define HWIO_TCL_R1_EVENTMASK_IX_0_PHYS(x) (x+0x00001014) 5617 #define HWIO_TCL_R1_EVENTMASK_IX_0_RMSK 0xffffffff 5618 #define HWIO_TCL_R1_EVENTMASK_IX_0_SHFT 0 5619 #define HWIO_TCL_R1_EVENTMASK_IX_0_IN(x) \ 5620 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_0_RMSK) 5621 #define HWIO_TCL_R1_EVENTMASK_IX_0_INM(x, mask) \ 5622 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), mask) 5623 #define HWIO_TCL_R1_EVENTMASK_IX_0_OUT(x, val) \ 5624 out_dword( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), val) 5625 #define HWIO_TCL_R1_EVENTMASK_IX_0_OUTM(x, mask, val) \ 5626 do {\ 5627 HWIO_INTLOCK(); \ 5628 out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_0_IN(x)); \ 5629 HWIO_INTFREE();\ 5630 } while (0) 5631 5632 #define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_BMSK 0xffffffff 5633 #define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_SHFT 0x0 5634 5635 //// Register TCL_R1_EVENTMASK_IX_1 //// 5636 5637 #define HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x) (x+0x00001018) 5638 #define HWIO_TCL_R1_EVENTMASK_IX_1_PHYS(x) (x+0x00001018) 5639 #define HWIO_TCL_R1_EVENTMASK_IX_1_RMSK 0xffffffff 5640 #define HWIO_TCL_R1_EVENTMASK_IX_1_SHFT 0 5641 #define HWIO_TCL_R1_EVENTMASK_IX_1_IN(x) \ 5642 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_1_RMSK) 5643 #define HWIO_TCL_R1_EVENTMASK_IX_1_INM(x, mask) \ 5644 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), mask) 5645 #define HWIO_TCL_R1_EVENTMASK_IX_1_OUT(x, val) \ 5646 out_dword( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), val) 5647 #define HWIO_TCL_R1_EVENTMASK_IX_1_OUTM(x, mask, val) \ 5648 do {\ 5649 HWIO_INTLOCK(); \ 5650 out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_1_IN(x)); \ 5651 HWIO_INTFREE();\ 5652 } while (0) 5653 5654 #define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_BMSK 0xffffffff 5655 #define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_SHFT 0x0 5656 5657 //// Register TCL_R1_EVENTMASK_IX_2 //// 5658 5659 #define HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x) (x+0x0000101c) 5660 #define HWIO_TCL_R1_EVENTMASK_IX_2_PHYS(x) (x+0x0000101c) 5661 #define HWIO_TCL_R1_EVENTMASK_IX_2_RMSK 0xffffffff 5662 #define HWIO_TCL_R1_EVENTMASK_IX_2_SHFT 0 5663 #define HWIO_TCL_R1_EVENTMASK_IX_2_IN(x) \ 5664 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_2_RMSK) 5665 #define HWIO_TCL_R1_EVENTMASK_IX_2_INM(x, mask) \ 5666 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), mask) 5667 #define HWIO_TCL_R1_EVENTMASK_IX_2_OUT(x, val) \ 5668 out_dword( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), val) 5669 #define HWIO_TCL_R1_EVENTMASK_IX_2_OUTM(x, mask, val) \ 5670 do {\ 5671 HWIO_INTLOCK(); \ 5672 out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_2_IN(x)); \ 5673 HWIO_INTFREE();\ 5674 } while (0) 5675 5676 #define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_BMSK 0xffffffff 5677 #define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_SHFT 0x0 5678 5679 //// Register TCL_R1_EVENTMASK_IX_3 //// 5680 5681 #define HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x) (x+0x00001020) 5682 #define HWIO_TCL_R1_EVENTMASK_IX_3_PHYS(x) (x+0x00001020) 5683 #define HWIO_TCL_R1_EVENTMASK_IX_3_RMSK 0xffffffff 5684 #define HWIO_TCL_R1_EVENTMASK_IX_3_SHFT 0 5685 #define HWIO_TCL_R1_EVENTMASK_IX_3_IN(x) \ 5686 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_3_RMSK) 5687 #define HWIO_TCL_R1_EVENTMASK_IX_3_INM(x, mask) \ 5688 in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), mask) 5689 #define HWIO_TCL_R1_EVENTMASK_IX_3_OUT(x, val) \ 5690 out_dword( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), val) 5691 #define HWIO_TCL_R1_EVENTMASK_IX_3_OUTM(x, mask, val) \ 5692 do {\ 5693 HWIO_INTLOCK(); \ 5694 out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_3_IN(x)); \ 5695 HWIO_INTFREE();\ 5696 } while (0) 5697 5698 #define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_BMSK 0xffffffff 5699 #define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_SHFT 0x0 5700 5701 //// Register TCL_R1_REG_ACCESS_EVENT_GEN_CTRL //// 5702 5703 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) (x+0x00001024) 5704 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) (x+0x00001024) 5705 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff 5706 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_SHFT 0 5707 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ 5708 in_dword_masked ( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK) 5709 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, mask) \ 5710 in_dword_masked ( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask) 5711 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, val) \ 5712 out_dword( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), val) 5713 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x, mask, val) \ 5714 do {\ 5715 HWIO_INTLOCK(); \ 5716 out_dword_masked_ns(HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask, val, HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)); \ 5717 HWIO_INTFREE();\ 5718 } while (0) 5719 5720 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 5721 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 0x11 5722 5723 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x0001fffc 5724 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 0x2 5725 5726 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x00000002 5727 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 0x1 5728 5729 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x00000001 5730 #define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0x0 5731 5732 //// Register TCL_R1_END_OF_TEST_CHECK //// 5733 5734 #define HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00001028) 5735 #define HWIO_TCL_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00001028) 5736 #define HWIO_TCL_R1_END_OF_TEST_CHECK_RMSK 0x00000001 5737 #define HWIO_TCL_R1_END_OF_TEST_CHECK_SHFT 0 5738 #define HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x) \ 5739 in_dword_masked ( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_END_OF_TEST_CHECK_RMSK) 5740 #define HWIO_TCL_R1_END_OF_TEST_CHECK_INM(x, mask) \ 5741 in_dword_masked ( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), mask) 5742 #define HWIO_TCL_R1_END_OF_TEST_CHECK_OUT(x, val) \ 5743 out_dword( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), val) 5744 #define HWIO_TCL_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 5745 do {\ 5746 HWIO_INTLOCK(); \ 5747 out_dword_masked_ns(HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x)); \ 5748 HWIO_INTFREE();\ 5749 } while (0) 5750 5751 #define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 5752 #define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 5753 5754 //// Register TCL_R1_ASE_END_OF_TEST_CHECK //// 5755 5756 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x) (x+0x0000102c) 5757 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_PHYS(x) (x+0x0000102c) 5758 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_RMSK 0x00000001 5759 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_SHFT 0 5760 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x) \ 5761 in_dword_masked ( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_RMSK) 5762 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_INM(x, mask) \ 5763 in_dword_masked ( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), mask) 5764 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUT(x, val) \ 5765 out_dword( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), val) 5766 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 5767 do {\ 5768 HWIO_INTLOCK(); \ 5769 out_dword_masked_ns(HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x)); \ 5770 HWIO_INTFREE();\ 5771 } while (0) 5772 5773 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 5774 #define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 5775 5776 //// Register TCL_R1_ASE_DEBUG_CLEAR_COUNTERS //// 5777 5778 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x) (x+0x00001030) 5779 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_PHYS(x) (x+0x00001030) 5780 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_RMSK 0x00000001 5781 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_SHFT 0 5782 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x) \ 5783 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_RMSK) 5784 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_INM(x, mask) \ 5785 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask) 5786 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUT(x, val) \ 5787 out_dword( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), val) 5788 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUTM(x, mask, val) \ 5789 do {\ 5790 HWIO_INTLOCK(); \ 5791 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x)); \ 5792 HWIO_INTFREE();\ 5793 } while (0) 5794 5795 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_BMSK 0x00000001 5796 #define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_SHFT 0x0 5797 5798 //// Register TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER //// 5799 5800 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x) (x+0x00001034) 5801 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_PHYS(x) (x+0x00001034) 5802 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK 0xffffffff 5803 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_SHFT 0 5804 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x) \ 5805 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK) 5806 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_INM(x, mask) \ 5807 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask) 5808 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_OUT(x, val) \ 5809 out_dword( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), val) 5810 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_OUTM(x, mask, val) \ 5811 do {\ 5812 HWIO_INTLOCK(); \ 5813 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x)); \ 5814 HWIO_INTFREE();\ 5815 } while (0) 5816 5817 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_BMSK 0xffffffff 5818 #define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_SHFT 0x0 5819 5820 //// Register TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER //// 5821 5822 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x) (x+0x00001038) 5823 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_PHYS(x) (x+0x00001038) 5824 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_RMSK 0xffffffff 5825 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_SHFT 0 5826 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_IN(x) \ 5827 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_RMSK) 5828 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_INM(x, mask) \ 5829 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask) 5830 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_OUT(x, val) \ 5831 out_dword( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), val) 5832 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_OUTM(x, mask, val) \ 5833 do {\ 5834 HWIO_INTLOCK(); \ 5835 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_IN(x)); \ 5836 HWIO_INTFREE();\ 5837 } while (0) 5838 5839 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_BMSK 0xffffffff 5840 #define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_SHFT 0x0 5841 5842 //// Register TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER //// 5843 5844 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x) (x+0x0000103c) 5845 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PHYS(x) (x+0x0000103c) 5846 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK 0x000fffff 5847 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_SHFT 0 5848 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x) \ 5849 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK) 5850 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_INM(x, mask) \ 5851 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask) 5852 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUT(x, val) \ 5853 out_dword( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), val) 5854 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUTM(x, mask, val) \ 5855 do {\ 5856 HWIO_INTLOCK(); \ 5857 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x)); \ 5858 HWIO_INTFREE();\ 5859 } while (0) 5860 5861 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_BMSK 0x000ffc00 5862 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_SHFT 0xa 5863 5864 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_BMSK 0x000003ff 5865 #define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_SHFT 0x0 5866 5867 //// Register TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER //// 5868 5869 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x) (x+0x00001040) 5870 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PHYS(x) (x+0x00001040) 5871 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_RMSK 0x03ffffff 5872 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SHFT 0 5873 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_IN(x) \ 5874 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_RMSK) 5875 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_INM(x, mask) \ 5876 in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask) 5877 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_OUT(x, val) \ 5878 out_dword( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), val) 5879 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_OUTM(x, mask, val) \ 5880 do {\ 5881 HWIO_INTLOCK(); \ 5882 out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_IN(x)); \ 5883 HWIO_INTFREE();\ 5884 } while (0) 5885 5886 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_BMSK 0x03fffc00 5887 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_SHFT 0xa 5888 5889 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_BMSK 0x000003e0 5890 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_SHFT 0x5 5891 5892 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_BMSK 0x0000001f 5893 #define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_SHFT 0x0 5894 5895 //// Register TCL_R1_ASE_SM_STATES //// 5896 5897 #define HWIO_TCL_R1_ASE_SM_STATES_ADDR(x) (x+0x00001044) 5898 #define HWIO_TCL_R1_ASE_SM_STATES_PHYS(x) (x+0x00001044) 5899 #define HWIO_TCL_R1_ASE_SM_STATES_RMSK 0x003fffff 5900 #define HWIO_TCL_R1_ASE_SM_STATES_SHFT 0 5901 #define HWIO_TCL_R1_ASE_SM_STATES_IN(x) \ 5902 in_dword_masked ( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), HWIO_TCL_R1_ASE_SM_STATES_RMSK) 5903 #define HWIO_TCL_R1_ASE_SM_STATES_INM(x, mask) \ 5904 in_dword_masked ( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), mask) 5905 #define HWIO_TCL_R1_ASE_SM_STATES_OUT(x, val) \ 5906 out_dword( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), val) 5907 #define HWIO_TCL_R1_ASE_SM_STATES_OUTM(x, mask, val) \ 5908 do {\ 5909 HWIO_INTLOCK(); \ 5910 out_dword_masked_ns(HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), mask, val, HWIO_TCL_R1_ASE_SM_STATES_IN(x)); \ 5911 HWIO_INTFREE();\ 5912 } while (0) 5913 5914 #define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_BMSK 0x00300000 5915 #define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_SHFT 0x14 5916 5917 #define HWIO_TCL_R1_ASE_SM_STATES_CACHE_CHK_STATE_BMSK 0x000c0000 5918 #define HWIO_TCL_R1_ASE_SM_STATES_CACHE_CHK_STATE_SHFT 0x12 5919 5920 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS1_STATE_BMSK 0x00030000 5921 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS1_STATE_SHFT 0x10 5922 5923 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS2_STATE_BMSK 0x0000c000 5924 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS2_STATE_SHFT 0xe 5925 5926 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP1_STATE_BMSK 0x00003800 5927 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP1_STATE_SHFT 0xb 5928 5929 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP2_STATE_BMSK 0x00000700 5930 #define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP2_STATE_SHFT 0x8 5931 5932 #define HWIO_TCL_R1_ASE_SM_STATES_PEER_ISS_STATE_BMSK 0x000000c0 5933 #define HWIO_TCL_R1_ASE_SM_STATES_PEER_ISS_STATE_SHFT 0x6 5934 5935 #define HWIO_TCL_R1_ASE_SM_STATES_PEER_RESP_STATE_BMSK 0x00000030 5936 #define HWIO_TCL_R1_ASE_SM_STATES_PEER_RESP_STATE_SHFT 0x4 5937 5938 #define HWIO_TCL_R1_ASE_SM_STATES_APP_RETURN_STATE_BMSK 0x0000000f 5939 #define HWIO_TCL_R1_ASE_SM_STATES_APP_RETURN_STATE_SHFT 0x0 5940 5941 //// Register TCL_R1_ASE_CACHE_DEBUG //// 5942 5943 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x) (x+0x00001048) 5944 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_PHYS(x) (x+0x00001048) 5945 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_RMSK 0x000003ff 5946 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_SHFT 0 5947 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x) \ 5948 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), HWIO_TCL_R1_ASE_CACHE_DEBUG_RMSK) 5949 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_INM(x, mask) \ 5950 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), mask) 5951 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUT(x, val) \ 5952 out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), val) 5953 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUTM(x, mask, val) \ 5954 do {\ 5955 HWIO_INTLOCK(); \ 5956 out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x)); \ 5957 HWIO_INTFREE();\ 5958 } while (0) 5959 5960 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_BMSK 0x000003ff 5961 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_SHFT 0x0 5962 5963 //// Register TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS //// 5964 5965 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x) (x+0x0000104c) 5966 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_PHYS(x) (x+0x0000104c) 5967 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_RMSK 0x007fffff 5968 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_SHFT 0 5969 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_IN(x) \ 5970 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_RMSK) 5971 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_INM(x, mask) \ 5972 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask) 5973 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_OUT(x, val) \ 5974 out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), val) 5975 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_OUTM(x, mask, val) \ 5976 do {\ 5977 HWIO_INTLOCK(); \ 5978 out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_IN(x)); \ 5979 HWIO_INTFREE();\ 5980 } while (0) 5981 5982 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_BMSK 0x007ffff8 5983 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_SHFT 0x3 5984 5985 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_BMSK 0x00000004 5986 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_SHFT 0x2 5987 5988 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_DIRTY_BMSK 0x00000002 5989 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_DIRTY_SHFT 0x1 5990 5991 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_VALID_BMSK 0x00000001 5992 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_VALID_SHFT 0x0 5993 5994 //// Register TCL_R1_ASE_CACHE_DEBUG_ENTRY_n //// 5995 5996 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n) (base+0x1050+0x4*n) 5997 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_PHYS(base, n) (base+0x1050+0x4*n) 5998 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK 0xffffffff 5999 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_SHFT 0 6000 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_MAXn 31 6001 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INI(base, n) \ 6002 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK) 6003 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INMI(base, n, mask) \ 6004 in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask) 6005 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_OUTI(base, n, val) \ 6006 out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), val) 6007 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_OUTMI(base, n, mask, val) \ 6008 do {\ 6009 HWIO_INTLOCK(); \ 6010 out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INI(base, n)); \ 6011 HWIO_INTFREE();\ 6012 } while (0) 6013 6014 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_BMSK 0xffffffff 6015 #define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_SHFT 0x0 6016 6017 //// Register TCL_R1_FSE_END_OF_TEST_CHECK //// 6018 6019 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x) (x+0x000010d0) 6020 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_PHYS(x) (x+0x000010d0) 6021 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_RMSK 0x00000001 6022 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_SHFT 0 6023 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_IN(x) \ 6024 in_dword_masked ( HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_RMSK) 6025 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_INM(x, mask) \ 6026 in_dword_masked ( HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), mask) 6027 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_OUT(x, val) \ 6028 out_dword( HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), val) 6029 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 6030 do {\ 6031 HWIO_INTLOCK(); \ 6032 out_dword_masked_ns(HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_IN(x)); \ 6033 HWIO_INTFREE();\ 6034 } while (0) 6035 6036 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 6037 #define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 6038 6039 //// Register TCL_R1_FSE_DEBUG_CLEAR_COUNTERS //// 6040 6041 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x) (x+0x000010d4) 6042 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_PHYS(x) (x+0x000010d4) 6043 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_RMSK 0x00000001 6044 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_SHFT 0 6045 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_IN(x) \ 6046 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_RMSK) 6047 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_INM(x, mask) \ 6048 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask) 6049 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_OUT(x, val) \ 6050 out_dword( HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), val) 6051 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_OUTM(x, mask, val) \ 6052 do {\ 6053 HWIO_INTLOCK(); \ 6054 out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_IN(x)); \ 6055 HWIO_INTFREE();\ 6056 } while (0) 6057 6058 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_EN_BMSK 0x00000001 6059 #define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_EN_SHFT 0x0 6060 6061 //// Register TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER //// 6062 6063 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x) (x+0x000010d8) 6064 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_PHYS(x) (x+0x000010d8) 6065 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK 0xffffffff 6066 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_SHFT 0 6067 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x) \ 6068 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK) 6069 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_INM(x, mask) \ 6070 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask) 6071 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_OUT(x, val) \ 6072 out_dword( HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), val) 6073 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_OUTM(x, mask, val) \ 6074 do {\ 6075 HWIO_INTLOCK(); \ 6076 out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x)); \ 6077 HWIO_INTFREE();\ 6078 } while (0) 6079 6080 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_BMSK 0xffffffff 6081 #define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_SHFT 0x0 6082 6083 //// Register TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER //// 6084 6085 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x) (x+0x000010dc) 6086 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_PHYS(x) (x+0x000010dc) 6087 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_RMSK 0xffffffff 6088 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_SHFT 0 6089 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_IN(x) \ 6090 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_RMSK) 6091 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_INM(x, mask) \ 6092 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask) 6093 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_OUT(x, val) \ 6094 out_dword( HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), val) 6095 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_OUTM(x, mask, val) \ 6096 do {\ 6097 HWIO_INTLOCK(); \ 6098 out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_IN(x)); \ 6099 HWIO_INTFREE();\ 6100 } while (0) 6101 6102 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_VAL_BMSK 0xffffffff 6103 #define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_VAL_SHFT 0x0 6104 6105 //// Register TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER //// 6106 6107 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x) (x+0x000010e0) 6108 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_PHYS(x) (x+0x000010e0) 6109 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK 0x000fffff 6110 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_SHFT 0 6111 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x) \ 6112 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK) 6113 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_INM(x, mask) \ 6114 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask) 6115 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUT(x, val) \ 6116 out_dword( HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), val) 6117 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUTM(x, mask, val) \ 6118 do {\ 6119 HWIO_INTLOCK(); \ 6120 out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x)); \ 6121 HWIO_INTFREE();\ 6122 } while (0) 6123 6124 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_BMSK 0x000ffc00 6125 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_SHFT 0xa 6126 6127 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_BMSK 0x000003ff 6128 #define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_SHFT 0x0 6129 6130 //// Register TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER //// 6131 6132 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x) (x+0x000010e4) 6133 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_PHYS(x) (x+0x000010e4) 6134 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_RMSK 0x03ffffff 6135 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_SHFT 0 6136 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_IN(x) \ 6137 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_RMSK) 6138 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_INM(x, mask) \ 6139 in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask) 6140 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_OUT(x, val) \ 6141 out_dword( HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), val) 6142 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_OUTM(x, mask, val) \ 6143 do {\ 6144 HWIO_INTLOCK(); \ 6145 out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_IN(x)); \ 6146 HWIO_INTFREE();\ 6147 } while (0) 6148 6149 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_BMSK 0x03fffc00 6150 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_SHFT 0xa 6151 6152 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_BMSK 0x000003e0 6153 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_SHFT 0x5 6154 6155 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_BMSK 0x0000001f 6156 #define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_SHFT 0x0 6157 6158 //// Register TCL_R1_FSE_SM_STATES //// 6159 6160 #define HWIO_TCL_R1_FSE_SM_STATES_ADDR(x) (x+0x000010e8) 6161 #define HWIO_TCL_R1_FSE_SM_STATES_PHYS(x) (x+0x000010e8) 6162 #define HWIO_TCL_R1_FSE_SM_STATES_RMSK 0x003fffff 6163 #define HWIO_TCL_R1_FSE_SM_STATES_SHFT 0 6164 #define HWIO_TCL_R1_FSE_SM_STATES_IN(x) \ 6165 in_dword_masked ( HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), HWIO_TCL_R1_FSE_SM_STATES_RMSK) 6166 #define HWIO_TCL_R1_FSE_SM_STATES_INM(x, mask) \ 6167 in_dword_masked ( HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), mask) 6168 #define HWIO_TCL_R1_FSE_SM_STATES_OUT(x, val) \ 6169 out_dword( HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), val) 6170 #define HWIO_TCL_R1_FSE_SM_STATES_OUTM(x, mask, val) \ 6171 do {\ 6172 HWIO_INTLOCK(); \ 6173 out_dword_masked_ns(HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), mask, val, HWIO_TCL_R1_FSE_SM_STATES_IN(x)); \ 6174 HWIO_INTFREE();\ 6175 } while (0) 6176 6177 #define HWIO_TCL_R1_FSE_SM_STATES_GSE_CTRL_STATE_BMSK 0x00300000 6178 #define HWIO_TCL_R1_FSE_SM_STATES_GSE_CTRL_STATE_SHFT 0x14 6179 6180 #define HWIO_TCL_R1_FSE_SM_STATES_CACHE_CHK_STATE_BMSK 0x000c0000 6181 #define HWIO_TCL_R1_FSE_SM_STATES_CACHE_CHK_STATE_SHFT 0x12 6182 6183 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS1_STATE_BMSK 0x00030000 6184 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS1_STATE_SHFT 0x10 6185 6186 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS2_STATE_BMSK 0x0000c000 6187 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS2_STATE_SHFT 0xe 6188 6189 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP1_STATE_BMSK 0x00003800 6190 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP1_STATE_SHFT 0xb 6191 6192 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP2_STATE_BMSK 0x00000700 6193 #define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP2_STATE_SHFT 0x8 6194 6195 #define HWIO_TCL_R1_FSE_SM_STATES_PEER_ISS_STATE_BMSK 0x000000c0 6196 #define HWIO_TCL_R1_FSE_SM_STATES_PEER_ISS_STATE_SHFT 0x6 6197 6198 #define HWIO_TCL_R1_FSE_SM_STATES_PEER_RESP_STATE_BMSK 0x00000030 6199 #define HWIO_TCL_R1_FSE_SM_STATES_PEER_RESP_STATE_SHFT 0x4 6200 6201 #define HWIO_TCL_R1_FSE_SM_STATES_APP_RETURN_STATE_BMSK 0x0000000f 6202 #define HWIO_TCL_R1_FSE_SM_STATES_APP_RETURN_STATE_SHFT 0x0 6203 6204 //// Register TCL_R1_FSE_CACHE_DEBUG //// 6205 6206 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x) (x+0x000010ec) 6207 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_PHYS(x) (x+0x000010ec) 6208 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_RMSK 0x000003ff 6209 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_SHFT 0 6210 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_IN(x) \ 6211 in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), HWIO_TCL_R1_FSE_CACHE_DEBUG_RMSK) 6212 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_INM(x, mask) \ 6213 in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), mask) 6214 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_OUT(x, val) \ 6215 out_dword( HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), val) 6216 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_OUTM(x, mask, val) \ 6217 do {\ 6218 HWIO_INTLOCK(); \ 6219 out_dword_masked_ns(HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), mask, val, HWIO_TCL_R1_FSE_CACHE_DEBUG_IN(x)); \ 6220 HWIO_INTFREE();\ 6221 } while (0) 6222 6223 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_READ_IDX_BMSK 0x000003ff 6224 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_READ_IDX_SHFT 0x0 6225 6226 //// Register TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS //// 6227 6228 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x) (x+0x000010f0) 6229 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_PHYS(x) (x+0x000010f0) 6230 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_RMSK 0x007fffff 6231 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_SHFT 0 6232 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_IN(x) \ 6233 in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_RMSK) 6234 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_INM(x, mask) \ 6235 in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask) 6236 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_OUT(x, val) \ 6237 out_dword( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), val) 6238 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_OUTM(x, mask, val) \ 6239 do {\ 6240 HWIO_INTLOCK(); \ 6241 out_dword_masked_ns(HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask, val, HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_IN(x)); \ 6242 HWIO_INTFREE();\ 6243 } while (0) 6244 6245 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_BMSK 0x007ffff8 6246 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_SHFT 0x3 6247 6248 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_BMSK 0x00000004 6249 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_SHFT 0x2 6250 6251 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_DIRTY_BMSK 0x00000002 6252 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_DIRTY_SHFT 0x1 6253 6254 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_VALID_BMSK 0x00000001 6255 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_VALID_SHFT 0x0 6256 6257 //// Register TCL_R1_FSE_CACHE_DEBUG_ENTRY_n //// 6258 6259 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n) (base+0x10F4+0x4*n) 6260 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_PHYS(base, n) (base+0x10F4+0x4*n) 6261 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_RMSK 0xffffffff 6262 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_SHFT 0 6263 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_MAXn 31 6264 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_INI(base, n) \ 6265 in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_RMSK) 6266 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_INMI(base, n, mask) \ 6267 in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask) 6268 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_OUTI(base, n, val) \ 6269 out_dword( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), val) 6270 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_OUTMI(base, n, mask, val) \ 6271 do {\ 6272 HWIO_INTLOCK(); \ 6273 out_dword_masked_ns(HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask, val, HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_INI(base, n)); \ 6274 HWIO_INTFREE();\ 6275 } while (0) 6276 6277 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_VAL_BMSK 0xffffffff 6278 #define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_VAL_SHFT 0x0 6279 6280 //// Register TCL_R2_SW2TCL1_RING_HP //// 6281 6282 #define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x) (x+0x00002000) 6283 #define HWIO_TCL_R2_SW2TCL1_RING_HP_PHYS(x) (x+0x00002000) 6284 #define HWIO_TCL_R2_SW2TCL1_RING_HP_RMSK 0x000fffff 6285 #define HWIO_TCL_R2_SW2TCL1_RING_HP_SHFT 0 6286 #define HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x) \ 6287 in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL1_RING_HP_RMSK) 6288 #define HWIO_TCL_R2_SW2TCL1_RING_HP_INM(x, mask) \ 6289 in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), mask) 6290 #define HWIO_TCL_R2_SW2TCL1_RING_HP_OUT(x, val) \ 6291 out_dword( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), val) 6292 #define HWIO_TCL_R2_SW2TCL1_RING_HP_OUTM(x, mask, val) \ 6293 do {\ 6294 HWIO_INTLOCK(); \ 6295 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x)); \ 6296 HWIO_INTFREE();\ 6297 } while (0) 6298 6299 #define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_BMSK 0x000fffff 6300 #define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_SHFT 0x0 6301 6302 //// Register TCL_R2_SW2TCL1_RING_TP //// 6303 6304 #define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x) (x+0x00002004) 6305 #define HWIO_TCL_R2_SW2TCL1_RING_TP_PHYS(x) (x+0x00002004) 6306 #define HWIO_TCL_R2_SW2TCL1_RING_TP_RMSK 0x000fffff 6307 #define HWIO_TCL_R2_SW2TCL1_RING_TP_SHFT 0 6308 #define HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x) \ 6309 in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL1_RING_TP_RMSK) 6310 #define HWIO_TCL_R2_SW2TCL1_RING_TP_INM(x, mask) \ 6311 in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), mask) 6312 #define HWIO_TCL_R2_SW2TCL1_RING_TP_OUT(x, val) \ 6313 out_dword( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), val) 6314 #define HWIO_TCL_R2_SW2TCL1_RING_TP_OUTM(x, mask, val) \ 6315 do {\ 6316 HWIO_INTLOCK(); \ 6317 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x)); \ 6318 HWIO_INTFREE();\ 6319 } while (0) 6320 6321 #define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_BMSK 0x000fffff 6322 #define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_SHFT 0x0 6323 6324 //// Register TCL_R2_SW2TCL2_RING_HP //// 6325 6326 #define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x) (x+0x00002008) 6327 #define HWIO_TCL_R2_SW2TCL2_RING_HP_PHYS(x) (x+0x00002008) 6328 #define HWIO_TCL_R2_SW2TCL2_RING_HP_RMSK 0x000fffff 6329 #define HWIO_TCL_R2_SW2TCL2_RING_HP_SHFT 0 6330 #define HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x) \ 6331 in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL2_RING_HP_RMSK) 6332 #define HWIO_TCL_R2_SW2TCL2_RING_HP_INM(x, mask) \ 6333 in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), mask) 6334 #define HWIO_TCL_R2_SW2TCL2_RING_HP_OUT(x, val) \ 6335 out_dword( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), val) 6336 #define HWIO_TCL_R2_SW2TCL2_RING_HP_OUTM(x, mask, val) \ 6337 do {\ 6338 HWIO_INTLOCK(); \ 6339 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x)); \ 6340 HWIO_INTFREE();\ 6341 } while (0) 6342 6343 #define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_BMSK 0x000fffff 6344 #define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_SHFT 0x0 6345 6346 //// Register TCL_R2_SW2TCL2_RING_TP //// 6347 6348 #define HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x) (x+0x0000200c) 6349 #define HWIO_TCL_R2_SW2TCL2_RING_TP_PHYS(x) (x+0x0000200c) 6350 #define HWIO_TCL_R2_SW2TCL2_RING_TP_RMSK 0x000fffff 6351 #define HWIO_TCL_R2_SW2TCL2_RING_TP_SHFT 0 6352 #define HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x) \ 6353 in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL2_RING_TP_RMSK) 6354 #define HWIO_TCL_R2_SW2TCL2_RING_TP_INM(x, mask) \ 6355 in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), mask) 6356 #define HWIO_TCL_R2_SW2TCL2_RING_TP_OUT(x, val) \ 6357 out_dword( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), val) 6358 #define HWIO_TCL_R2_SW2TCL2_RING_TP_OUTM(x, mask, val) \ 6359 do {\ 6360 HWIO_INTLOCK(); \ 6361 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x)); \ 6362 HWIO_INTFREE();\ 6363 } while (0) 6364 6365 #define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_BMSK 0x000fffff 6366 #define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_SHFT 0x0 6367 6368 //// Register TCL_R2_SW2TCL3_RING_HP //// 6369 6370 #define HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x) (x+0x00002010) 6371 #define HWIO_TCL_R2_SW2TCL3_RING_HP_PHYS(x) (x+0x00002010) 6372 #define HWIO_TCL_R2_SW2TCL3_RING_HP_RMSK 0x000fffff 6373 #define HWIO_TCL_R2_SW2TCL3_RING_HP_SHFT 0 6374 #define HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x) \ 6375 in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL3_RING_HP_RMSK) 6376 #define HWIO_TCL_R2_SW2TCL3_RING_HP_INM(x, mask) \ 6377 in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), mask) 6378 #define HWIO_TCL_R2_SW2TCL3_RING_HP_OUT(x, val) \ 6379 out_dword( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), val) 6380 #define HWIO_TCL_R2_SW2TCL3_RING_HP_OUTM(x, mask, val) \ 6381 do {\ 6382 HWIO_INTLOCK(); \ 6383 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x)); \ 6384 HWIO_INTFREE();\ 6385 } while (0) 6386 6387 #define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_BMSK 0x000fffff 6388 #define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_SHFT 0x0 6389 6390 //// Register TCL_R2_SW2TCL3_RING_TP //// 6391 6392 #define HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x) (x+0x00002014) 6393 #define HWIO_TCL_R2_SW2TCL3_RING_TP_PHYS(x) (x+0x00002014) 6394 #define HWIO_TCL_R2_SW2TCL3_RING_TP_RMSK 0x000fffff 6395 #define HWIO_TCL_R2_SW2TCL3_RING_TP_SHFT 0 6396 #define HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x) \ 6397 in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL3_RING_TP_RMSK) 6398 #define HWIO_TCL_R2_SW2TCL3_RING_TP_INM(x, mask) \ 6399 in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), mask) 6400 #define HWIO_TCL_R2_SW2TCL3_RING_TP_OUT(x, val) \ 6401 out_dword( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), val) 6402 #define HWIO_TCL_R2_SW2TCL3_RING_TP_OUTM(x, mask, val) \ 6403 do {\ 6404 HWIO_INTLOCK(); \ 6405 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x)); \ 6406 HWIO_INTFREE();\ 6407 } while (0) 6408 6409 #define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_BMSK 0x000fffff 6410 #define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_SHFT 0x0 6411 6412 //// Register TCL_R2_SW2TCL_CMD_RING_HP //// 6413 6414 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x) (x+0x00002018) 6415 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_PHYS(x) (x+0x00002018) 6416 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_RMSK 0x000fffff 6417 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_SHFT 0 6418 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_IN(x) \ 6419 in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL_CMD_RING_HP_RMSK) 6420 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_INM(x, mask) \ 6421 in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), mask) 6422 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_OUT(x, val) \ 6423 out_dword( HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), val) 6424 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_OUTM(x, mask, val) \ 6425 do {\ 6426 HWIO_INTLOCK(); \ 6427 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL_CMD_RING_HP_IN(x)); \ 6428 HWIO_INTFREE();\ 6429 } while (0) 6430 6431 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_HEAD_PTR_BMSK 0x000fffff 6432 #define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_HEAD_PTR_SHFT 0x0 6433 6434 //// Register TCL_R2_SW2TCL_CMD_RING_TP //// 6435 6436 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x) (x+0x0000201c) 6437 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_PHYS(x) (x+0x0000201c) 6438 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_RMSK 0x000fffff 6439 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_SHFT 0 6440 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_IN(x) \ 6441 in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL_CMD_RING_TP_RMSK) 6442 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_INM(x, mask) \ 6443 in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), mask) 6444 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_OUT(x, val) \ 6445 out_dword( HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), val) 6446 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_OUTM(x, mask, val) \ 6447 do {\ 6448 HWIO_INTLOCK(); \ 6449 out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL_CMD_RING_TP_IN(x)); \ 6450 HWIO_INTFREE();\ 6451 } while (0) 6452 6453 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_TAIL_PTR_BMSK 0x000fffff 6454 #define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_TAIL_PTR_SHFT 0x0 6455 6456 //// Register TCL_R2_FW2TCL1_RING_HP //// 6457 6458 #define HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x) (x+0x00002020) 6459 #define HWIO_TCL_R2_FW2TCL1_RING_HP_PHYS(x) (x+0x00002020) 6460 #define HWIO_TCL_R2_FW2TCL1_RING_HP_RMSK 0x0000ffff 6461 #define HWIO_TCL_R2_FW2TCL1_RING_HP_SHFT 0 6462 #define HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x) \ 6463 in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), HWIO_TCL_R2_FW2TCL1_RING_HP_RMSK) 6464 #define HWIO_TCL_R2_FW2TCL1_RING_HP_INM(x, mask) \ 6465 in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), mask) 6466 #define HWIO_TCL_R2_FW2TCL1_RING_HP_OUT(x, val) \ 6467 out_dword( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), val) 6468 #define HWIO_TCL_R2_FW2TCL1_RING_HP_OUTM(x, mask, val) \ 6469 do {\ 6470 HWIO_INTLOCK(); \ 6471 out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x)); \ 6472 HWIO_INTFREE();\ 6473 } while (0) 6474 6475 #define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6476 #define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_SHFT 0x0 6477 6478 //// Register TCL_R2_FW2TCL1_RING_TP //// 6479 6480 #define HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x) (x+0x00002024) 6481 #define HWIO_TCL_R2_FW2TCL1_RING_TP_PHYS(x) (x+0x00002024) 6482 #define HWIO_TCL_R2_FW2TCL1_RING_TP_RMSK 0x0000ffff 6483 #define HWIO_TCL_R2_FW2TCL1_RING_TP_SHFT 0 6484 #define HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x) \ 6485 in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), HWIO_TCL_R2_FW2TCL1_RING_TP_RMSK) 6486 #define HWIO_TCL_R2_FW2TCL1_RING_TP_INM(x, mask) \ 6487 in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), mask) 6488 #define HWIO_TCL_R2_FW2TCL1_RING_TP_OUT(x, val) \ 6489 out_dword( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), val) 6490 #define HWIO_TCL_R2_FW2TCL1_RING_TP_OUTM(x, mask, val) \ 6491 do {\ 6492 HWIO_INTLOCK(); \ 6493 out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x)); \ 6494 HWIO_INTFREE();\ 6495 } while (0) 6496 6497 #define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6498 #define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_SHFT 0x0 6499 6500 //// Register TCL_R2_TCL2TQM_RING_HP //// 6501 6502 #define HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x) (x+0x00002028) 6503 #define HWIO_TCL_R2_TCL2TQM_RING_HP_PHYS(x) (x+0x00002028) 6504 #define HWIO_TCL_R2_TCL2TQM_RING_HP_RMSK 0x0000ffff 6505 #define HWIO_TCL_R2_TCL2TQM_RING_HP_SHFT 0 6506 #define HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x) \ 6507 in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), HWIO_TCL_R2_TCL2TQM_RING_HP_RMSK) 6508 #define HWIO_TCL_R2_TCL2TQM_RING_HP_INM(x, mask) \ 6509 in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), mask) 6510 #define HWIO_TCL_R2_TCL2TQM_RING_HP_OUT(x, val) \ 6511 out_dword( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), val) 6512 #define HWIO_TCL_R2_TCL2TQM_RING_HP_OUTM(x, mask, val) \ 6513 do {\ 6514 HWIO_INTLOCK(); \ 6515 out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x)); \ 6516 HWIO_INTFREE();\ 6517 } while (0) 6518 6519 #define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6520 #define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_SHFT 0x0 6521 6522 //// Register TCL_R2_TCL2TQM_RING_TP //// 6523 6524 #define HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x) (x+0x0000202c) 6525 #define HWIO_TCL_R2_TCL2TQM_RING_TP_PHYS(x) (x+0x0000202c) 6526 #define HWIO_TCL_R2_TCL2TQM_RING_TP_RMSK 0x0000ffff 6527 #define HWIO_TCL_R2_TCL2TQM_RING_TP_SHFT 0 6528 #define HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x) \ 6529 in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), HWIO_TCL_R2_TCL2TQM_RING_TP_RMSK) 6530 #define HWIO_TCL_R2_TCL2TQM_RING_TP_INM(x, mask) \ 6531 in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), mask) 6532 #define HWIO_TCL_R2_TCL2TQM_RING_TP_OUT(x, val) \ 6533 out_dword( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), val) 6534 #define HWIO_TCL_R2_TCL2TQM_RING_TP_OUTM(x, mask, val) \ 6535 do {\ 6536 HWIO_INTLOCK(); \ 6537 out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x)); \ 6538 HWIO_INTFREE();\ 6539 } while (0) 6540 6541 #define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6542 #define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_SHFT 0x0 6543 6544 //// Register TCL_R2_TCL_STATUS1_RING_HP //// 6545 6546 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x) (x+0x00002030) 6547 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_PHYS(x) (x+0x00002030) 6548 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_RMSK 0x0000ffff 6549 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_SHFT 0 6550 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x) \ 6551 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), HWIO_TCL_R2_TCL_STATUS1_RING_HP_RMSK) 6552 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_INM(x, mask) \ 6553 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), mask) 6554 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUT(x, val) \ 6555 out_dword( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), val) 6556 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUTM(x, mask, val) \ 6557 do {\ 6558 HWIO_INTLOCK(); \ 6559 out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x)); \ 6560 HWIO_INTFREE();\ 6561 } while (0) 6562 6563 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6564 #define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_SHFT 0x0 6565 6566 //// Register TCL_R2_TCL_STATUS1_RING_TP //// 6567 6568 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x) (x+0x00002034) 6569 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_PHYS(x) (x+0x00002034) 6570 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_RMSK 0x0000ffff 6571 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_SHFT 0 6572 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x) \ 6573 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), HWIO_TCL_R2_TCL_STATUS1_RING_TP_RMSK) 6574 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_INM(x, mask) \ 6575 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), mask) 6576 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUT(x, val) \ 6577 out_dword( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), val) 6578 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUTM(x, mask, val) \ 6579 do {\ 6580 HWIO_INTLOCK(); \ 6581 out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x)); \ 6582 HWIO_INTFREE();\ 6583 } while (0) 6584 6585 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6586 #define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_SHFT 0x0 6587 6588 //// Register TCL_R2_TCL_STATUS2_RING_HP //// 6589 6590 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x) (x+0x00002038) 6591 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_PHYS(x) (x+0x00002038) 6592 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_RMSK 0x0000ffff 6593 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_SHFT 0 6594 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_IN(x) \ 6595 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), HWIO_TCL_R2_TCL_STATUS2_RING_HP_RMSK) 6596 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_INM(x, mask) \ 6597 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), mask) 6598 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_OUT(x, val) \ 6599 out_dword( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), val) 6600 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_OUTM(x, mask, val) \ 6601 do {\ 6602 HWIO_INTLOCK(); \ 6603 out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS2_RING_HP_IN(x)); \ 6604 HWIO_INTFREE();\ 6605 } while (0) 6606 6607 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6608 #define HWIO_TCL_R2_TCL_STATUS2_RING_HP_HEAD_PTR_SHFT 0x0 6609 6610 //// Register TCL_R2_TCL_STATUS2_RING_TP //// 6611 6612 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x) (x+0x0000203c) 6613 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_PHYS(x) (x+0x0000203c) 6614 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_RMSK 0x0000ffff 6615 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_SHFT 0 6616 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_IN(x) \ 6617 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), HWIO_TCL_R2_TCL_STATUS2_RING_TP_RMSK) 6618 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_INM(x, mask) \ 6619 in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), mask) 6620 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_OUT(x, val) \ 6621 out_dword( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), val) 6622 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_OUTM(x, mask, val) \ 6623 do {\ 6624 HWIO_INTLOCK(); \ 6625 out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS2_RING_TP_IN(x)); \ 6626 HWIO_INTFREE();\ 6627 } while (0) 6628 6629 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6630 #define HWIO_TCL_R2_TCL_STATUS2_RING_TP_TAIL_PTR_SHFT 0x0 6631 6632 //// Register TCL_R2_TCL2FW_RING_HP //// 6633 6634 #define HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x) (x+0x00002040) 6635 #define HWIO_TCL_R2_TCL2FW_RING_HP_PHYS(x) (x+0x00002040) 6636 #define HWIO_TCL_R2_TCL2FW_RING_HP_RMSK 0x0000ffff 6637 #define HWIO_TCL_R2_TCL2FW_RING_HP_SHFT 0 6638 #define HWIO_TCL_R2_TCL2FW_RING_HP_IN(x) \ 6639 in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), HWIO_TCL_R2_TCL2FW_RING_HP_RMSK) 6640 #define HWIO_TCL_R2_TCL2FW_RING_HP_INM(x, mask) \ 6641 in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), mask) 6642 #define HWIO_TCL_R2_TCL2FW_RING_HP_OUT(x, val) \ 6643 out_dword( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), val) 6644 #define HWIO_TCL_R2_TCL2FW_RING_HP_OUTM(x, mask, val) \ 6645 do {\ 6646 HWIO_INTLOCK(); \ 6647 out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2FW_RING_HP_IN(x)); \ 6648 HWIO_INTFREE();\ 6649 } while (0) 6650 6651 #define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_BMSK 0x0000ffff 6652 #define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_SHFT 0x0 6653 6654 //// Register TCL_R2_TCL2FW_RING_TP //// 6655 6656 #define HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x) (x+0x00002044) 6657 #define HWIO_TCL_R2_TCL2FW_RING_TP_PHYS(x) (x+0x00002044) 6658 #define HWIO_TCL_R2_TCL2FW_RING_TP_RMSK 0x0000ffff 6659 #define HWIO_TCL_R2_TCL2FW_RING_TP_SHFT 0 6660 #define HWIO_TCL_R2_TCL2FW_RING_TP_IN(x) \ 6661 in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), HWIO_TCL_R2_TCL2FW_RING_TP_RMSK) 6662 #define HWIO_TCL_R2_TCL2FW_RING_TP_INM(x, mask) \ 6663 in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), mask) 6664 #define HWIO_TCL_R2_TCL2FW_RING_TP_OUT(x, val) \ 6665 out_dword( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), val) 6666 #define HWIO_TCL_R2_TCL2FW_RING_TP_OUTM(x, mask, val) \ 6667 do {\ 6668 HWIO_INTLOCK(); \ 6669 out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2FW_RING_TP_IN(x)); \ 6670 HWIO_INTFREE();\ 6671 } while (0) 6672 6673 #define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_BMSK 0x0000ffff 6674 #define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_SHFT 0x0 6675 6676 6677 #endif 6678 6679