1 /* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 2 * 3 * Permission to use, copy, modify, and/or distribute this software for any 4 * purpose with or without fee is hereby granted, provided that the above 5 * copyright notice and this permission notice appear in all copies. 6 * 7 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 8 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 9 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 10 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 11 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 12 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 13 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 */ 15 16 // $ATH_LICENSE_HW_HDR_C$ 17 // 18 // DO NOT EDIT! This file is automatically generated 19 // These definitions are tied to a particular hardware layout 20 21 22 #ifndef _PHYRX_PKT_END_INFO_H_ 23 #define _PHYRX_PKT_END_INFO_H_ 24 #if !defined(__ASSEMBLER__) 25 #endif 26 27 #include "rx_location_info.h" 28 #include "rx_timing_offset_info.h" 29 #include "receive_rssi_info.h" 30 31 // ################ START SUMMARY ################# 32 // 33 // Dword Fields 34 // 0 phy_internal_nap[0], location_info_valid[1], timing_info_valid[2], rssi_info_valid[3], rx_frame_correction_needed[4], frameless_frame_received[5], reserved_0a[11:6], dl_ofdma_info_valid[12], dl_ofdma_ru_start_index[19:13], dl_ofdma_ru_width[26:20], reserved_0b[31:27] 35 // 1 phy_timestamp_1_lower_32[31:0] 36 // 2 phy_timestamp_1_upper_32[31:0] 37 // 3 phy_timestamp_2_lower_32[31:0] 38 // 4 phy_timestamp_2_upper_32[31:0] 39 // 5-13 struct rx_location_info rx_location_info_details; 40 // 14 struct rx_timing_offset_info rx_timing_offset_info_details; 41 // 15-30 struct receive_rssi_info post_rssi_info_details; 42 // 31 phy_sw_status_31_0[31:0] 43 // 32 phy_sw_status_63_32[31:0] 44 // 45 // ################ END SUMMARY ################# 46 47 #define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 33 48 49 struct phyrx_pkt_end_info { 50 uint32_t phy_internal_nap : 1, //[0] 51 location_info_valid : 1, //[1] 52 timing_info_valid : 1, //[2] 53 rssi_info_valid : 1, //[3] 54 rx_frame_correction_needed : 1, //[4] 55 frameless_frame_received : 1, //[5] 56 reserved_0a : 6, //[11:6] 57 dl_ofdma_info_valid : 1, //[12] 58 dl_ofdma_ru_start_index : 7, //[19:13] 59 dl_ofdma_ru_width : 7, //[26:20] 60 reserved_0b : 5; //[31:27] 61 uint32_t phy_timestamp_1_lower_32 : 32; //[31:0] 62 uint32_t phy_timestamp_1_upper_32 : 32; //[31:0] 63 uint32_t phy_timestamp_2_lower_32 : 32; //[31:0] 64 uint32_t phy_timestamp_2_upper_32 : 32; //[31:0] 65 struct rx_location_info rx_location_info_details; 66 struct rx_timing_offset_info rx_timing_offset_info_details; 67 struct receive_rssi_info post_rssi_info_details; 68 uint32_t phy_sw_status_31_0 : 32; //[31:0] 69 uint32_t phy_sw_status_63_32 : 32; //[31:0] 70 }; 71 72 /* 73 74 phy_internal_nap 75 76 When set, PHY RX entered an internal NAP state, as PHY 77 determined that this reception was not destined to this 78 device 79 80 location_info_valid 81 82 Indicates that the RX_LOCATION_INFO structure later on 83 in the TLV contains valid info 84 85 timing_info_valid 86 87 Indicates that the RX_TIMING_OFFSET_INFO structure later 88 on in the TLV contains valid info 89 90 rssi_info_valid 91 92 Indicates that the RECEIVE_RSSI_INFO structure later on 93 in the TLV contains valid info 94 95 rx_frame_correction_needed 96 97 When clear, no action is needed in the MAC. 98 99 100 101 When set, the falling edge of the rx_frame happened 4us 102 too late. MAC will need to compensate for this delay in 103 order to maintain proper SIFS timing and/or not to get 104 de-slotted. 105 106 107 108 PHY uses this for very short 11a frames. 109 110 111 112 When set, PHY will have passed this TLV to the MAC up to 113 8 us into the 'real SIFS' time, and thus within 4us from the 114 falling edge of the rx_frame. 115 116 117 118 <legal all> 119 120 frameless_frame_received 121 122 When set, PHY has received the 'frameless frame' . Can 123 be used in the 'MU-RTS -CTS exchange where CTS reception can 124 be problematic. 125 126 <legal all> 127 128 reserved_0a 129 130 <legal 0> 131 132 dl_ofdma_info_valid 133 134 When set, the following DL_ofdma_... fields are valid. 135 136 It provides the MAC insight into which RU was allocated 137 to this device. 138 139 <legal all> 140 141 dl_ofdma_ru_start_index 142 143 RU index number to which User is assigned 144 145 RU numbering is over the entire BW, starting from 0 and 146 in increasing frequency order and not primary-secondary 147 order 148 149 <legal 0-73> 150 151 dl_ofdma_ru_width 152 153 The size of the RU for this user. 154 155 In units of 1 (26 tone) RU 156 157 <legal 1-74> 158 159 reserved_0b 160 161 <legal 0> 162 163 phy_timestamp_1_lower_32 164 165 TODO PHY: cleanup descriptionThe PHY timestamp in the 166 AMPI of the first rising edge of rx_clear_pri after 167 TX_PHY_DESC. . This field should set to 0 by the PHY and 168 should be updated by the AMPI before being forwarded to the 169 rest of the MAC. This field indicates the lower 32 bits of 170 the timestamp 171 172 phy_timestamp_1_upper_32 173 174 TODO PHY: cleanup description 175 176 The PHY timestamp in the AMPI of the first rising edge 177 of rx_clear_pri after TX_PHY_DESC. This field should set to 178 0 by the PHY and should be updated by the AMPI before being 179 forwarded to the rest of the MAC. This field indicates the 180 upper 32 bits of the timestamp 181 182 phy_timestamp_2_lower_32 183 184 TODO PHY: cleanup description 185 186 The PHY timestamp in the AMPI of the rising edge of 187 rx_clear_pri after RX_RSSI_LEGACY. This field should set to 188 0 by the PHY and should be updated by the AMPI before being 189 forwarded to the rest of the MAC. This field indicates the 190 lower 32 bits of the timestamp 191 192 phy_timestamp_2_upper_32 193 194 TODO PHY: cleanup description 195 196 The PHY timestamp in the AMPI of the rising edge of 197 rx_clear_pri after RX_RSSI_LEGACY. This field should set to 198 0 by the PHY and should be updated by the AMPI before being 199 forwarded to the rest of the MAC. This field indicates the 200 upper 32 bits of the timestamp 201 202 struct rx_location_info rx_location_info_details 203 204 Overview of location related info 205 206 struct rx_timing_offset_info rx_timing_offset_info_details 207 208 Overview of timing offset related info 209 210 struct receive_rssi_info post_rssi_info_details 211 212 Overview of the post-RSSI values. 213 214 phy_sw_status_31_0 215 216 Some PHY micro code status that can be put in here. 217 Details of definition within SW specification 218 219 This field can be used for debugging, FW - SW message 220 exchange, etc. 221 222 It could for example be a pointer to a DDR memory 223 location where PHY FW put some debug info. 224 225 <legal all> 226 227 phy_sw_status_63_32 228 229 Some PHY micro code status that can be put in here. 230 Details of definition within SW specification 231 232 This field can be used for debugging, FW - SW message 233 exchange, etc. 234 235 It could for example be a pointer to a DDR memory 236 location where PHY FW put some debug info. 237 238 <legal all> 239 */ 240 241 242 /* Description PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP 243 244 When set, PHY RX entered an internal NAP state, as PHY 245 determined that this reception was not destined to this 246 device 247 */ 248 #define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_OFFSET 0x00000000 249 #define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_LSB 0 250 #define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_MASK 0x00000001 251 252 /* Description PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID 253 254 Indicates that the RX_LOCATION_INFO structure later on 255 in the TLV contains valid info 256 */ 257 #define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_OFFSET 0x00000000 258 #define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_LSB 1 259 #define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_MASK 0x00000002 260 261 /* Description PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID 262 263 Indicates that the RX_TIMING_OFFSET_INFO structure later 264 on in the TLV contains valid info 265 */ 266 #define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_OFFSET 0x00000000 267 #define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_LSB 2 268 #define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_MASK 0x00000004 269 270 /* Description PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID 271 272 Indicates that the RECEIVE_RSSI_INFO structure later on 273 in the TLV contains valid info 274 */ 275 #define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_OFFSET 0x00000000 276 #define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_LSB 3 277 #define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_MASK 0x00000008 278 279 /* Description PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED 280 281 When clear, no action is needed in the MAC. 282 283 284 285 When set, the falling edge of the rx_frame happened 4us 286 too late. MAC will need to compensate for this delay in 287 order to maintain proper SIFS timing and/or not to get 288 de-slotted. 289 290 291 292 PHY uses this for very short 11a frames. 293 294 295 296 When set, PHY will have passed this TLV to the MAC up to 297 8 us into the 'real SIFS' time, and thus within 4us from the 298 falling edge of the rx_frame. 299 300 301 302 <legal all> 303 */ 304 #define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_OFFSET 0x00000000 305 #define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_LSB 4 306 #define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_MASK 0x00000010 307 308 /* Description PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED 309 310 When set, PHY has received the 'frameless frame' . Can 311 be used in the 'MU-RTS -CTS exchange where CTS reception can 312 be problematic. 313 314 <legal all> 315 */ 316 #define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 317 #define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_LSB 5 318 #define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 319 320 /* Description PHYRX_PKT_END_INFO_0_RESERVED_0A 321 322 <legal 0> 323 */ 324 #define PHYRX_PKT_END_INFO_0_RESERVED_0A_OFFSET 0x00000000 325 #define PHYRX_PKT_END_INFO_0_RESERVED_0A_LSB 6 326 #define PHYRX_PKT_END_INFO_0_RESERVED_0A_MASK 0x00000fc0 327 328 /* Description PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID 329 330 When set, the following DL_ofdma_... fields are valid. 331 332 It provides the MAC insight into which RU was allocated 333 to this device. 334 335 <legal all> 336 */ 337 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_OFFSET 0x00000000 338 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_LSB 12 339 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_MASK 0x00001000 340 341 /* Description PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX 342 343 RU index number to which User is assigned 344 345 RU numbering is over the entire BW, starting from 0 and 346 in increasing frequency order and not primary-secondary 347 order 348 349 <legal 0-73> 350 */ 351 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_OFFSET 0x00000000 352 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_LSB 13 353 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_MASK 0x000fe000 354 355 /* Description PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH 356 357 The size of the RU for this user. 358 359 In units of 1 (26 tone) RU 360 361 <legal 1-74> 362 */ 363 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_OFFSET 0x00000000 364 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_LSB 20 365 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_MASK 0x07f00000 366 367 /* Description PHYRX_PKT_END_INFO_0_RESERVED_0B 368 369 <legal 0> 370 */ 371 #define PHYRX_PKT_END_INFO_0_RESERVED_0B_OFFSET 0x00000000 372 #define PHYRX_PKT_END_INFO_0_RESERVED_0B_LSB 27 373 #define PHYRX_PKT_END_INFO_0_RESERVED_0B_MASK 0xf8000000 374 375 /* Description PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32 376 377 TODO PHY: cleanup descriptionThe PHY timestamp in the 378 AMPI of the first rising edge of rx_clear_pri after 379 TX_PHY_DESC. . This field should set to 0 by the PHY and 380 should be updated by the AMPI before being forwarded to the 381 rest of the MAC. This field indicates the lower 32 bits of 382 the timestamp 383 */ 384 #define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 385 #define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_LSB 0 386 #define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff 387 388 /* Description PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32 389 390 TODO PHY: cleanup description 391 392 The PHY timestamp in the AMPI of the first rising edge 393 of rx_clear_pri after TX_PHY_DESC. This field should set to 394 0 by the PHY and should be updated by the AMPI before being 395 forwarded to the rest of the MAC. This field indicates the 396 upper 32 bits of the timestamp 397 */ 398 #define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 399 #define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_LSB 0 400 #define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff 401 402 /* Description PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32 403 404 TODO PHY: cleanup description 405 406 The PHY timestamp in the AMPI of the rising edge of 407 rx_clear_pri after RX_RSSI_LEGACY. This field should set to 408 0 by the PHY and should be updated by the AMPI before being 409 forwarded to the rest of the MAC. This field indicates the 410 lower 32 bits of the timestamp 411 */ 412 #define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c 413 #define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_LSB 0 414 #define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff 415 416 /* Description PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32 417 418 TODO PHY: cleanup description 419 420 The PHY timestamp in the AMPI of the rising edge of 421 rx_clear_pri after RX_RSSI_LEGACY. This field should set to 422 0 by the PHY and should be updated by the AMPI before being 423 forwarded to the rest of the MAC. This field indicates the 424 upper 32 bits of the timestamp 425 */ 426 #define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 427 #define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_LSB 0 428 #define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff 429 430 /* EXTERNAL REFERENCE : struct rx_location_info rx_location_info_details */ 431 432 433 /* Description PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY 434 435 For 20/40/80, this field shows the RTT first arrival 436 correction value computed from L-LTF on the first selected 437 Rx chain 438 439 440 441 For 80+80, this field shows the RTT first arrival 442 correction value computed from L-LTF on pri80 on the 443 selected pri80 Rx chain 444 445 446 447 16 bits, signed 12.4. 12 bits integer to cover -6.4us to 448 6.4us, and 4 bits fraction to cover pri80 and 32x FAC 449 interpolation 450 451 452 453 clock unit is 320MHz 454 455 <legal all> 456 */ 457 #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_OFFSET 0x00000014 458 #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_LSB 0 459 #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_MASK 0x0000ffff 460 461 /* Description PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80 462 463 For 20/40/80, this field shows the RTT first arrival 464 correction value computed from L-LTF on the second selected 465 Rx chain 466 467 468 469 For 80+80, this field shows the RTT first arrival 470 correction value computed from L-LTF on ext80 on the 471 selected ext80 Rx chain 472 473 474 475 16 bits, signed 12.4. 12 bits integer to cover -6.4us to 476 6.4us, and 4 bits fraction to cover ext80 and 32x FAC 477 interpolation 478 479 480 481 clock unit is 320MHz 482 483 <legal all> 484 */ 485 #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_OFFSET 0x00000014 486 #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_LSB 16 487 #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_MASK 0xffff0000 488 489 /* Description PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT 490 491 For 20/40/80, this field shows the RTT first arrival 492 correction value computed from (V)HT/HE-LTF on the first 493 selected Rx chain 494 495 496 497 For 80+80, this field shows the RTT first arrival 498 correction value computed from (V)HT/HE-LTF on pri80 on the 499 selected pri80 Rx chain 500 501 502 503 16 bits, signed 12.4. 12 bits integer to cover -6.4us to 504 6.4us, and 4 bits fraction to cover pri80 and 32x FAC 505 interpolation 506 507 508 509 clock unit is 320MHz 510 511 <legal all> 512 */ 513 #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_OFFSET 0x00000018 514 #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_LSB 0 515 #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_MASK 0x0000ffff 516 517 /* Description PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80 518 519 For 20/40/80, this field shows the RTT first arrival 520 correction value computed from (V)HT/HE-LTF on the second 521 selected Rx chain 522 523 524 525 For 80+80, this field shows the RTT first arrival 526 correction value computed from (V)HT/HE-LTF on ext80 on the 527 selected ext80 Rx chain 528 529 530 531 16 bits, signed 12.4. 12 bits integer to cover -6.4us to 532 6.4us, and 4 bits fraction to cover ext80 and 32x FAC 533 interpolation 534 535 536 537 clock unit is 320MHz 538 539 <legal all> 540 */ 541 #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_OFFSET 0x00000018 542 #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_LSB 16 543 #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_MASK 0xffff0000 544 545 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS 546 547 Status of rtt_fac_legacy 548 549 550 551 <enum 0 location_fac_legacy_status_not_valid> 552 553 <enum 1 location_fac_legacy_status_valid> 554 555 <legal all> 556 */ 557 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_OFFSET 0x0000001c 558 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_LSB 0 559 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_MASK 0x00000001 560 561 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS 562 563 Status of rtt_fac_legacy_ext80 564 565 566 567 <enum 0 location_fac_legacy_ext80_status_not_valid> 568 569 <enum 1 location_fac_legacy_ext80_status_valid> 570 571 <legal all> 572 */ 573 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_OFFSET 0x0000001c 574 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_LSB 1 575 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_MASK 0x00000002 576 577 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS 578 579 Status of rtt_fac_vht 580 581 582 583 <enum 0 location_fac_vht_status_not_valid> 584 585 <enum 1 location_fac_vht_status_valid> 586 587 <legal all> 588 */ 589 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_OFFSET 0x0000001c 590 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_LSB 2 591 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_MASK 0x00000004 592 593 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS 594 595 Status of rtt_fac_vht_ext80 596 597 598 599 <enum 0 location_fac_vht_ext80_status_not_valid> 600 601 <enum 1 location_fac_vht_ext80_status_valid> 602 603 <legal all> 604 */ 605 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_OFFSET 0x0000001c 606 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_LSB 3 607 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_MASK 0x00000008 608 609 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS 610 611 To support fine SIFS adjustment, need to provide FAC 612 value @ integer number of 320 MHz clock cycles to MAC. It 613 is from L-LTF if it is a Legacy packet and from (V)HT/HE-LTF 614 if it is a (V)HT/HE packet 615 616 617 618 12 bits, signed, no fractional part 619 620 <legal all> 621 */ 622 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_OFFSET 0x0000001c 623 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_LSB 4 624 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_MASK 0x0000fff0 625 626 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS 627 628 Status of rtt_fac_sifs 629 630 0: not valid 631 632 1: valid and from L-LTF 633 634 2: valid and from (V)HT/HE-LTF 635 636 3: reserved 637 638 <legal 0-2> 639 */ 640 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_OFFSET 0x0000001c 641 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_LSB 16 642 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_MASK 0x00030000 643 644 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS 645 646 Status of channel frequency response dump 647 648 649 650 <enum 0 location_CFR_dump_not_valid> 651 652 <enum 1 location_CFR_dump_valid> 653 654 <legal all> 655 */ 656 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000001c 657 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 18 658 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00040000 659 660 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS 661 662 Status of channel impulse response dump 663 664 665 666 <enum 0 location_CIR_dump_not_valid> 667 668 <enum 1 location_CIR_dump_valid> 669 670 <legal all> 671 */ 672 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000001c 673 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 19 674 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0x00080000 675 676 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE 677 678 Channel dump size. It shows how many tones in CFR in 679 one chain, for example, it will show 52 for Legacy20 and 484 680 for VHT160 681 682 683 684 <legal all> 685 */ 686 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_OFFSET 0x0000001c 687 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_LSB 20 688 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_MASK 0x7ff00000 689 690 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE 691 692 Indicator showing if HW IFFT mode or SW IFFT mode 693 694 695 696 <enum 0 location_sw_ifft_mode> 697 698 <enum 1 location_hw_ifft_mode> 699 700 <legal all> 701 */ 702 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000001c 703 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 31 704 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x80000000 705 706 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS 707 708 Indicate if BTCF is used to capture the timestamps 709 710 711 712 <enum 0 location_not_BTCF_based_ts> 713 714 <enum 1 location_BTCF_based_ts> 715 716 <legal all> 717 */ 718 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_OFFSET 0x00000020 719 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_LSB 0 720 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_MASK 0x00000001 721 722 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE 723 724 Indicate preamble type 725 726 727 728 <enum 0 location_preamble_type_legacy> 729 730 <enum 1 location_preamble_type_ht> 731 732 <enum 2 location_preamble_type_vht> 733 734 <enum 3 location_preamble_type_he_su_4xltf> 735 736 <enum 4 location_preamble_type_he_su_2xltf> 737 738 <enum 5 location_preamble_type_he_su_1xltf> 739 740 <enum 6 741 location_preamble_type_he_trigger_based_ul_4xltf> 742 743 <enum 7 744 location_preamble_type_he_trigger_based_ul_2xltf> 745 746 <enum 8 747 location_preamble_type_he_trigger_based_ul_1xltf> 748 749 <enum 9 location_preamble_type_he_mu_4xltf> 750 751 <enum 10 location_preamble_type_he_mu_2xltf> 752 753 <enum 11 location_preamble_type_he_mu_1xltf> 754 755 <enum 12 756 location_preamble_type_he_extended_range_su_4xltf> 757 758 <enum 13 759 location_preamble_type_he_extended_range_su_2xltf> 760 761 <enum 14 762 location_preamble_type_he_extended_range_su_1xltf> 763 764 <legal 0-14> 765 */ 766 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x00000020 767 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 1 768 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000003e 769 770 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG 771 772 Indicate the bandwidth of L-LTF 773 774 775 776 <enum 0 location_pkt_bw_20MHz> 777 778 <enum 1 location_pkt_bw_40MHz> 779 780 <enum 2 location_pkt_bw_80MHz> 781 782 <enum 3 location_pkt_bw_160MHz> 783 784 <legal all> 785 */ 786 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x00000020 787 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 6 788 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x000000c0 789 790 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT 791 792 Indicate the bandwidth of (V)HT/HE-LTF 793 794 795 796 <enum 0 location_pkt_bw_20MHz> 797 798 <enum 1 location_pkt_bw_40MHz> 799 800 <enum 2 location_pkt_bw_80MHz> 801 802 <enum 3 location_pkt_bw_160MHz> 803 804 <legal all> 805 */ 806 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x00000020 807 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 8 808 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x00000300 809 810 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE 811 812 Indicate GI (guard interval) type 813 814 815 816 <enum 0 gi_0_8_us > HE related GI. Can also be used 817 for HE 818 819 <enum 1 gi_0_4_us > HE related GI. Can also be used 820 for HE 821 822 <enum 2 gi_1_6_us > HE related GI 823 824 <enum 3 gi_3_2_us > HE related GI 825 826 <legal 0 - 3> 827 */ 828 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x00000020 829 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 10 830 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000c00 831 832 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE 833 834 Bits 0~4 indicate MCS rate, if Legacy, 835 836 0: 48 Mbps, 837 838 1: 24 Mbps, 839 840 2: 12 Mbps, 841 842 3: 6 Mbps, 843 844 4: 54 Mbps, 845 846 5: 36 Mbps, 847 848 6: 18 Mbps, 849 850 7: 9 Mbps, 851 852 853 854 if HT, 0-7: MCS0-MCS7, 855 856 if VHT, 0-9: MCS0-MCS9, 857 858 859 <legal all> 860 */ 861 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x00000020 862 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 12 863 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0x0001f000 864 865 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN 866 867 For 20/40/80, this field shows the first selected Rx 868 chain that is used in HW IFFT mode 869 870 871 872 For 80+80, this field shows the selected pri80 Rx chain 873 that is used in HW IFFT mode 874 875 876 877 <enum 0 location_strongest_chain_is_0> 878 879 <enum 1 location_strongest_chain_is_1> 880 881 <enum 2 location_strongest_chain_is_2> 882 883 <enum 3 location_strongest_chain_is_3> 884 885 <enum 4 location_strongest_chain_is_4> 886 887 <enum 5 location_strongest_chain_is_5> 888 889 <enum 6 location_strongest_chain_is_6> 890 891 <enum 7 location_strongest_chain_is_7> 892 893 <legal all> 894 */ 895 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_OFFSET 0x00000020 896 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_LSB 17 897 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_MASK 0x000e0000 898 899 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80 900 901 For 20/40/80, this field shows the second selected Rx 902 chain that is used in HW IFFT mode 903 904 905 906 For 80+80, this field shows the selected ext80 Rx chain 907 that is used in HW IFFT mode 908 909 910 911 <enum 0 location_strongest_chain_is_0> 912 913 <enum 1 location_strongest_chain_is_1> 914 915 <enum 2 location_strongest_chain_is_2> 916 917 <enum 3 location_strongest_chain_is_3> 918 919 <enum 4 location_strongest_chain_is_4> 920 921 <enum 5 location_strongest_chain_is_5> 922 923 <enum 6 location_strongest_chain_is_6> 924 925 <enum 7 location_strongest_chain_is_7> 926 927 <legal all> 928 */ 929 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_OFFSET 0x00000020 930 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_LSB 20 931 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_MASK 0x00700000 932 933 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK 934 935 Rx chain mask, each bit is a Rx chain 936 937 0: the Rx chain is not used 938 939 1: the Rx chain is used 940 941 Support up to 8 Rx chains 942 943 <legal all> 944 */ 945 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x00000020 946 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 23 947 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x7f800000 948 949 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3 950 951 <legal 0> 952 */ 953 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x00000020 954 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 31 955 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x80000000 956 957 /* Description PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS 958 959 RX packet start timestamp 960 961 962 963 It reports the time the first L-STF ADC sample arrived 964 at RX antenna 965 966 967 968 clock unit is 480MHz 969 970 <legal all> 971 */ 972 #define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x00000024 973 #define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 0 974 #define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff 975 976 /* Description PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS 977 978 RX packet end timestamp 979 980 981 982 It reports the time the last symbol's last ADC sample 983 arrived at RX antenna 984 985 986 987 clock unit is 480MHz 988 989 <legal all> 990 */ 991 #define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x00000028 992 #define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 0 993 #define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff 994 995 /* Description PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START 996 997 The phase of the SFO of the first symbol's first FFT 998 input sample 999 1000 1001 1002 12 bits, signed 6.6. 6 bits integer to cover -66.7ns to 1003 66.7ns, and 6 bits fraction to provide a resolution of 1004 0.03ns 1005 1006 1007 1008 clock unit is 480MHz 1009 1010 <legal all> 1011 */ 1012 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_OFFSET 0x0000002c 1013 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_LSB 0 1014 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_MASK 0x00000fff 1015 1016 /* Description PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END 1017 1018 The phase of the SFO of the last symbol's last FFT input 1019 sample 1020 1021 1022 1023 12 bits, signed 6.6. 6 bits integer to cover -66.7ns to 1024 66.7ns, and 6 bits fraction to provide a resolution of 1025 0.03ns 1026 1027 1028 1029 clock unit is 480MHz 1030 1031 <legal all> 1032 */ 1033 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_OFFSET 0x0000002c 1034 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_LSB 12 1035 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_MASK 0x00fff000 1036 1037 /* Description PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8 1038 1039 The high 8 bits of the 40 bits pointer pointed to the 1040 external RTT channel information buffer 1041 1042 1043 1044 8 bits 1045 1046 <legal all> 1047 */ 1048 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000002c 1049 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 24 1050 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0xff000000 1051 1052 /* Description PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32 1053 1054 The low 32 bits of the 40 bits pointer pointed to the 1055 external RTT channel information buffer 1056 1057 1058 1059 32 bits 1060 1061 <legal all> 1062 */ 1063 #define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000030 1064 #define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 1065 #define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff 1066 1067 /* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT 1068 1069 CFO measurement. Needed for passive locationing 1070 1071 1072 1073 14 bits, signed 1.13. 13 bits fraction to provide a 1074 resolution of 153 Hz 1075 1076 1077 1078 In units of cycles/800 ns 1079 1080 <legal all> 1081 */ 1082 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x00000034 1083 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0 1084 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x00003fff 1085 1086 /* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD 1087 1088 Channel delay spread measurement. Needed for selecting 1089 GI length 1090 1091 1092 1093 8 bits, unsigned. At 25 ns step. Can represent up to 1094 6375 ns 1095 1096 1097 1098 In units of cycles @ 40 MHz 1099 1100 <legal all> 1101 */ 1102 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_OFFSET 0x00000034 1103 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_LSB 14 1104 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_MASK 0x003fc000 1105 1106 /* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL 1107 1108 Indicate which timing backoff value is used 1109 1110 1111 1112 <enum 0 timing_backoff_low_rssi> 1113 1114 <enum 1 timing_backoff_mid_rssi> 1115 1116 <enum 2 timing_backoff_high_rssi> 1117 1118 <enum 3 reserved> 1119 1120 <legal all> 1121 */ 1122 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000034 1123 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 22 1124 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x00c00000 1125 1126 /* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8 1127 1128 <legal 0> 1129 */ 1130 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_OFFSET 0x00000034 1131 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_LSB 24 1132 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_MASK 0x7f000000 1133 1134 /* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID 1135 1136 <enum 0 rx_location_info_is_not_valid> 1137 1138 <enum 1 rx_location_info_is_valid> 1139 1140 <legal all> 1141 */ 1142 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x00000034 1143 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 31 1144 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x80000000 1145 1146 /* EXTERNAL REFERENCE : struct rx_timing_offset_info rx_timing_offset_info_details */ 1147 1148 1149 /* Description PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET 1150 1151 Cumulative reference frequency error at end of RX 1152 1153 <legal all> 1154 */ 1155 #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000038 1156 #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0 1157 #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff 1158 1159 /* Description PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED 1160 1161 <legal 0> 1162 */ 1163 #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x00000038 1164 #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 12 1165 #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff000 1166 1167 /* EXTERNAL REFERENCE : struct receive_rssi_info post_rssi_info_details */ 1168 1169 1170 /* Description PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0 1171 1172 RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. 1173 1174 Value of 0x80 indicates invalid. 1175 */ 1176 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000003c 1177 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 1178 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff 1179 1180 /* Description PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0 1181 1182 RSSI of RX PPDU on chain 0 of extension 20 MHz 1183 bandwidth. 1184 1185 Value of 0x80 indicates invalid. 1186 */ 1187 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000003c 1188 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 1189 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 1190 1191 /* Description PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0 1192 1193 RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz 1194 bandwidth. 1195 1196 Value of 0x80 indicates invalid. 1197 */ 1198 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000003c 1199 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 1200 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 1201 1202 /* Description PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0 1203 1204 RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz 1205 bandwidth. 1206 1207 Value of 0x80 indicates invalid. 1208 */ 1209 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000003c 1210 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 1211 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 1212 1213 /* Description PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0 1214 1215 RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz 1216 bandwidth. 1217 1218 Value of 0x80 indicates invalid. 1219 */ 1220 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000040 1221 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 1222 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff 1223 1224 /* Description PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0 1225 1226 RSSI of RX PPDU on chain 0 of extension 80, low-high 20 1227 MHz bandwidth. 1228 1229 Value of 0x80 indicates invalid. 1230 */ 1231 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000040 1232 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 1233 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 1234 1235 /* Description PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0 1236 1237 RSSI of RX PPDU on chain 0 of extension 80, high-low 20 1238 MHz bandwidth. 1239 1240 Value of 0x80 indicates invalid. 1241 */ 1242 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000040 1243 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 1244 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 1245 1246 /* Description PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0 1247 1248 RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz 1249 bandwidth. 1250 1251 Value of 0x80 indicates invalid. 1252 */ 1253 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000040 1254 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 1255 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 1256 1257 /* Description PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1 1258 1259 RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. 1260 1261 Value of 0x80 indicates invalid. 1262 */ 1263 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000044 1264 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 1265 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff 1266 1267 /* Description PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1 1268 1269 RSSI of RX PPDU on chain 1 of extension 20 MHz 1270 bandwidth. 1271 1272 Value of 0x80 indicates invalid. 1273 */ 1274 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000044 1275 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 1276 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 1277 1278 /* Description PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1 1279 1280 RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz 1281 bandwidth. 1282 1283 Value of 0x80 indicates invalid. 1284 */ 1285 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000044 1286 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 1287 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 1288 1289 /* Description PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1 1290 1291 RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz 1292 bandwidth. 1293 1294 Value of 0x80 indicates invalid. 1295 */ 1296 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000044 1297 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 1298 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 1299 1300 /* Description PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1 1301 1302 RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz 1303 bandwidth. 1304 1305 Value of 0x80 indicates invalid. 1306 */ 1307 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000048 1308 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 1309 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff 1310 1311 /* Description PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1 1312 1313 RSSI of RX PPDU on chain 1 of extension 80, low-high 20 1314 MHz bandwidth. 1315 1316 Value of 0x80 indicates invalid. 1317 */ 1318 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000048 1319 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 1320 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 1321 1322 /* Description PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1 1323 1324 RSSI of RX PPDU on chain 1 of extension 80, high-low 20 1325 MHz bandwidth. 1326 1327 Value of 0x80 indicates invalid. 1328 */ 1329 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000048 1330 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 1331 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 1332 1333 /* Description PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1 1334 1335 RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz 1336 bandwidth. 1337 1338 Value of 0x80 indicates invalid. 1339 */ 1340 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000048 1341 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 1342 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 1343 1344 /* Description PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2 1345 1346 RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. 1347 1348 Value of 0x80 indicates invalid. 1349 */ 1350 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000004c 1351 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 1352 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff 1353 1354 /* Description PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2 1355 1356 RSSI of RX PPDU on chain 2 of extension 20 MHz 1357 bandwidth. 1358 1359 Value of 0x80 indicates invalid. 1360 */ 1361 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000004c 1362 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 1363 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 1364 1365 /* Description PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2 1366 1367 RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz 1368 bandwidth. 1369 1370 Value of 0x80 indicates invalid. 1371 */ 1372 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000004c 1373 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 1374 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 1375 1376 /* Description PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2 1377 1378 RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz 1379 bandwidth. 1380 1381 Value of 0x80 indicates invalid. 1382 */ 1383 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000004c 1384 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 1385 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 1386 1387 /* Description PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2 1388 1389 RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz 1390 bandwidth. 1391 1392 Value of 0x80 indicates invalid. 1393 */ 1394 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000050 1395 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 1396 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff 1397 1398 /* Description PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2 1399 1400 RSSI of RX PPDU on chain 2 of extension 80, low-high 20 1401 MHz bandwidth. 1402 1403 Value of 0x80 indicates invalid. 1404 */ 1405 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000050 1406 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 1407 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 1408 1409 /* Description PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2 1410 1411 RSSI of RX PPDU on chain 2 of extension 80, high-low 20 1412 MHz bandwidth. 1413 1414 Value of 0x80 indicates invalid. 1415 */ 1416 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000050 1417 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 1418 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 1419 1420 /* Description PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2 1421 1422 RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz 1423 bandwidth. 1424 1425 Value of 0x80 indicates invalid. 1426 */ 1427 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000050 1428 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 1429 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 1430 1431 /* Description PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3 1432 1433 RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. 1434 1435 Value of 0x80 indicates invalid. 1436 */ 1437 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000054 1438 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 1439 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff 1440 1441 /* Description PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3 1442 1443 RSSI of RX PPDU on chain 3 of extension 20 MHz 1444 bandwidth. 1445 1446 Value of 0x80 indicates invalid. 1447 */ 1448 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000054 1449 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 1450 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 1451 1452 /* Description PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3 1453 1454 RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz 1455 bandwidth. 1456 1457 Value of 0x80 indicates invalid. 1458 */ 1459 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000054 1460 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 1461 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 1462 1463 /* Description PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3 1464 1465 RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz 1466 bandwidth. 1467 1468 Value of 0x80 indicates invalid. 1469 */ 1470 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000054 1471 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 1472 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 1473 1474 /* Description PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3 1475 1476 RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz 1477 bandwidth. 1478 1479 Value of 0x80 indicates invalid. 1480 */ 1481 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000058 1482 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 1483 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff 1484 1485 /* Description PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3 1486 1487 RSSI of RX PPDU on chain 3 of extension 80, low-high 20 1488 MHz bandwidth. 1489 1490 Value of 0x80 indicates invalid. 1491 */ 1492 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000058 1493 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 1494 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 1495 1496 /* Description PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3 1497 1498 RSSI of RX PPDU on chain 3 of extension 80, high-low 20 1499 MHz bandwidth. 1500 1501 Value of 0x80 indicates invalid. 1502 */ 1503 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000058 1504 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 1505 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 1506 1507 /* Description PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3 1508 1509 RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz 1510 bandwidth. 1511 1512 Value of 0x80 indicates invalid. 1513 */ 1514 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000058 1515 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 1516 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 1517 1518 /* Description PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4 1519 1520 RSSI of RX PPDU on chain 4 of primary 20 MHz bandwidth. 1521 1522 Value of 0x80 indicates invalid. 1523 */ 1524 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000005c 1525 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0 1526 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff 1527 1528 /* Description PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4 1529 1530 RSSI of RX PPDU on chain 4 of extension 20 MHz 1531 bandwidth. 1532 1533 Value of 0x80 indicates invalid. 1534 */ 1535 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000005c 1536 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8 1537 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00 1538 1539 /* Description PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4 1540 1541 RSSI of RX PPDU on chain 4 of extension 40, low 20 MHz 1542 bandwidth. 1543 1544 Value of 0x80 indicates invalid. 1545 */ 1546 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000005c 1547 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16 1548 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000 1549 1550 /* Description PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4 1551 1552 RSSI of RX PPDU on chain 4 of extension 40, high 20 MHz 1553 bandwidth. 1554 1555 Value of 0x80 indicates invalid. 1556 */ 1557 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000005c 1558 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24 1559 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000 1560 1561 /* Description PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4 1562 1563 RSSI of RX PPDU on chain 4 of extension 80, low 20 MHz 1564 bandwidth. 1565 1566 Value of 0x80 indicates invalid. 1567 */ 1568 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000060 1569 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0 1570 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff 1571 1572 /* Description PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4 1573 1574 RSSI of RX PPDU on chain 4 of extension 80, low-high 20 1575 MHz bandwidth. 1576 1577 Value of 0x80 indicates invalid. 1578 */ 1579 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000060 1580 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8 1581 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00 1582 1583 /* Description PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4 1584 1585 RSSI of RX PPDU on chain 4 of extension 80, high-low 20 1586 MHz bandwidth. 1587 1588 Value of 0x80 indicates invalid. 1589 */ 1590 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000060 1591 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16 1592 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000 1593 1594 /* Description PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4 1595 1596 RSSI of RX PPDU on chain 4 of extension 80, high 20 MHz 1597 bandwidth. 1598 1599 Value of 0x80 indicates invalid. 1600 */ 1601 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000060 1602 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24 1603 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000 1604 1605 /* Description PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5 1606 1607 RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. 1608 1609 Value of 0x80 indicates invalid. 1610 */ 1611 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000064 1612 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0 1613 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff 1614 1615 /* Description PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5 1616 1617 RSSI of RX PPDU on chain 5 of extension 20 MHz 1618 bandwidth. 1619 1620 Value of 0x80 indicates invalid. 1621 */ 1622 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000064 1623 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8 1624 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00 1625 1626 /* Description PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5 1627 1628 RSSI of RX PPDU on chain 5 of extension 40, low 20 MHz 1629 bandwidth. 1630 1631 Value of 0x80 indicates invalid. 1632 */ 1633 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000064 1634 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16 1635 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000 1636 1637 /* Description PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5 1638 1639 RSSI of RX PPDU on chain 5 of extension 40, high 20 MHz 1640 bandwidth. 1641 1642 Value of 0x80 indicates invalid. 1643 */ 1644 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000064 1645 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24 1646 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000 1647 1648 /* Description PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5 1649 1650 RSSI of RX PPDU on chain 5 of extension 80, low 20 MHz 1651 bandwidth. 1652 1653 Value of 0x80 indicates invalid. 1654 */ 1655 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000068 1656 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0 1657 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff 1658 1659 /* Description PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5 1660 1661 RSSI of RX PPDU on chain 5 of extension 80, low-high 20 1662 MHz bandwidth. 1663 1664 Value of 0x80 indicates invalid. 1665 */ 1666 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000068 1667 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8 1668 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00 1669 1670 /* Description PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5 1671 1672 RSSI of RX PPDU on chain 5 of extension 80, high-low 20 1673 MHz bandwidth. 1674 1675 Value of 0x80 indicates invalid. 1676 */ 1677 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000068 1678 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16 1679 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000 1680 1681 /* Description PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5 1682 1683 RSSI of RX PPDU on chain 5 of extension 80, high 20 MHz 1684 bandwidth. 1685 1686 Value of 0x80 indicates invalid. 1687 */ 1688 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000068 1689 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24 1690 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000 1691 1692 /* Description PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6 1693 1694 RSSI of RX PPDU on chain 6 of primary 20 MHz bandwidth. 1695 1696 Value of 0x80 indicates invalid. 1697 */ 1698 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000006c 1699 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0 1700 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff 1701 1702 /* Description PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6 1703 1704 RSSI of RX PPDU on chain 6 of extension 20 MHz 1705 bandwidth. 1706 1707 Value of 0x80 indicates invalid. 1708 */ 1709 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000006c 1710 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8 1711 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00 1712 1713 /* Description PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6 1714 1715 RSSI of RX PPDU on chain 6 of extension 40, low 20 MHz 1716 bandwidth. 1717 1718 Value of 0x80 indicates invalid. 1719 */ 1720 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000006c 1721 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16 1722 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000 1723 1724 /* Description PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6 1725 1726 RSSI of RX PPDU on chain 6 of extension 40, high 20 MHz 1727 bandwidth. 1728 1729 Value of 0x80 indicates invalid. 1730 */ 1731 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000006c 1732 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24 1733 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000 1734 1735 /* Description PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6 1736 1737 RSSI of RX PPDU on chain 6 of extension 80, low 20 MHz 1738 bandwidth. 1739 1740 Value of 0x80 indicates invalid. 1741 */ 1742 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000070 1743 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0 1744 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff 1745 1746 /* Description PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6 1747 1748 RSSI of RX PPDU on chain 6 of extension 80, low-high 20 1749 MHz bandwidth. 1750 1751 Value of 0x80 indicates invalid. 1752 */ 1753 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000070 1754 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8 1755 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00 1756 1757 /* Description PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6 1758 1759 RSSI of RX PPDU on chain 6 of extension 80, high-low 20 1760 MHz bandwidth. 1761 1762 Value of 0x80 indicates invalid. 1763 */ 1764 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000070 1765 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16 1766 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000 1767 1768 /* Description PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6 1769 1770 RSSI of RX PPDU on chain 6 of extension 80, high 20 MHz 1771 bandwidth. 1772 1773 Value of 0x80 indicates invalid. 1774 */ 1775 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000070 1776 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24 1777 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000 1778 1779 /* Description PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7 1780 1781 RSSI of RX PPDU on chain 7 of primary 20 MHz bandwidth. 1782 1783 Value of 0x80 indicates invalid. 1784 */ 1785 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000074 1786 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0 1787 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff 1788 1789 /* Description PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7 1790 1791 RSSI of RX PPDU on chain 7 of extension 20 MHz 1792 bandwidth. 1793 1794 Value of 0x80 indicates invalid. 1795 */ 1796 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000074 1797 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8 1798 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00 1799 1800 /* Description PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7 1801 1802 RSSI of RX PPDU on chain 7 of extension 40, low 20 MHz 1803 bandwidth. 1804 1805 Value of 0x80 indicates invalid. 1806 */ 1807 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000074 1808 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16 1809 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000 1810 1811 /* Description PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7 1812 1813 RSSI of RX PPDU on chain 7 of extension 40, high 20 MHz 1814 bandwidth. 1815 1816 Value of 0x80 indicates invalid. 1817 */ 1818 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000074 1819 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24 1820 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000 1821 1822 /* Description PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7 1823 1824 RSSI of RX PPDU on chain 7 of extension 80, low 20 MHz 1825 bandwidth. 1826 1827 Value of 0x80 indicates invalid. 1828 */ 1829 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000078 1830 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0 1831 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff 1832 1833 /* Description PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7 1834 1835 RSSI of RX PPDU on chain 7 of extension 80, low-high 20 1836 MHz bandwidth. 1837 1838 Value of 0x80 indicates invalid. 1839 */ 1840 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000078 1841 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8 1842 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00 1843 1844 /* Description PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7 1845 1846 RSSI of RX PPDU on chain 7 of extension 80, high-low 20 1847 MHz bandwidth. 1848 1849 Value of 0x80 indicates invalid. 1850 */ 1851 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000078 1852 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16 1853 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000 1854 1855 /* Description PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7 1856 1857 RSSI of RX PPDU on chain 7 of extension 80, high 20 MHz 1858 bandwidth. 1859 1860 Value of 0x80 indicates invalid. 1861 */ 1862 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000078 1863 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24 1864 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000 1865 1866 /* Description PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0 1867 1868 Some PHY micro code status that can be put in here. 1869 Details of definition within SW specification 1870 1871 This field can be used for debugging, FW - SW message 1872 exchange, etc. 1873 1874 It could for example be a pointer to a DDR memory 1875 location where PHY FW put some debug info. 1876 1877 <legal all> 1878 */ 1879 #define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_OFFSET 0x0000007c 1880 #define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_LSB 0 1881 #define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_MASK 0xffffffff 1882 1883 /* Description PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32 1884 1885 Some PHY micro code status that can be put in here. 1886 Details of definition within SW specification 1887 1888 This field can be used for debugging, FW - SW message 1889 exchange, etc. 1890 1891 It could for example be a pointer to a DDR memory 1892 location where PHY FW put some debug info. 1893 1894 <legal all> 1895 */ 1896 #define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_OFFSET 0x00000080 1897 #define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_LSB 0 1898 #define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_MASK 0xffffffff 1899 1900 1901 #endif // _PHYRX_PKT_END_INFO_H_ 1902