1 /* 2 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 // $ATH_LICENSE_HW_HDR_C$ 18 // 19 // DO NOT EDIT! This file is automatically generated 20 // These definitions are tied to a particular hardware layout 21 22 23 #ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ 24 #define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ 25 #if !defined(__ASSEMBLER__) 26 #endif 27 28 #include "uniform_reo_status_header.h" 29 30 // ################ START SUMMARY ################# 31 // 32 // Dword Fields 33 // 0-1 struct uniform_reo_status_header status_header; 34 // 2 threshold_index[1:0], reserved_2[31:2] 35 // 3 link_descriptor_counter0[23:0], reserved_3[31:24] 36 // 4 link_descriptor_counter1[23:0], reserved_4[31:24] 37 // 5 link_descriptor_counter2[23:0], reserved_5[31:24] 38 // 6 link_descriptor_counter_sum[25:0], reserved_6[31:26] 39 // 7 reserved_7[31:0] 40 // 8 reserved_8[31:0] 41 // 9 reserved_9a[31:0] 42 // 10 reserved_10a[31:0] 43 // 11 reserved_11a[31:0] 44 // 12 reserved_12a[31:0] 45 // 13 reserved_13a[31:0] 46 // 14 reserved_14a[31:0] 47 // 15 reserved_15a[31:0] 48 // 16 reserved_16a[31:0] 49 // 17 reserved_17a[31:0] 50 // 18 reserved_18a[31:0] 51 // 19 reserved_19a[31:0] 52 // 20 reserved_20a[31:0] 53 // 21 reserved_21a[31:0] 54 // 22 reserved_22a[31:0] 55 // 23 reserved_23a[31:0] 56 // 24 reserved_24a[27:0], looping_count[31:28] 57 // 58 // ################ END SUMMARY ################# 59 60 #define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 25 61 62 struct reo_descriptor_threshold_reached_status { 63 struct uniform_reo_status_header status_header; 64 uint32_t threshold_index : 2, //[1:0] 65 reserved_2 : 30; //[31:2] 66 uint32_t link_descriptor_counter0 : 24, //[23:0] 67 reserved_3 : 8; //[31:24] 68 uint32_t link_descriptor_counter1 : 24, //[23:0] 69 reserved_4 : 8; //[31:24] 70 uint32_t link_descriptor_counter2 : 24, //[23:0] 71 reserved_5 : 8; //[31:24] 72 uint32_t link_descriptor_counter_sum : 26, //[25:0] 73 reserved_6 : 6; //[31:26] 74 uint32_t reserved_7 : 32; //[31:0] 75 uint32_t reserved_8 : 32; //[31:0] 76 uint32_t reserved_9a : 32; //[31:0] 77 uint32_t reserved_10a : 32; //[31:0] 78 uint32_t reserved_11a : 32; //[31:0] 79 uint32_t reserved_12a : 32; //[31:0] 80 uint32_t reserved_13a : 32; //[31:0] 81 uint32_t reserved_14a : 32; //[31:0] 82 uint32_t reserved_15a : 32; //[31:0] 83 uint32_t reserved_16a : 32; //[31:0] 84 uint32_t reserved_17a : 32; //[31:0] 85 uint32_t reserved_18a : 32; //[31:0] 86 uint32_t reserved_19a : 32; //[31:0] 87 uint32_t reserved_20a : 32; //[31:0] 88 uint32_t reserved_21a : 32; //[31:0] 89 uint32_t reserved_22a : 32; //[31:0] 90 uint32_t reserved_23a : 32; //[31:0] 91 uint32_t reserved_24a : 28, //[27:0] 92 looping_count : 4; //[31:28] 93 }; 94 95 /* 96 97 struct uniform_reo_status_header status_header 98 99 Consumer: SW 100 101 Producer: REO 102 103 104 105 Details that can link this status with the original 106 command. It also contains info on how long REO took to 107 execute this command. 108 109 threshold_index 110 111 The index of the threshold register whose value got 112 reached 113 114 115 116 <enum 0 reo_desc_counter0_threshold> 117 118 <enum 1 reo_desc_counter1_threshold> 119 120 <enum 2 reo_desc_counter2_threshold> 121 122 <enum 3 reo_desc_counter_sum_threshold> 123 124 125 126 <legal all> 127 128 reserved_2 129 130 <legal 0> 131 132 link_descriptor_counter0 133 134 Value of this counter at generation of this message 135 136 <legal all> 137 138 reserved_3 139 140 <legal 0> 141 142 link_descriptor_counter1 143 144 Value of this counter at generation of this message 145 146 <legal all> 147 148 reserved_4 149 150 <legal 0> 151 152 link_descriptor_counter2 153 154 Value of this counter at generation of this message 155 156 <legal all> 157 158 reserved_5 159 160 <legal 0> 161 162 link_descriptor_counter_sum 163 164 Value of this counter at generation of this message 165 166 <legal all> 167 168 reserved_6 169 170 <legal 0> 171 172 reserved_7 173 174 <legal 0> 175 176 reserved_8 177 178 <legal 0> 179 180 reserved_9a 181 182 <legal 0> 183 184 reserved_10a 185 186 <legal 0> 187 188 reserved_11a 189 190 <legal 0> 191 192 reserved_12a 193 194 <legal 0> 195 196 reserved_13a 197 198 <legal 0> 199 200 reserved_14a 201 202 <legal 0> 203 204 reserved_15a 205 206 <legal 0> 207 208 reserved_16a 209 210 <legal 0> 211 212 reserved_17a 213 214 <legal 0> 215 216 reserved_18a 217 218 <legal 0> 219 220 reserved_19a 221 222 <legal 0> 223 224 reserved_20a 225 226 <legal 0> 227 228 reserved_21a 229 230 <legal 0> 231 232 reserved_22a 233 234 <legal 0> 235 236 reserved_23a 237 238 <legal 0> 239 240 reserved_24a 241 242 <legal 0> 243 244 looping_count 245 246 A count value that indicates the number of times the 247 producer of entries into this Ring has looped around the 248 ring. 249 250 At initialization time, this value is set to 0. On the 251 first loop, this value is set to 1. After the max value is 252 reached allowed by the number of bits for this field, the 253 count value continues with 0 again. 254 255 256 257 In case SW is the consumer of the ring entries, it can 258 use this field to figure out up to where the producer of 259 entries has created new entries. This eliminates the need to 260 check where the head pointer' of the ring is located once 261 the SW starts processing an interrupt indicating that new 262 entries have been put into this ring... 263 264 265 266 Also note that SW if it wants only needs to look at the 267 LSB bit of this count value. 268 269 <legal all> 270 */ 271 272 273 /* EXTERNAL REFERENCE : struct uniform_reo_status_header status_header */ 274 275 276 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER 277 278 Consumer: SW , DEBUG 279 280 Producer: REO 281 282 283 284 The value in this field is equal to value of the 285 'REO_CMD_Number' field the REO command 286 287 288 289 This field helps to correlate the statuses with the REO 290 commands. 291 292 293 294 <legal all> 295 */ 296 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 297 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 298 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff 299 300 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME 301 302 Consumer: DEBUG 303 304 Producer: REO 305 306 307 308 The amount of time REO took to excecute the command. 309 Note that this time does not include the duration of the 310 command waiting in the command ring, before the execution 311 started. 312 313 314 315 In us. 316 317 318 319 <legal all> 320 */ 321 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 322 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 323 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 324 325 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS 326 327 Consumer: DEBUG 328 329 Producer: REO 330 331 332 333 Execution status of the command. 334 335 336 337 <enum 0 reo_successful_execution> Command has 338 successfully be executed 339 340 <enum 1 reo_blocked_execution> Command could not be 341 executed as the queue or cache was blocked 342 343 <enum 2 reo_failed_execution> Command has encountered 344 problems when executing, like the queue descriptor not being 345 valid. None of the status fields in the entire STATUS TLV 346 are valid. 347 348 <enum 3 reo_resource_blocked> Command is NOT executed 349 because one or more descriptors were blocked. This is SW 350 programming mistake. 351 352 None of the status fields in the entire STATUS TLV are 353 valid. 354 355 356 357 <legal 0-3> 358 */ 359 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 360 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 361 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 362 363 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_RESERVED_0A 364 365 <legal 0> 366 */ 367 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 368 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28 369 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 370 371 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_STATUS_HEADER_TIMESTAMP 372 373 Timestamp at the moment that this status report is 374 written. 375 376 377 378 <legal all> 379 */ 380 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 381 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0 382 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff 383 384 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX 385 386 The index of the threshold register whose value got 387 reached 388 389 390 391 <enum 0 reo_desc_counter0_threshold> 392 393 <enum 1 reo_desc_counter1_threshold> 394 395 <enum 2 reo_desc_counter2_threshold> 396 397 <enum 3 reo_desc_counter_sum_threshold> 398 399 400 401 <legal all> 402 */ 403 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_OFFSET 0x00000008 404 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_LSB 0 405 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_MASK 0x00000003 406 407 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2 408 409 <legal 0> 410 */ 411 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_OFFSET 0x00000008 412 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_LSB 2 413 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_MASK 0xfffffffc 414 415 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0 416 417 Value of this counter at generation of this message 418 419 <legal all> 420 */ 421 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_OFFSET 0x0000000c 422 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_LSB 0 423 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_MASK 0x00ffffff 424 425 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3 426 427 <legal 0> 428 */ 429 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_OFFSET 0x0000000c 430 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_LSB 24 431 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_MASK 0xff000000 432 433 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1 434 435 Value of this counter at generation of this message 436 437 <legal all> 438 */ 439 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_OFFSET 0x00000010 440 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_LSB 0 441 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_MASK 0x00ffffff 442 443 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4 444 445 <legal 0> 446 */ 447 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_OFFSET 0x00000010 448 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_LSB 24 449 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_MASK 0xff000000 450 451 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2 452 453 Value of this counter at generation of this message 454 455 <legal all> 456 */ 457 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_OFFSET 0x00000014 458 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_LSB 0 459 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_MASK 0x00ffffff 460 461 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5 462 463 <legal 0> 464 */ 465 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_OFFSET 0x00000014 466 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_LSB 24 467 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_MASK 0xff000000 468 469 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM 470 471 Value of this counter at generation of this message 472 473 <legal all> 474 */ 475 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET 0x00000018 476 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_LSB 0 477 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_MASK 0x03ffffff 478 479 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6 480 481 <legal 0> 482 */ 483 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_OFFSET 0x00000018 484 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_LSB 26 485 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_MASK 0xfc000000 486 487 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7 488 489 <legal 0> 490 */ 491 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_OFFSET 0x0000001c 492 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_LSB 0 493 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_MASK 0xffffffff 494 495 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8 496 497 <legal 0> 498 */ 499 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_OFFSET 0x00000020 500 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_LSB 0 501 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_MASK 0xffffffff 502 503 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A 504 505 <legal 0> 506 */ 507 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_OFFSET 0x00000024 508 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_LSB 0 509 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_MASK 0xffffffff 510 511 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A 512 513 <legal 0> 514 */ 515 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_OFFSET 0x00000028 516 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_LSB 0 517 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_MASK 0xffffffff 518 519 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A 520 521 <legal 0> 522 */ 523 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_OFFSET 0x0000002c 524 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_LSB 0 525 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_MASK 0xffffffff 526 527 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A 528 529 <legal 0> 530 */ 531 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_OFFSET 0x00000030 532 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_LSB 0 533 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_MASK 0xffffffff 534 535 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A 536 537 <legal 0> 538 */ 539 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_OFFSET 0x00000034 540 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_LSB 0 541 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_MASK 0xffffffff 542 543 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A 544 545 <legal 0> 546 */ 547 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_OFFSET 0x00000038 548 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_LSB 0 549 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_MASK 0xffffffff 550 551 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A 552 553 <legal 0> 554 */ 555 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_OFFSET 0x0000003c 556 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_LSB 0 557 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_MASK 0xffffffff 558 559 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A 560 561 <legal 0> 562 */ 563 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_OFFSET 0x00000040 564 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_LSB 0 565 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_MASK 0xffffffff 566 567 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A 568 569 <legal 0> 570 */ 571 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_OFFSET 0x00000044 572 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_LSB 0 573 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_MASK 0xffffffff 574 575 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A 576 577 <legal 0> 578 */ 579 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_OFFSET 0x00000048 580 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_LSB 0 581 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_MASK 0xffffffff 582 583 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A 584 585 <legal 0> 586 */ 587 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_OFFSET 0x0000004c 588 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_LSB 0 589 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_MASK 0xffffffff 590 591 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A 592 593 <legal 0> 594 */ 595 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_OFFSET 0x00000050 596 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_LSB 0 597 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_MASK 0xffffffff 598 599 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A 600 601 <legal 0> 602 */ 603 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_OFFSET 0x00000054 604 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_LSB 0 605 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_MASK 0xffffffff 606 607 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A 608 609 <legal 0> 610 */ 611 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_OFFSET 0x00000058 612 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_LSB 0 613 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_MASK 0xffffffff 614 615 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A 616 617 <legal 0> 618 */ 619 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_OFFSET 0x0000005c 620 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_LSB 0 621 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_MASK 0xffffffff 622 623 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A 624 625 <legal 0> 626 */ 627 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_OFFSET 0x00000060 628 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_LSB 0 629 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_MASK 0x0fffffff 630 631 /* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT 632 633 A count value that indicates the number of times the 634 producer of entries into this Ring has looped around the 635 ring. 636 637 At initialization time, this value is set to 0. On the 638 first loop, this value is set to 1. After the max value is 639 reached allowed by the number of bits for this field, the 640 count value continues with 0 again. 641 642 643 644 In case SW is the consumer of the ring entries, it can 645 use this field to figure out up to where the producer of 646 entries has created new entries. This eliminates the need to 647 check where the head pointer' of the ring is located once 648 the SW starts processing an interrupt indicating that new 649 entries have been put into this ring... 650 651 652 653 Also note that SW if it wants only needs to look at the 654 LSB bit of this count value. 655 656 <legal all> 657 */ 658 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 659 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_LSB 28 660 #define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 661 662 663 #endif // _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ 664