1 /* 2 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 // $ATH_LICENSE_HW_HDR_C$ 18 // 19 // DO NOT EDIT! This file is automatically generated 20 // These definitions are tied to a particular hardware layout 21 22 23 #ifndef _REO_DESTINATION_RING_H_ 24 #define _REO_DESTINATION_RING_H_ 25 #if !defined(__ASSEMBLER__) 26 #endif 27 28 #include "buffer_addr_info.h" 29 #include "rx_mpdu_desc_info.h" 30 #include "rx_msdu_desc_info.h" 31 32 // ################ START SUMMARY ################# 33 // 34 // Dword Fields 35 // 0-1 struct buffer_addr_info buf_or_link_desc_addr_info; 36 // 2-3 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 37 // 4-5 struct rx_msdu_desc_info rx_msdu_desc_info_details; 38 // 6 rx_reo_queue_desc_addr_31_0[31:0] 39 // 7 rx_reo_queue_desc_addr_39_32[7:0], reo_dest_buffer_type[8], reo_push_reason[10:9], reo_error_code[15:11], receive_queue_number[31:16] 40 // 8 soft_reorder_info_valid[0], reorder_opcode[4:1], reorder_slot_index[12:5], mpdu_fragment_number[16:13], reserved_8a[31:17] 41 // 9 reserved_9a[31:0] 42 // 10 reserved_10a[31:0] 43 // 11 reserved_11a[31:0] 44 // 12 reserved_12a[31:0] 45 // 13 reserved_13a[31:0] 46 // 14 reserved_14a[31:0] 47 // 15 reserved_15[19:0], ring_id[27:20], looping_count[31:28] 48 // 49 // ################ END SUMMARY ################# 50 51 #define NUM_OF_DWORDS_REO_DESTINATION_RING 16 52 53 struct reo_destination_ring { 54 struct buffer_addr_info buf_or_link_desc_addr_info; 55 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 56 struct rx_msdu_desc_info rx_msdu_desc_info_details; 57 uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] 58 uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] 59 reo_dest_buffer_type : 1, //[8] 60 reo_push_reason : 2, //[10:9] 61 reo_error_code : 5, //[15:11] 62 receive_queue_number : 16; //[31:16] 63 uint32_t soft_reorder_info_valid : 1, //[0] 64 reorder_opcode : 4, //[4:1] 65 reorder_slot_index : 8, //[12:5] 66 mpdu_fragment_number : 4, //[16:13] 67 reserved_8a : 15; //[31:17] 68 uint32_t reserved_9a : 32; //[31:0] 69 uint32_t reserved_10a : 32; //[31:0] 70 uint32_t reserved_11a : 32; //[31:0] 71 uint32_t reserved_12a : 32; //[31:0] 72 uint32_t reserved_13a : 32; //[31:0] 73 uint32_t reserved_14a : 32; //[31:0] 74 uint32_t reserved_15 : 20, //[19:0] 75 ring_id : 8, //[27:20] 76 looping_count : 4; //[31:28] 77 }; 78 79 /* 80 81 struct buffer_addr_info buf_or_link_desc_addr_info 82 83 Consumer: REO/SW/FW 84 85 Producer: RXDMA 86 87 88 89 Details of the physical address of the a buffer or MSDU 90 link descriptor 91 92 struct rx_mpdu_desc_info rx_mpdu_desc_info_details 93 94 Consumer: REO/SW/FW 95 96 Producer: RXDMA 97 98 99 100 General information related to the MPDU that is passed 101 on from REO entrance ring to the REO destination ring 102 103 struct rx_msdu_desc_info rx_msdu_desc_info_details 104 105 General information related to the MSDU that is passed 106 on from RXDMA all the way to to the REO destination ring. 107 108 rx_reo_queue_desc_addr_31_0 109 110 Consumer: REO 111 112 Producer: RXDMA 113 114 115 116 Address (lower 32 bits) of the REO queue descriptor. 117 118 <legal all> 119 120 rx_reo_queue_desc_addr_39_32 121 122 Consumer: REO 123 124 Producer: RXDMA 125 126 127 128 Address (upper 8 bits) of the REO queue descriptor. 129 130 <legal all> 131 132 reo_dest_buffer_type 133 134 Indicates the type of address provided in the 135 'Buf_or_link_desc_addr_info' 136 137 138 139 <enum 0 MSDU_buf_address> The address of an MSDU buffer 140 141 <enum 1 MSDU_link_desc_address> The address of the MSDU 142 link descriptor. 143 144 145 146 <legal all> 147 148 reo_push_reason 149 150 Indicates why REO pushed the frame to this exit ring 151 152 153 154 <enum 0 reo_error_detected> Reo detected an error an 155 pushed this frame to this queue 156 157 <enum 1 reo_routing_instruction> Reo pushed the frame to 158 this queue per received routing instructions. No error 159 within REO was detected 160 161 162 163 164 165 <legal 0 - 1> 166 167 reo_error_code 168 169 Field only valid when 'Reo_push_reason' set to 170 'reo_error_detected'. 171 172 173 174 <enum 0 reo_queue_desc_addr_zero> Reo queue descriptor 175 provided in the REO_ENTRANCE ring is set to 0 176 177 <enum 1 reo_queue_desc_not_valid> Reo queue descriptor 178 valid bit is NOT set 179 180 <enum 2 ampdu_in_non_ba> AMPDU frame received without BA 181 session having been setup. 182 183 <enum 3 non_ba_duplicate> Non-BA session, SN equal to 184 SSN, Retry bit set: duplicate frame 185 186 <enum 4 ba_duplicate> BA session, duplicate frame 187 188 <enum 5 regular_frame_2k_jump> A normal (management/data 189 frame) received with 2K jump in SN 190 191 <enum 6 bar_frame_2k_jump> A bar received with 2K jump 192 in SSN 193 194 <enum 7 regular_frame_OOR> A normal (management/data 195 frame) received with SN falling within the OOR window 196 197 <enum 8 bar_frame_OOR> A bar received with SSN falling 198 within the OOR window 199 200 <enum 9 bar_frame_no_ba_session> A bar received without 201 a BA session 202 203 <enum 10 bar_frame_sn_equals_ssn> A bar received with 204 SSN equal to SN 205 206 <enum 11 pn_check_failed> PN Check Failed packet. 207 208 <enum 12 2k_error_handling_flag_set> Frame is forwarded 209 as a result of the 'Seq_2k_error_detected_flag' been set in 210 the REO Queue descriptor 211 212 <enum 13 pn_error_handling_flag_set> Frame is forwarded 213 as a result of the 'pn_error_detected_flag' been set in the 214 REO Queue descriptor 215 216 <enum 14 queue_descriptor_blocked_set> Frame is 217 forwarded as a result of the queue descriptor(address) being 218 blocked as SW/FW seems to be currently in the process of 219 making updates to this descriptor... 220 221 222 223 <legal 0-14> 224 225 receive_queue_number 226 227 This field indicates the REO MPDU reorder queue ID from 228 which this frame originated. This field is populated from a 229 field with the same name in the RX_REO_QUEUE descriptor. 230 231 <legal all> 232 233 soft_reorder_info_valid 234 235 When set, REO has been instructed to not perform the 236 actual re-ordering of frames for this queue, but just to 237 insert the reorder opcodes 238 239 <legal all> 240 241 reorder_opcode 242 243 Field is valid when 'Soft_reorder_info_valid' is set. 244 This field is always valid for debug purpose as well. 245 246 Details are in the MLD. 247 248 249 250 <enum 0 invalid> 251 252 <enum 1 fwdcur_fwdbuf> 253 254 <enum 2 fwdbuf_fwdcur> 255 256 <enum 3 qcur> 257 258 <enum 4 fwdbuf_qcur> 259 260 <enum 5 fwdbuf_drop> 261 262 <enum 6 fwdall_drop> 263 264 <enum 7 fwdall_qcur> 265 266 <enum 8 reserved_reo_opcode_1> 267 268 <enum 9 dropcur> the error reason code is in 269 reo_error_code field. 270 271 <enum 10 reserved_reo_opcode_2> 272 273 <enum 11 reserved_reo_opcode_3> 274 275 <enum 12 reserved_reo_opcode_4> 276 277 <enum 13 reserved_reo_opcode_5> 278 279 <enum 14 reserved_reo_opcode_6> 280 281 <enum 15 reserved_reo_opcode_7> 282 283 284 285 <legal all> 286 287 reorder_slot_index 288 289 Field only valid when 'Soft_reorder_info_valid' is set. 290 291 292 293 TODO: add description 294 295 296 297 <legal all> 298 299 mpdu_fragment_number 300 301 Field only valid when Rx_mpdu_desc_info_details. 302 303 Fragment_flag is set. 304 305 306 307 The fragment number from the 802.11 header. 308 309 310 311 Note that the sequence number is embedded in field: 312 Rx_mpdu_desc_info_details. 313 314 Mpdu_Sequence_number 315 316 <legal all> 317 318 reserved_8a 319 320 <legal 0> 321 322 reserved_9a 323 324 <legal 0> 325 326 reserved_10a 327 328 <legal 0> 329 330 reserved_11a 331 332 <legal 0> 333 334 reserved_12a 335 336 <legal 0> 337 338 reserved_13a 339 340 <legal 0> 341 342 reserved_14a 343 344 <legal 0> 345 346 reserved_15 347 348 <legal 0> 349 350 ring_id 351 352 The buffer pointer ring ID. 353 354 0 refers to the IDLE ring 355 356 1 - N refers to other rings 357 358 359 360 Helps with debugging when dumping ring contents. 361 362 <legal all> 363 364 looping_count 365 366 A count value that indicates the number of times the 367 producer of entries into this Ring has looped around the 368 ring. 369 370 At initialization time, this value is set to 0. On the 371 first loop, this value is set to 1. After the max value is 372 reached allowed by the number of bits for this field, the 373 count value continues with 0 again. 374 375 In case SW is the consumer of the ring entries, it can 376 use this field to figure out up to where the producer of 377 entries has created new entries. This eliminates the need to 378 check where the head pointer' of the ring is located once 379 the SW starts processing an interrupt indicating that new 380 entries have been put into this ring... 381 382 383 384 Also note that SW if it wants only needs to look at the 385 LSB bit of this count value. 386 387 <legal all> 388 */ 389 390 391 /* EXTERNAL REFERENCE : struct buffer_addr_info buf_or_link_desc_addr_info */ 392 393 394 /* Description REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 395 396 Address (lower 32 bits) of the MSDU buffer OR 397 MSDU_EXTENSION descriptor OR Link Descriptor 398 399 400 401 In case of 'NULL' pointer, this field is set to 0 402 403 <legal all> 404 */ 405 #define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 406 #define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 407 #define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 408 409 /* Description REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 410 411 Address (upper 8 bits) of the MSDU buffer OR 412 MSDU_EXTENSION descriptor OR Link Descriptor 413 414 415 416 In case of 'NULL' pointer, this field is set to 0 417 418 <legal all> 419 */ 420 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 421 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 422 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 423 424 /* Description REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 425 426 Consumer: WBM 427 428 Producer: SW/FW 429 430 431 432 In case of 'NULL' pointer, this field is set to 0 433 434 435 436 Indicates to which buffer manager the buffer OR 437 MSDU_EXTENSION descriptor OR link descriptor that is being 438 pointed to shall be returned after the frame has been 439 processed. It is used by WBM for routing purposes. 440 441 442 443 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 444 to the WMB buffer idle list 445 446 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 447 returned to the WMB idle link descriptor idle list 448 449 <enum 2 FW_BM> This buffer shall be returned to the FW 450 451 <enum 3 SW0_BM> This buffer shall be returned to the SW, 452 ring 0 453 454 <enum 4 SW1_BM> This buffer shall be returned to the SW, 455 ring 1 456 457 <enum 5 SW2_BM> This buffer shall be returned to the SW, 458 ring 2 459 460 <enum 6 SW3_BM> This buffer shall be returned to the SW, 461 ring 3 462 463 <enum 7 SW4_BM> This buffer shall be returned to the SW, 464 ring 3 465 466 467 468 <legal all> 469 */ 470 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 471 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 472 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 473 474 /* Description REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 475 476 Cookie field exclusively used by SW. 477 478 479 480 In case of 'NULL' pointer, this field is set to 0 481 482 483 484 HW ignores the contents, accept that it passes the 485 programmed value on to other descriptors together with the 486 physical address 487 488 489 490 Field can be used by SW to for example associate the 491 buffers physical address with the virtual address 492 493 The bit definitions as used by SW are within SW HLD 494 specification 495 496 497 498 NOTE: 499 500 The three most significant bits can have a special 501 meaning in case this struct is embedded in a TX_MPDU_DETAILS 502 STRUCT, and field transmit_bw_restriction is set 503 504 505 506 In case of NON punctured transmission: 507 508 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 509 510 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 511 512 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 513 514 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 515 516 517 518 In case of punctured transmission: 519 520 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 521 522 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 523 524 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 525 526 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 527 528 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 529 530 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 531 532 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 533 534 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 535 536 537 538 Note: a punctured transmission is indicated by the 539 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 540 TLV 541 542 543 544 <legal all> 545 */ 546 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 547 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 548 #define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 549 550 /* EXTERNAL REFERENCE : struct rx_mpdu_desc_info rx_mpdu_desc_info_details */ 551 552 553 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT 554 555 Consumer: REO/SW/FW 556 557 Producer: RXDMA 558 559 560 561 The number of MSDUs within the MPDU 562 563 <legal all> 564 */ 565 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 566 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 567 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff 568 569 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER 570 571 Consumer: REO/SW/FW 572 573 Producer: RXDMA 574 575 576 577 The field can have two different meanings based on the 578 setting of field 'BAR_frame': 579 580 581 582 'BAR_frame' is NOT set: 583 584 The MPDU sequence number of the received frame. 585 586 587 588 'BAR_frame' is set. 589 590 The MPDU Start sequence number from the BAR frame 591 592 <legal all> 593 */ 594 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 595 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8 596 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00 597 598 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG 599 600 Consumer: REO/SW/FW 601 602 Producer: RXDMA 603 604 605 606 When set, this MPDU is a fragment and REO should forward 607 this fragment MPDU to the REO destination ring without any 608 reorder checks, pn checks or bitmap update. This implies 609 that REO is forwarding the pointer to the MSDU link 610 descriptor. The destination ring is coming from a 611 programmable register setting in REO 612 613 614 615 <legal all> 616 */ 617 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 618 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20 619 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000 620 621 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT 622 623 Consumer: REO/SW/FW 624 625 Producer: RXDMA 626 627 628 629 The retry bit setting from the MPDU header of the 630 received frame 631 632 <legal all> 633 */ 634 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 635 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21 636 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000 637 638 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG 639 640 Consumer: REO/SW/FW 641 642 Producer: RXDMA 643 644 645 646 When set, the MPDU was received as part of an A-MPDU. 647 648 <legal all> 649 */ 650 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 651 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22 652 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000 653 654 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME 655 656 Consumer: REO/SW/FW 657 658 Producer: RXDMA 659 660 661 662 When set, the received frame is a BAR frame. After 663 processing, this frame shall be pushed to SW or deleted. 664 665 <legal all> 666 */ 667 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 668 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23 669 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000 670 671 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO 672 673 Consumer: REO/SW/FW 674 675 Producer: RXDMA 676 677 678 679 Copied here by RXDMA from RX_MPDU_END 680 681 When not set, REO will Not perform a PN sequence number 682 check 683 */ 684 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 685 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24 686 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000 687 688 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID 689 690 When set, OLE found a valid SA entry for all MSDUs in 691 this MPDU 692 693 <legal all> 694 */ 695 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 696 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25 697 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000 698 699 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 700 701 When set, at least 1 MSDU within the MPDU has an 702 unsuccessful MAC source address search due to the expiration 703 of the search timer. 704 705 <legal all> 706 */ 707 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 708 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26 709 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000 710 711 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID 712 713 When set, OLE found a valid DA entry for all MSDUs in 714 this MPDU 715 716 <legal all> 717 */ 718 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 719 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27 720 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000 721 722 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC 723 724 Field Only valid if da_is_valid is set 725 726 727 728 When set, at least one of the DA addresses is a 729 Multicast or Broadcast address. 730 731 <legal all> 732 */ 733 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 734 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28 735 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000 736 737 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 738 739 When set, at least 1 MSDU within the MPDU has an 740 unsuccessful MAC destination address search due to the 741 expiration of the search timer. 742 743 <legal all> 744 */ 745 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 746 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29 747 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000 748 749 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU 750 751 Field only valid when first_msdu_in_mpdu_flag is set. 752 753 754 755 When set, the contents in the MSDU buffer contains a 756 'RAW' MPDU. This 'RAW' MPDU might be spread out over 757 multiple MSDU buffers. 758 759 <legal all> 760 */ 761 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 762 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30 763 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 764 765 /* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG 766 767 The More Fragment bit setting from the MPDU header of 768 the received frame 769 770 771 772 <legal all> 773 */ 774 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 775 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31 776 #define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000 777 778 /* Description REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA 779 780 Meta data that SW has programmed in the Peer table entry 781 of the transmitting STA. 782 783 <legal all> 784 */ 785 #define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c 786 #define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 787 #define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 788 789 /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ 790 791 792 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG 793 794 Parsed from RX_MSDU_END TLV . In the case MSDU spans 795 over multiple buffers, this field will be valid in the Last 796 buffer used by the MSDU 797 798 799 800 <enum 0 Not_first_msdu> This is not the first MSDU in 801 the MPDU. 802 803 <enum 1 first_msdu> This MSDU is the first one in the 804 MPDU. 805 806 807 808 <legal all> 809 */ 810 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 811 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 812 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 813 814 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG 815 816 Consumer: WBM/REO/SW/FW 817 818 Producer: RXDMA 819 820 821 822 Parsed from RX_MSDU_END TLV . In the case MSDU spans 823 over multiple buffers, this field will be valid in the Last 824 buffer used by the MSDU 825 826 827 828 <enum 0 Not_last_msdu> There are more MSDUs linked to 829 this MSDU that belongs to this MPDU 830 831 <enum 1 Last_msdu> this MSDU is the last one in the 832 MPDU. This setting is only allowed in combination with 833 'Msdu_continuation' set to 0. This implies that when an msdu 834 is spread out over multiple buffers and thus 835 msdu_continuation is set, only for the very last buffer of 836 the msdu, can the 'last_msdu_in_mpdu_flag' be set. 837 838 839 840 When both first_msdu_in_mpdu_flag and 841 last_msdu_in_mpdu_flag are set, the MPDU that this MSDU 842 belongs to only contains a single MSDU. 843 844 845 846 847 848 <legal all> 849 */ 850 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 851 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 852 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 853 854 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION 855 856 When set, this MSDU buffer was not able to hold the 857 entire MSDU. The next buffer will therefor contain 858 additional information related to this MSDU. 859 860 861 862 <legal all> 863 */ 864 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 865 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 866 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 867 868 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH 869 870 Parsed from RX_MSDU_START TLV . In the case MSDU spans 871 over multiple buffers, this field will be valid in the First 872 buffer used by MSDU. 873 874 875 876 Full MSDU length in bytes after decapsulation. 877 878 879 880 This field is still valid for MPDU frames without 881 A-MSDU. It still represents MSDU length after decapsulation 882 883 884 885 Or in case of RAW MPDUs, it indicates the length of the 886 entire MPDU (without FCS field) 887 888 <legal all> 889 */ 890 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 891 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 892 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 893 894 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION 895 896 Parsed from RX_MSDU_END TLV . In the case MSDU spans 897 over multiple buffers, this field will be valid in the Last 898 buffer used by the MSDU 899 900 901 902 The ID of the REO exit ring where the MSDU frame shall 903 push after (MPDU level) reordering has finished. 904 905 906 907 <enum 0 reo_destination_tcl> Reo will push the frame 908 into the REO2TCL ring 909 910 <enum 1 reo_destination_sw1> Reo will push the frame 911 into the REO2SW1 ring 912 913 <enum 2 reo_destination_sw2> Reo will push the frame 914 into the REO2SW1 ring 915 916 <enum 3 reo_destination_sw3> Reo will push the frame 917 into the REO2SW1 ring 918 919 <enum 4 reo_destination_sw4> Reo will push the frame 920 into the REO2SW1 ring 921 922 <enum 5 reo_destination_release> Reo will push the frame 923 into the REO_release ring 924 925 <enum 6 reo_destination_fw> Reo will push the frame into 926 the REO2FW ring 927 928 <enum 7 reo_destination_7> REO remaps this 929 930 <enum 8 reo_destination_8> REO remaps this <enum 9 931 reo_destination_9> REO remaps this <enum 10 932 reo_destination_10> REO remaps this 933 934 <enum 11 reo_destination_11> REO remaps this 935 936 <enum 12 reo_destination_12> REO remaps this <enum 13 937 reo_destination_13> REO remaps this 938 939 <enum 14 reo_destination_14> REO remaps this 940 941 <enum 15 reo_destination_15> REO remaps this 942 943 <enum 16 reo_destination_16> REO remaps this 944 945 <enum 17 reo_destination_17> REO remaps this 946 947 <enum 18 reo_destination_18> REO remaps this 948 949 <enum 19 reo_destination_19> REO remaps this 950 951 <enum 20 reo_destination_20> REO remaps this 952 953 <enum 21 reo_destination_21> REO remaps this 954 955 <enum 22 reo_destination_22> REO remaps this 956 957 <enum 23 reo_destination_23> REO remaps this 958 959 <enum 24 reo_destination_24> REO remaps this 960 961 <enum 25 reo_destination_25> REO remaps this 962 963 <enum 26 reo_destination_26> REO remaps this 964 965 <enum 27 reo_destination_27> REO remaps this 966 967 <enum 28 reo_destination_28> REO remaps this 968 969 <enum 29 reo_destination_29> REO remaps this 970 971 <enum 30 reo_destination_30> REO remaps this 972 973 <enum 31 reo_destination_31> REO remaps this 974 975 976 977 <legal all> 978 */ 979 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000010 980 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 981 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 982 983 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP 984 985 Parsed from RX_MSDU_END TLV . In the case MSDU spans 986 over multiple buffers, this field will be valid in the Last 987 buffer used by the MSDU 988 989 990 991 When set, REO shall drop this MSDU and not forward it to 992 any other ring... 993 994 <legal all> 995 */ 996 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 997 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 998 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 999 1000 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID 1001 1002 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1003 over multiple buffers, this field will be valid in the Last 1004 buffer used by the MSDU 1005 1006 1007 1008 Indicates that OLE found a valid SA entry for this MSDU 1009 1010 <legal all> 1011 */ 1012 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 1013 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 1014 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 1015 1016 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 1017 1018 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1019 over multiple buffers, this field will be valid in the Last 1020 buffer used by the MSDU 1021 1022 1023 1024 Indicates an unsuccessful MAC source address search due 1025 to the expiring of the search timer for this MSDU 1026 1027 <legal all> 1028 */ 1029 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000010 1030 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 1031 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 1032 1033 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID 1034 1035 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1036 over multiple buffers, this field will be valid in the Last 1037 buffer used by the MSDU 1038 1039 1040 1041 Indicates that OLE found a valid DA entry for this MSDU 1042 1043 <legal all> 1044 */ 1045 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 1046 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 1047 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 1048 1049 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC 1050 1051 Field Only valid if da_is_valid is set 1052 1053 1054 1055 Indicates the DA address was a Multicast of Broadcast 1056 address for this MSDU 1057 1058 <legal all> 1059 */ 1060 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 1061 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 1062 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 1063 1064 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 1065 1066 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1067 over multiple buffers, this field will be valid in the Last 1068 buffer used by the MSDU 1069 1070 1071 1072 Indicates an unsuccessful MAC destination address search 1073 due to the expiring of the search timer for this MSDU 1074 1075 <legal all> 1076 */ 1077 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000010 1078 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 1079 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 1080 1081 /* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A 1082 1083 <legal 0> 1084 */ 1085 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000010 1086 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28 1087 #define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000 1088 1089 /* Description REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A 1090 1091 <legal 0> 1092 */ 1093 #define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000014 1094 #define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0 1095 #define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff 1096 1097 /* Description REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0 1098 1099 Consumer: REO 1100 1101 Producer: RXDMA 1102 1103 1104 1105 Address (lower 32 bits) of the REO queue descriptor. 1106 1107 <legal all> 1108 */ 1109 #define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000018 1110 #define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 1111 #define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff 1112 1113 /* Description REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32 1114 1115 Consumer: REO 1116 1117 Producer: RXDMA 1118 1119 1120 1121 Address (upper 8 bits) of the REO queue descriptor. 1122 1123 <legal all> 1124 */ 1125 #define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000001c 1126 #define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 1127 #define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff 1128 1129 /* Description REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE 1130 1131 Indicates the type of address provided in the 1132 'Buf_or_link_desc_addr_info' 1133 1134 1135 1136 <enum 0 MSDU_buf_address> The address of an MSDU buffer 1137 1138 <enum 1 MSDU_link_desc_address> The address of the MSDU 1139 link descriptor. 1140 1141 1142 1143 <legal all> 1144 */ 1145 #define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c 1146 #define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB 8 1147 #define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK 0x00000100 1148 1149 /* Description REO_DESTINATION_RING_7_REO_PUSH_REASON 1150 1151 Indicates why REO pushed the frame to this exit ring 1152 1153 1154 1155 <enum 0 reo_error_detected> Reo detected an error an 1156 pushed this frame to this queue 1157 1158 <enum 1 reo_routing_instruction> Reo pushed the frame to 1159 this queue per received routing instructions. No error 1160 within REO was detected 1161 1162 1163 1164 1165 1166 <legal 0 - 1> 1167 */ 1168 #define REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET 0x0000001c 1169 #define REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB 9 1170 #define REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK 0x00000600 1171 1172 /* Description REO_DESTINATION_RING_7_REO_ERROR_CODE 1173 1174 Field only valid when 'Reo_push_reason' set to 1175 'reo_error_detected'. 1176 1177 1178 1179 <enum 0 reo_queue_desc_addr_zero> Reo queue descriptor 1180 provided in the REO_ENTRANCE ring is set to 0 1181 1182 <enum 1 reo_queue_desc_not_valid> Reo queue descriptor 1183 valid bit is NOT set 1184 1185 <enum 2 ampdu_in_non_ba> AMPDU frame received without BA 1186 session having been setup. 1187 1188 <enum 3 non_ba_duplicate> Non-BA session, SN equal to 1189 SSN, Retry bit set: duplicate frame 1190 1191 <enum 4 ba_duplicate> BA session, duplicate frame 1192 1193 <enum 5 regular_frame_2k_jump> A normal (management/data 1194 frame) received with 2K jump in SN 1195 1196 <enum 6 bar_frame_2k_jump> A bar received with 2K jump 1197 in SSN 1198 1199 <enum 7 regular_frame_OOR> A normal (management/data 1200 frame) received with SN falling within the OOR window 1201 1202 <enum 8 bar_frame_OOR> A bar received with SSN falling 1203 within the OOR window 1204 1205 <enum 9 bar_frame_no_ba_session> A bar received without 1206 a BA session 1207 1208 <enum 10 bar_frame_sn_equals_ssn> A bar received with 1209 SSN equal to SN 1210 1211 <enum 11 pn_check_failed> PN Check Failed packet. 1212 1213 <enum 12 2k_error_handling_flag_set> Frame is forwarded 1214 as a result of the 'Seq_2k_error_detected_flag' been set in 1215 the REO Queue descriptor 1216 1217 <enum 13 pn_error_handling_flag_set> Frame is forwarded 1218 as a result of the 'pn_error_detected_flag' been set in the 1219 REO Queue descriptor 1220 1221 <enum 14 queue_descriptor_blocked_set> Frame is 1222 forwarded as a result of the queue descriptor(address) being 1223 blocked as SW/FW seems to be currently in the process of 1224 making updates to this descriptor... 1225 1226 1227 1228 <legal 0-14> 1229 */ 1230 #define REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET 0x0000001c 1231 #define REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB 11 1232 #define REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK 0x0000f800 1233 1234 /* Description REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER 1235 1236 This field indicates the REO MPDU reorder queue ID from 1237 which this frame originated. This field is populated from a 1238 field with the same name in the RX_REO_QUEUE descriptor. 1239 1240 <legal all> 1241 */ 1242 #define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000001c 1243 #define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_LSB 16 1244 #define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_MASK 0xffff0000 1245 1246 /* Description REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID 1247 1248 When set, REO has been instructed to not perform the 1249 actual re-ordering of frames for this queue, but just to 1250 insert the reorder opcodes 1251 1252 <legal all> 1253 */ 1254 #define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_OFFSET 0x00000020 1255 #define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_LSB 0 1256 #define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_MASK 0x00000001 1257 1258 /* Description REO_DESTINATION_RING_8_REORDER_OPCODE 1259 1260 Field is valid when 'Soft_reorder_info_valid' is set. 1261 This field is always valid for debug purpose as well. 1262 1263 Details are in the MLD. 1264 1265 1266 1267 <enum 0 invalid> 1268 1269 <enum 1 fwdcur_fwdbuf> 1270 1271 <enum 2 fwdbuf_fwdcur> 1272 1273 <enum 3 qcur> 1274 1275 <enum 4 fwdbuf_qcur> 1276 1277 <enum 5 fwdbuf_drop> 1278 1279 <enum 6 fwdall_drop> 1280 1281 <enum 7 fwdall_qcur> 1282 1283 <enum 8 reserved_reo_opcode_1> 1284 1285 <enum 9 dropcur> the error reason code is in 1286 reo_error_code field. 1287 1288 <enum 10 reserved_reo_opcode_2> 1289 1290 <enum 11 reserved_reo_opcode_3> 1291 1292 <enum 12 reserved_reo_opcode_4> 1293 1294 <enum 13 reserved_reo_opcode_5> 1295 1296 <enum 14 reserved_reo_opcode_6> 1297 1298 <enum 15 reserved_reo_opcode_7> 1299 1300 1301 1302 <legal all> 1303 */ 1304 #define REO_DESTINATION_RING_8_REORDER_OPCODE_OFFSET 0x00000020 1305 #define REO_DESTINATION_RING_8_REORDER_OPCODE_LSB 1 1306 #define REO_DESTINATION_RING_8_REORDER_OPCODE_MASK 0x0000001e 1307 1308 /* Description REO_DESTINATION_RING_8_REORDER_SLOT_INDEX 1309 1310 Field only valid when 'Soft_reorder_info_valid' is set. 1311 1312 1313 1314 TODO: add description 1315 1316 1317 1318 <legal all> 1319 */ 1320 #define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_OFFSET 0x00000020 1321 #define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_LSB 5 1322 #define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_MASK 0x00001fe0 1323 1324 /* Description REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER 1325 1326 Field only valid when Rx_mpdu_desc_info_details. 1327 1328 Fragment_flag is set. 1329 1330 1331 1332 The fragment number from the 802.11 header. 1333 1334 1335 1336 Note that the sequence number is embedded in field: 1337 Rx_mpdu_desc_info_details. 1338 1339 Mpdu_Sequence_number 1340 1341 <legal all> 1342 */ 1343 #define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020 1344 #define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_LSB 13 1345 #define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_MASK 0x0001e000 1346 1347 /* Description REO_DESTINATION_RING_8_RESERVED_8A 1348 1349 <legal 0> 1350 */ 1351 #define REO_DESTINATION_RING_8_RESERVED_8A_OFFSET 0x00000020 1352 #define REO_DESTINATION_RING_8_RESERVED_8A_LSB 17 1353 #define REO_DESTINATION_RING_8_RESERVED_8A_MASK 0xfffe0000 1354 1355 /* Description REO_DESTINATION_RING_9_RESERVED_9A 1356 1357 <legal 0> 1358 */ 1359 #define REO_DESTINATION_RING_9_RESERVED_9A_OFFSET 0x00000024 1360 #define REO_DESTINATION_RING_9_RESERVED_9A_LSB 0 1361 #define REO_DESTINATION_RING_9_RESERVED_9A_MASK 0xffffffff 1362 1363 /* Description REO_DESTINATION_RING_10_RESERVED_10A 1364 1365 <legal 0> 1366 */ 1367 #define REO_DESTINATION_RING_10_RESERVED_10A_OFFSET 0x00000028 1368 #define REO_DESTINATION_RING_10_RESERVED_10A_LSB 0 1369 #define REO_DESTINATION_RING_10_RESERVED_10A_MASK 0xffffffff 1370 1371 /* Description REO_DESTINATION_RING_11_RESERVED_11A 1372 1373 <legal 0> 1374 */ 1375 #define REO_DESTINATION_RING_11_RESERVED_11A_OFFSET 0x0000002c 1376 #define REO_DESTINATION_RING_11_RESERVED_11A_LSB 0 1377 #define REO_DESTINATION_RING_11_RESERVED_11A_MASK 0xffffffff 1378 1379 /* Description REO_DESTINATION_RING_12_RESERVED_12A 1380 1381 <legal 0> 1382 */ 1383 #define REO_DESTINATION_RING_12_RESERVED_12A_OFFSET 0x00000030 1384 #define REO_DESTINATION_RING_12_RESERVED_12A_LSB 0 1385 #define REO_DESTINATION_RING_12_RESERVED_12A_MASK 0xffffffff 1386 1387 /* Description REO_DESTINATION_RING_13_RESERVED_13A 1388 1389 <legal 0> 1390 */ 1391 #define REO_DESTINATION_RING_13_RESERVED_13A_OFFSET 0x00000034 1392 #define REO_DESTINATION_RING_13_RESERVED_13A_LSB 0 1393 #define REO_DESTINATION_RING_13_RESERVED_13A_MASK 0xffffffff 1394 1395 /* Description REO_DESTINATION_RING_14_RESERVED_14A 1396 1397 <legal 0> 1398 */ 1399 #define REO_DESTINATION_RING_14_RESERVED_14A_OFFSET 0x00000038 1400 #define REO_DESTINATION_RING_14_RESERVED_14A_LSB 0 1401 #define REO_DESTINATION_RING_14_RESERVED_14A_MASK 0xffffffff 1402 1403 /* Description REO_DESTINATION_RING_15_RESERVED_15 1404 1405 <legal 0> 1406 */ 1407 #define REO_DESTINATION_RING_15_RESERVED_15_OFFSET 0x0000003c 1408 #define REO_DESTINATION_RING_15_RESERVED_15_LSB 0 1409 #define REO_DESTINATION_RING_15_RESERVED_15_MASK 0x000fffff 1410 1411 /* Description REO_DESTINATION_RING_15_RING_ID 1412 1413 The buffer pointer ring ID. 1414 1415 0 refers to the IDLE ring 1416 1417 1 - N refers to other rings 1418 1419 1420 1421 Helps with debugging when dumping ring contents. 1422 1423 <legal all> 1424 */ 1425 #define REO_DESTINATION_RING_15_RING_ID_OFFSET 0x0000003c 1426 #define REO_DESTINATION_RING_15_RING_ID_LSB 20 1427 #define REO_DESTINATION_RING_15_RING_ID_MASK 0x0ff00000 1428 1429 /* Description REO_DESTINATION_RING_15_LOOPING_COUNT 1430 1431 A count value that indicates the number of times the 1432 producer of entries into this Ring has looped around the 1433 ring. 1434 1435 At initialization time, this value is set to 0. On the 1436 first loop, this value is set to 1. After the max value is 1437 reached allowed by the number of bits for this field, the 1438 count value continues with 0 again. 1439 1440 In case SW is the consumer of the ring entries, it can 1441 use this field to figure out up to where the producer of 1442 entries has created new entries. This eliminates the need to 1443 check where the head pointer' of the ring is located once 1444 the SW starts processing an interrupt indicating that new 1445 entries have been put into this ring... 1446 1447 1448 1449 Also note that SW if it wants only needs to look at the 1450 LSB bit of this count value. 1451 1452 <legal all> 1453 */ 1454 #define REO_DESTINATION_RING_15_LOOPING_COUNT_OFFSET 0x0000003c 1455 #define REO_DESTINATION_RING_15_LOOPING_COUNT_LSB 28 1456 #define REO_DESTINATION_RING_15_LOOPING_COUNT_MASK 0xf0000000 1457 1458 1459 #endif // _REO_DESTINATION_RING_H_ 1460