xref: /wlan-driver/fw-api/hw/qca8074/v2/reo_flush_queue.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2020 The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 // $ATH_LICENSE_HW_HDR_C$
18 //
19 // DO NOT EDIT!  This file is automatically generated
20 //               These definitions are tied to a particular hardware layout
21 
22 
23 #ifndef _REO_FLUSH_QUEUE_H_
24 #define _REO_FLUSH_QUEUE_H_
25 #if !defined(__ASSEMBLER__)
26 #endif
27 
28 #include "uniform_reo_cmd_header.h"
29 
30 // ################ START SUMMARY #################
31 //
32 //	Dword	Fields
33 //	0	struct uniform_reo_cmd_header cmd_header;
34 //	1	flush_desc_addr_31_0[31:0]
35 //	2	flush_desc_addr_39_32[7:0], block_desc_addr_usage_after_flush[8], block_resource_index[10:9], invalidate_queue_and_flush[11], reserved_2a[31:12]
36 //	3	reserved_3a[31:0]
37 //	4	reserved_4a[31:0]
38 //	5	reserved_5a[31:0]
39 //	6	reserved_6a[31:0]
40 //	7	reserved_7a[31:0]
41 //	8	reserved_8a[31:0]
42 //
43 // ################ END SUMMARY #################
44 
45 #define NUM_OF_DWORDS_REO_FLUSH_QUEUE 9
46 
47 struct reo_flush_queue {
48     struct            uniform_reo_cmd_header                       cmd_header;
49              uint32_t flush_desc_addr_31_0            : 32; //[31:0]
50              uint32_t flush_desc_addr_39_32           :  8, //[7:0]
51                       block_desc_addr_usage_after_flush:  1, //[8]
52                       block_resource_index            :  2, //[10:9]
53                       invalidate_queue_and_flush      :  1, //[11]
54                       reserved_2a                     : 20; //[31:12]
55              uint32_t reserved_3a                     : 32; //[31:0]
56              uint32_t reserved_4a                     : 32; //[31:0]
57              uint32_t reserved_5a                     : 32; //[31:0]
58              uint32_t reserved_6a                     : 32; //[31:0]
59              uint32_t reserved_7a                     : 32; //[31:0]
60              uint32_t reserved_8a                     : 32; //[31:0]
61 };
62 
63 /*
64 
65 struct uniform_reo_cmd_header cmd_header
66 
67 			Consumer: REO
68 
69 			Producer: SW
70 
71 
72 
73 			Details for command execution tracking purposes.
74 
75 flush_desc_addr_31_0
76 
77 			Consumer: REO
78 
79 			Producer: SW
80 
81 
82 
83 			Address (lower 32 bits) of the descriptor to flush
84 
85 			<legal all>
86 
87 flush_desc_addr_39_32
88 
89 			Consumer: REO
90 
91 			Producer: SW
92 
93 
94 
95 			Address (upper 8 bits) of the descriptor to flush
96 
97 			<legal all>
98 
99 block_desc_addr_usage_after_flush
100 
101 			When set, REO shall not re-fetch this address till SW
102 			explicitly unblocked this address
103 
104 
105 
106 			If the blocking resource was already used, this command
107 			shall fail and an error is reported
108 
109 
110 
111 			<legal all>
112 
113 block_resource_index
114 
115 			Field only valid when 'Block_desc_addr_usage_after_flush
116 			' is set.
117 
118 
119 
120 			Indicates which of the four blocking resources in REO
121 			will be assigned for managing the blocking of this address.
122 
123 			<legal all>
124 
125 invalidate_queue_and_flush
126 
127 			When set, after the queue has been completely flushed,
128 			invalidate the queue by clearing VLD and flush the queue
129 			descriptor from the cache.
130 
131 
132 
133 			<legal all>
134 
135 reserved_2a
136 
137 			<legal 0>
138 
139 reserved_3a
140 
141 			<legal 0>
142 
143 reserved_4a
144 
145 			<legal 0>
146 
147 reserved_5a
148 
149 			<legal 0>
150 
151 reserved_6a
152 
153 			<legal 0>
154 
155 reserved_7a
156 
157 			<legal 0>
158 
159 reserved_8a
160 
161 			<legal 0>
162 */
163 
164 
165  /* EXTERNAL REFERENCE : struct uniform_reo_cmd_header cmd_header */
166 
167 
168 /* Description		REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER
169 
170 			Consumer: REO/SW/DEBUG
171 
172 			Producer: SW
173 
174 
175 
176 			This number can be used by SW to track, identify and
177 			link the created commands with the command statusses
178 
179 
180 
181 
182 
183 			<legal all>
184 */
185 #define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET           0x00000000
186 #define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_LSB              0
187 #define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_MASK             0x0000ffff
188 
189 /* Description		REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED
190 
191 			Consumer: REO
192 
193 			Producer: SW
194 
195 
196 
197 			<enum 0 NoStatus> REO does not need to generate a status
198 			TLV for the execution of this command
199 
200 			<enum 1 StatusRequired> REO shall generate a status TLV
201 			for the execution of this command
202 
203 
204 
205 			<legal all>
206 */
207 #define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET      0x00000000
208 #define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB         16
209 #define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK        0x00010000
210 
211 /* Description		REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A
212 
213 			<legal 0>
214 */
215 #define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_OFFSET              0x00000000
216 #define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_LSB                 17
217 #define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_MASK                0xfffe0000
218 
219 /* Description		REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0
220 
221 			Consumer: REO
222 
223 			Producer: SW
224 
225 
226 
227 			Address (lower 32 bits) of the descriptor to flush
228 
229 			<legal all>
230 */
231 #define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_OFFSET                0x00000004
232 #define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_LSB                   0
233 #define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_MASK                  0xffffffff
234 
235 /* Description		REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32
236 
237 			Consumer: REO
238 
239 			Producer: SW
240 
241 
242 
243 			Address (upper 8 bits) of the descriptor to flush
244 
245 			<legal all>
246 */
247 #define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_OFFSET               0x00000008
248 #define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_LSB                  0
249 #define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_MASK                 0x000000ff
250 
251 /* Description		REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH
252 
253 			When set, REO shall not re-fetch this address till SW
254 			explicitly unblocked this address
255 
256 
257 
258 			If the blocking resource was already used, this command
259 			shall fail and an error is reported
260 
261 
262 
263 			<legal all>
264 */
265 #define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET   0x00000008
266 #define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB      8
267 #define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK     0x00000100
268 
269 /* Description		REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX
270 
271 			Field only valid when 'Block_desc_addr_usage_after_flush
272 			' is set.
273 
274 
275 
276 			Indicates which of the four blocking resources in REO
277 			will be assigned for managing the blocking of this address.
278 
279 			<legal all>
280 */
281 #define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_OFFSET                0x00000008
282 #define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_LSB                   9
283 #define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_MASK                  0x00000600
284 
285 /* Description		REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH
286 
287 			When set, after the queue has been completely flushed,
288 			invalidate the queue by clearing VLD and flush the queue
289 			descriptor from the cache.
290 
291 
292 
293 			<legal all>
294 */
295 #define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_OFFSET          0x00000008
296 #define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_LSB             11
297 #define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_MASK            0x00000800
298 
299 /* Description		REO_FLUSH_QUEUE_2_RESERVED_2A
300 
301 			<legal 0>
302 */
303 #define REO_FLUSH_QUEUE_2_RESERVED_2A_OFFSET                         0x00000008
304 #define REO_FLUSH_QUEUE_2_RESERVED_2A_LSB                            12
305 #define REO_FLUSH_QUEUE_2_RESERVED_2A_MASK                           0xfffff000
306 
307 /* Description		REO_FLUSH_QUEUE_3_RESERVED_3A
308 
309 			<legal 0>
310 */
311 #define REO_FLUSH_QUEUE_3_RESERVED_3A_OFFSET                         0x0000000c
312 #define REO_FLUSH_QUEUE_3_RESERVED_3A_LSB                            0
313 #define REO_FLUSH_QUEUE_3_RESERVED_3A_MASK                           0xffffffff
314 
315 /* Description		REO_FLUSH_QUEUE_4_RESERVED_4A
316 
317 			<legal 0>
318 */
319 #define REO_FLUSH_QUEUE_4_RESERVED_4A_OFFSET                         0x00000010
320 #define REO_FLUSH_QUEUE_4_RESERVED_4A_LSB                            0
321 #define REO_FLUSH_QUEUE_4_RESERVED_4A_MASK                           0xffffffff
322 
323 /* Description		REO_FLUSH_QUEUE_5_RESERVED_5A
324 
325 			<legal 0>
326 */
327 #define REO_FLUSH_QUEUE_5_RESERVED_5A_OFFSET                         0x00000014
328 #define REO_FLUSH_QUEUE_5_RESERVED_5A_LSB                            0
329 #define REO_FLUSH_QUEUE_5_RESERVED_5A_MASK                           0xffffffff
330 
331 /* Description		REO_FLUSH_QUEUE_6_RESERVED_6A
332 
333 			<legal 0>
334 */
335 #define REO_FLUSH_QUEUE_6_RESERVED_6A_OFFSET                         0x00000018
336 #define REO_FLUSH_QUEUE_6_RESERVED_6A_LSB                            0
337 #define REO_FLUSH_QUEUE_6_RESERVED_6A_MASK                           0xffffffff
338 
339 /* Description		REO_FLUSH_QUEUE_7_RESERVED_7A
340 
341 			<legal 0>
342 */
343 #define REO_FLUSH_QUEUE_7_RESERVED_7A_OFFSET                         0x0000001c
344 #define REO_FLUSH_QUEUE_7_RESERVED_7A_LSB                            0
345 #define REO_FLUSH_QUEUE_7_RESERVED_7A_MASK                           0xffffffff
346 
347 /* Description		REO_FLUSH_QUEUE_8_RESERVED_8A
348 
349 			<legal 0>
350 */
351 #define REO_FLUSH_QUEUE_8_RESERVED_8A_OFFSET                         0x00000020
352 #define REO_FLUSH_QUEUE_8_RESERVED_8A_LSB                            0
353 #define REO_FLUSH_QUEUE_8_RESERVED_8A_MASK                           0xffffffff
354 
355 
356 #endif // _REO_FLUSH_QUEUE_H_
357