xref: /wlan-driver/fw-api/hw/qca8074/v2/reo_update_rx_reo_queue_status.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2020 The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 // $ATH_LICENSE_HW_HDR_C$
18 //
19 // DO NOT EDIT!  This file is automatically generated
20 //               These definitions are tied to a particular hardware layout
21 
22 
23 #ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
24 #define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
25 #if !defined(__ASSEMBLER__)
26 #endif
27 
28 #include "uniform_reo_status_header.h"
29 
30 // ################ START SUMMARY #################
31 //
32 //	Dword	Fields
33 //	0-1	struct uniform_reo_status_header status_header;
34 //	2	reserved_2a[31:0]
35 //	3	reserved_3a[31:0]
36 //	4	reserved_4a[31:0]
37 //	5	reserved_5a[31:0]
38 //	6	reserved_6a[31:0]
39 //	7	reserved_7a[31:0]
40 //	8	reserved_8a[31:0]
41 //	9	reserved_9a[31:0]
42 //	10	reserved_10a[31:0]
43 //	11	reserved_11a[31:0]
44 //	12	reserved_12a[31:0]
45 //	13	reserved_13a[31:0]
46 //	14	reserved_14a[31:0]
47 //	15	reserved_15a[31:0]
48 //	16	reserved_16a[31:0]
49 //	17	reserved_17a[31:0]
50 //	18	reserved_18a[31:0]
51 //	19	reserved_19a[31:0]
52 //	20	reserved_20a[31:0]
53 //	21	reserved_21a[31:0]
54 //	22	reserved_22a[31:0]
55 //	23	reserved_23a[31:0]
56 //	24	reserved_24a[27:0], looping_count[31:28]
57 //
58 // ################ END SUMMARY #################
59 
60 #define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 25
61 
62 struct reo_update_rx_reo_queue_status {
63     struct            uniform_reo_status_header                       status_header;
64              uint32_t reserved_2a                     : 32; //[31:0]
65              uint32_t reserved_3a                     : 32; //[31:0]
66              uint32_t reserved_4a                     : 32; //[31:0]
67              uint32_t reserved_5a                     : 32; //[31:0]
68              uint32_t reserved_6a                     : 32; //[31:0]
69              uint32_t reserved_7a                     : 32; //[31:0]
70              uint32_t reserved_8a                     : 32; //[31:0]
71              uint32_t reserved_9a                     : 32; //[31:0]
72              uint32_t reserved_10a                    : 32; //[31:0]
73              uint32_t reserved_11a                    : 32; //[31:0]
74              uint32_t reserved_12a                    : 32; //[31:0]
75              uint32_t reserved_13a                    : 32; //[31:0]
76              uint32_t reserved_14a                    : 32; //[31:0]
77              uint32_t reserved_15a                    : 32; //[31:0]
78              uint32_t reserved_16a                    : 32; //[31:0]
79              uint32_t reserved_17a                    : 32; //[31:0]
80              uint32_t reserved_18a                    : 32; //[31:0]
81              uint32_t reserved_19a                    : 32; //[31:0]
82              uint32_t reserved_20a                    : 32; //[31:0]
83              uint32_t reserved_21a                    : 32; //[31:0]
84              uint32_t reserved_22a                    : 32; //[31:0]
85              uint32_t reserved_23a                    : 32; //[31:0]
86              uint32_t reserved_24a                    : 28, //[27:0]
87                       looping_count                   :  4; //[31:28]
88 };
89 
90 /*
91 
92 struct uniform_reo_status_header status_header
93 
94 			Consumer: SW
95 
96 			Producer: REO
97 
98 
99 
100 			Details that can link this status with the original
101 			command. It also contains info on how long REO took to
102 			execute this command.
103 
104 reserved_2a
105 
106 			<legal 0>
107 
108 reserved_3a
109 
110 			<legal 0>
111 
112 reserved_4a
113 
114 			<legal 0>
115 
116 reserved_5a
117 
118 			<legal 0>
119 
120 reserved_6a
121 
122 			<legal 0>
123 
124 reserved_7a
125 
126 			<legal 0>
127 
128 reserved_8a
129 
130 			<legal 0>
131 
132 reserved_9a
133 
134 			<legal 0>
135 
136 reserved_10a
137 
138 			<legal 0>
139 
140 reserved_11a
141 
142 			<legal 0>
143 
144 reserved_12a
145 
146 			<legal 0>
147 
148 reserved_13a
149 
150 			<legal 0>
151 
152 reserved_14a
153 
154 			<legal 0>
155 
156 reserved_15a
157 
158 			<legal 0>
159 
160 reserved_16a
161 
162 			<legal 0>
163 
164 reserved_17a
165 
166 			<legal 0>
167 
168 reserved_18a
169 
170 			<legal 0>
171 
172 reserved_19a
173 
174 			<legal 0>
175 
176 reserved_20a
177 
178 			<legal 0>
179 
180 reserved_21a
181 
182 			<legal 0>
183 
184 reserved_22a
185 
186 			<legal 0>
187 
188 reserved_23a
189 
190 			<legal 0>
191 
192 reserved_24a
193 
194 			<legal 0>
195 
196 looping_count
197 
198 			A count value that indicates the number of times the
199 			producer of entries into this Ring has looped around the
200 			ring.
201 
202 			At initialization time, this value is set to 0. On the
203 			first loop, this value is set to 1. After the max value is
204 			reached allowed by the number of bits for this field, the
205 			count value continues with 0 again.
206 
207 
208 
209 			In case SW is the consumer of the ring entries, it can
210 			use this field to figure out up to where the producer of
211 			entries has created new entries. This eliminates the need to
212 			check where the head pointer' of the ring is located once
213 			the SW starts processing an interrupt indicating that new
214 			entries have been put into this ring...
215 
216 
217 
218 			Also note that SW if it wants only needs to look at the
219 			LSB bit of this count value.
220 
221 			<legal all>
222 */
223 
224 
225  /* EXTERNAL REFERENCE : struct uniform_reo_status_header status_header */
226 
227 
228 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER
229 
230 			Consumer: SW , DEBUG
231 
232 			Producer: REO
233 
234 
235 
236 			The value in this field is equal to value of the
237 			'REO_CMD_Number' field the REO command
238 
239 
240 
241 			This field helps to correlate the statuses with the REO
242 			commands.
243 
244 
245 
246 			<legal all>
247 */
248 #define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
249 #define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
250 #define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
251 
252 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME
253 
254 			Consumer: DEBUG
255 
256 			Producer: REO
257 
258 
259 
260 			The amount of time REO took to excecute the command.
261 			Note that this time does not include the duration of the
262 			command waiting in the command ring, before the execution
263 			started.
264 
265 
266 
267 			In us.
268 
269 
270 
271 			<legal all>
272 */
273 #define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
274 #define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
275 #define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
276 
277 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS
278 
279 			Consumer: DEBUG
280 
281 			Producer: REO
282 
283 
284 
285 			Execution status of the command.
286 
287 
288 
289 			<enum 0 reo_successful_execution> Command has
290 			successfully be executed
291 
292 			<enum 1 reo_blocked_execution> Command could not be
293 			executed as the queue or cache was blocked
294 
295 			<enum 2 reo_failed_execution> Command has encountered
296 			problems when executing, like the queue descriptor not being
297 			valid. None of the status fields in the entire STATUS TLV
298 			are valid.
299 
300 			<enum 3 reo_resource_blocked> Command is NOT  executed
301 			because one or more descriptors were blocked. This is SW
302 			programming mistake.
303 
304 			None of the status fields in the entire STATUS TLV are
305 			valid.
306 
307 
308 
309 			<legal  0-3>
310 */
311 #define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
312 #define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
313 #define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
314 
315 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A
316 
317 			<legal 0>
318 */
319 #define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000
320 #define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28
321 #define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
322 
323 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP
324 
325 			Timestamp at the moment that this status report is
326 			written.
327 
328 
329 
330 			<legal all>
331 */
332 #define REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004
333 #define REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0
334 #define REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
335 
336 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A
337 
338 			<legal 0>
339 */
340 #define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_OFFSET          0x00000008
341 #define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_LSB             0
342 #define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_MASK            0xffffffff
343 
344 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A
345 
346 			<legal 0>
347 */
348 #define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_OFFSET          0x0000000c
349 #define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_LSB             0
350 #define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_MASK            0xffffffff
351 
352 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A
353 
354 			<legal 0>
355 */
356 #define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_OFFSET          0x00000010
357 #define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_LSB             0
358 #define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_MASK            0xffffffff
359 
360 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A
361 
362 			<legal 0>
363 */
364 #define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_OFFSET          0x00000014
365 #define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_LSB             0
366 #define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_MASK            0xffffffff
367 
368 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A
369 
370 			<legal 0>
371 */
372 #define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_OFFSET          0x00000018
373 #define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_LSB             0
374 #define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_MASK            0xffffffff
375 
376 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A
377 
378 			<legal 0>
379 */
380 #define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_OFFSET          0x0000001c
381 #define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_LSB             0
382 #define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_MASK            0xffffffff
383 
384 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A
385 
386 			<legal 0>
387 */
388 #define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_OFFSET          0x00000020
389 #define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_LSB             0
390 #define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_MASK            0xffffffff
391 
392 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A
393 
394 			<legal 0>
395 */
396 #define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_OFFSET          0x00000024
397 #define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_LSB             0
398 #define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_MASK            0xffffffff
399 
400 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A
401 
402 			<legal 0>
403 */
404 #define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_OFFSET        0x00000028
405 #define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_LSB           0
406 #define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_MASK          0xffffffff
407 
408 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A
409 
410 			<legal 0>
411 */
412 #define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_OFFSET        0x0000002c
413 #define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_LSB           0
414 #define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_MASK          0xffffffff
415 
416 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A
417 
418 			<legal 0>
419 */
420 #define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_OFFSET        0x00000030
421 #define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_LSB           0
422 #define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_MASK          0xffffffff
423 
424 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A
425 
426 			<legal 0>
427 */
428 #define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_OFFSET        0x00000034
429 #define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_LSB           0
430 #define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_MASK          0xffffffff
431 
432 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A
433 
434 			<legal 0>
435 */
436 #define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_OFFSET        0x00000038
437 #define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_LSB           0
438 #define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_MASK          0xffffffff
439 
440 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A
441 
442 			<legal 0>
443 */
444 #define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_OFFSET        0x0000003c
445 #define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_LSB           0
446 #define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_MASK          0xffffffff
447 
448 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A
449 
450 			<legal 0>
451 */
452 #define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_OFFSET        0x00000040
453 #define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_LSB           0
454 #define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_MASK          0xffffffff
455 
456 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A
457 
458 			<legal 0>
459 */
460 #define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_OFFSET        0x00000044
461 #define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_LSB           0
462 #define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_MASK          0xffffffff
463 
464 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A
465 
466 			<legal 0>
467 */
468 #define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_OFFSET        0x00000048
469 #define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_LSB           0
470 #define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_MASK          0xffffffff
471 
472 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A
473 
474 			<legal 0>
475 */
476 #define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_OFFSET        0x0000004c
477 #define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_LSB           0
478 #define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_MASK          0xffffffff
479 
480 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A
481 
482 			<legal 0>
483 */
484 #define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_OFFSET        0x00000050
485 #define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_LSB           0
486 #define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_MASK          0xffffffff
487 
488 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A
489 
490 			<legal 0>
491 */
492 #define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_OFFSET        0x00000054
493 #define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_LSB           0
494 #define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_MASK          0xffffffff
495 
496 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A
497 
498 			<legal 0>
499 */
500 #define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_OFFSET        0x00000058
501 #define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_LSB           0
502 #define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_MASK          0xffffffff
503 
504 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A
505 
506 			<legal 0>
507 */
508 #define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_OFFSET        0x0000005c
509 #define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_LSB           0
510 #define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_MASK          0xffffffff
511 
512 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A
513 
514 			<legal 0>
515 */
516 #define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_OFFSET        0x00000060
517 #define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_LSB           0
518 #define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_MASK          0x0fffffff
519 
520 /* Description		REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT
521 
522 			A count value that indicates the number of times the
523 			producer of entries into this Ring has looped around the
524 			ring.
525 
526 			At initialization time, this value is set to 0. On the
527 			first loop, this value is set to 1. After the max value is
528 			reached allowed by the number of bits for this field, the
529 			count value continues with 0 again.
530 
531 
532 
533 			In case SW is the consumer of the ring entries, it can
534 			use this field to figure out up to where the producer of
535 			entries has created new entries. This eliminates the need to
536 			check where the head pointer' of the ring is located once
537 			the SW starts processing an interrupt indicating that new
538 			entries have been put into this ring...
539 
540 
541 
542 			Also note that SW if it wants only needs to look at the
543 			LSB bit of this count value.
544 
545 			<legal all>
546 */
547 #define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_OFFSET       0x00000060
548 #define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_LSB          28
549 #define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_MASK         0xf0000000
550 
551 
552 #endif // _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
553