xref: /wlan-driver/fw-api/hw/qca8074/v2/rx_mpdu_info.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2020 The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 // $ATH_LICENSE_HW_HDR_C$
18 //
19 // DO NOT EDIT!  This file is automatically generated
20 //               These definitions are tied to a particular hardware layout
21 
22 
23 #ifndef _RX_MPDU_INFO_H_
24 #define _RX_MPDU_INFO_H_
25 #if !defined(__ASSEMBLER__)
26 #endif
27 
28 #include "rxpt_classify_info.h"
29 
30 // ################ START SUMMARY #################
31 //
32 //	Dword	Fields
33 //	0	rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], ndp_frame[9], phy_err[10], phy_err_during_mpdu_header[11], protocol_version_err[12], ast_based_lookup_valid[13], reserved_0a[15:14], phy_ppdu_id[31:16]
34 //	1	ast_index[15:0], sw_peer_id[31:16]
35 //	2	mpdu_frame_control_valid[0], mpdu_duration_valid[1], mac_addr_ad1_valid[2], mac_addr_ad2_valid[3], mac_addr_ad3_valid[4], mac_addr_ad4_valid[5], mpdu_sequence_control_valid[6], mpdu_qos_control_valid[7], mpdu_ht_control_valid[8], frame_encryption_info_valid[9], mpdu_fragment_number[13:10], more_fragment_flag[14], reserved_2a[15], fr_ds[16], to_ds[17], encrypted[18], mpdu_retry[19], mpdu_sequence_number[31:20]
36 //	3	epd_en[0], all_frames_shall_be_encrypted[1], encrypt_type[5:2], wep_key_width_for_variable_key[7:6], mesh_sta[8], bssid_hit[9], bssid_number[13:10], tid[17:14], reserved_3a[31:18]
37 //	4	pn_31_0[31:0]
38 //	5	pn_63_32[31:0]
39 //	6	pn_95_64[31:0]
40 //	7	pn_127_96[31:0]
41 //	8	peer_meta_data[31:0]
42 //	9	struct rxpt_classify_info rxpt_classify_info_details;
43 //	10	rx_reo_queue_desc_addr_31_0[31:0]
44 //	11	rx_reo_queue_desc_addr_39_32[7:0], receive_queue_number[23:8], pre_delim_err_warning[24], first_delim_err[25], reserved_11[31:26]
45 //	12	key_id_octet[7:0], new_peer_entry[8], decrypt_needed[9], decap_type[11:10], rx_insert_vlan_c_tag_padding[12], rx_insert_vlan_s_tag_padding[13], strip_vlan_c_tag_decap[14], strip_vlan_s_tag_decap[15], pre_delim_count[27:16], ampdu_flag[28], bar_frame[29], reserved_12[31:30]
46 //	13	mpdu_length[13:0], first_mpdu[14], mcast_bcast[15], ast_index_not_found[16], ast_index_timeout[17], power_mgmt[18], non_qos[19], null_data[20], mgmt_type[21], ctrl_type[22], more_data[23], eosp[24], fragment_flag[25], order[26], u_apsd_trigger[27], encrypt_required[28], directed[29], reserved_13[31:30]
47 //	14	mpdu_frame_control_field[15:0], mpdu_duration_field[31:16]
48 //	15	mac_addr_ad1_31_0[31:0]
49 //	16	mac_addr_ad1_47_32[15:0], mac_addr_ad2_15_0[31:16]
50 //	17	mac_addr_ad2_47_16[31:0]
51 //	18	mac_addr_ad3_31_0[31:0]
52 //	19	mac_addr_ad3_47_32[15:0], mpdu_sequence_control_field[31:16]
53 //	20	mac_addr_ad4_31_0[31:0]
54 //	21	mac_addr_ad4_47_32[15:0], mpdu_qos_control_field[31:16]
55 //	22	mpdu_ht_control_field[31:0]
56 //
57 // ################ END SUMMARY #################
58 
59 #define NUM_OF_DWORDS_RX_MPDU_INFO 23
60 
61 struct rx_mpdu_info {
62              uint32_t rxpcu_mpdu_filter_in_category   :  2, //[1:0]
63                       sw_frame_group_id               :  7, //[8:2]
64                       ndp_frame                       :  1, //[9]
65                       phy_err                         :  1, //[10]
66                       phy_err_during_mpdu_header      :  1, //[11]
67                       protocol_version_err            :  1, //[12]
68                       ast_based_lookup_valid          :  1, //[13]
69                       reserved_0a                     :  2, //[15:14]
70                       phy_ppdu_id                     : 16; //[31:16]
71              uint32_t ast_index                       : 16, //[15:0]
72                       sw_peer_id                      : 16; //[31:16]
73              uint32_t mpdu_frame_control_valid        :  1, //[0]
74                       mpdu_duration_valid             :  1, //[1]
75                       mac_addr_ad1_valid              :  1, //[2]
76                       mac_addr_ad2_valid              :  1, //[3]
77                       mac_addr_ad3_valid              :  1, //[4]
78                       mac_addr_ad4_valid              :  1, //[5]
79                       mpdu_sequence_control_valid     :  1, //[6]
80                       mpdu_qos_control_valid          :  1, //[7]
81                       mpdu_ht_control_valid           :  1, //[8]
82                       frame_encryption_info_valid     :  1, //[9]
83                       mpdu_fragment_number            :  4, //[13:10]
84                       more_fragment_flag              :  1, //[14]
85                       reserved_2a                     :  1, //[15]
86                       fr_ds                           :  1, //[16]
87                       to_ds                           :  1, //[17]
88                       encrypted                       :  1, //[18]
89                       mpdu_retry                      :  1, //[19]
90                       mpdu_sequence_number            : 12; //[31:20]
91              uint32_t epd_en                          :  1, //[0]
92                       all_frames_shall_be_encrypted   :  1, //[1]
93                       encrypt_type                    :  4, //[5:2]
94                       wep_key_width_for_variable_key  :  2, //[7:6]
95                       mesh_sta                        :  1, //[8]
96                       bssid_hit                       :  1, //[9]
97                       bssid_number                    :  4, //[13:10]
98                       tid                             :  4, //[17:14]
99                       reserved_3a                     : 14; //[31:18]
100              uint32_t pn_31_0                         : 32; //[31:0]
101              uint32_t pn_63_32                        : 32; //[31:0]
102              uint32_t pn_95_64                        : 32; //[31:0]
103              uint32_t pn_127_96                       : 32; //[31:0]
104              uint32_t peer_meta_data                  : 32; //[31:0]
105     struct            rxpt_classify_info                       rxpt_classify_info_details;
106              uint32_t rx_reo_queue_desc_addr_31_0     : 32; //[31:0]
107              uint32_t rx_reo_queue_desc_addr_39_32    :  8, //[7:0]
108                       receive_queue_number            : 16, //[23:8]
109                       pre_delim_err_warning           :  1, //[24]
110                       first_delim_err                 :  1, //[25]
111                       reserved_11                     :  6; //[31:26]
112              uint32_t key_id_octet                    :  8, //[7:0]
113                       new_peer_entry                  :  1, //[8]
114                       decrypt_needed                  :  1, //[9]
115                       decap_type                      :  2, //[11:10]
116                       rx_insert_vlan_c_tag_padding    :  1, //[12]
117                       rx_insert_vlan_s_tag_padding    :  1, //[13]
118                       strip_vlan_c_tag_decap          :  1, //[14]
119                       strip_vlan_s_tag_decap          :  1, //[15]
120                       pre_delim_count                 : 12, //[27:16]
121                       ampdu_flag                      :  1, //[28]
122                       bar_frame                       :  1, //[29]
123                       reserved_12                     :  2; //[31:30]
124              uint32_t mpdu_length                     : 14, //[13:0]
125                       first_mpdu                      :  1, //[14]
126                       mcast_bcast                     :  1, //[15]
127                       ast_index_not_found             :  1, //[16]
128                       ast_index_timeout               :  1, //[17]
129                       power_mgmt                      :  1, //[18]
130                       non_qos                         :  1, //[19]
131                       null_data                       :  1, //[20]
132                       mgmt_type                       :  1, //[21]
133                       ctrl_type                       :  1, //[22]
134                       more_data                       :  1, //[23]
135                       eosp                            :  1, //[24]
136                       fragment_flag                   :  1, //[25]
137                       order                           :  1, //[26]
138                       u_apsd_trigger                  :  1, //[27]
139                       encrypt_required                :  1, //[28]
140                       directed                        :  1, //[29]
141                       reserved_13                     :  2; //[31:30]
142              uint32_t mpdu_frame_control_field        : 16, //[15:0]
143                       mpdu_duration_field             : 16; //[31:16]
144              uint32_t mac_addr_ad1_31_0               : 32; //[31:0]
145              uint32_t mac_addr_ad1_47_32              : 16, //[15:0]
146                       mac_addr_ad2_15_0               : 16; //[31:16]
147              uint32_t mac_addr_ad2_47_16              : 32; //[31:0]
148              uint32_t mac_addr_ad3_31_0               : 32; //[31:0]
149              uint32_t mac_addr_ad3_47_32              : 16, //[15:0]
150                       mpdu_sequence_control_field     : 16; //[31:16]
151              uint32_t mac_addr_ad4_31_0               : 32; //[31:0]
152              uint32_t mac_addr_ad4_47_32              : 16, //[15:0]
153                       mpdu_qos_control_field          : 16; //[31:16]
154              uint32_t mpdu_ht_control_field           : 32; //[31:0]
155 };
156 
157 /*
158 
159 rxpcu_mpdu_filter_in_category
160 
161 			Field indicates what the reason was that this MPDU frame
162 			was allowed to come into the receive path by RXPCU
163 
164 			<enum 0 rxpcu_filter_pass> This MPDU passed the normal
165 			frame filter programming of rxpcu
166 
167 			<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
168 			regular frame filter and would have been dropped, were it
169 			not for the frame fitting into the 'monitor_client'
170 			category.
171 
172 			<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
173 			regular frame filter and also did not pass the
174 			rxpcu_monitor_client filter. It would have been dropped
175 			accept that it did pass the 'monitor_other' category.
176 
177 
178 
179 			Note: for ndp frame, if it was expected because the
180 			preceding NDPA was filter_pass, the setting
181 			rxpcu_filter_pass will be used. This setting will also be
182 			used for every ndp frame in case Promiscuous mode is
183 			enabled.
184 
185 
186 
187 			In case promiscuous is not enabled, and an NDP is not
188 			preceded by a NPDA filter pass frame, the only other setting
189 			that could appear here for the NDP is rxpcu_monitor_other.
190 
191 			(rxpcu has a configuration bit specifically for this
192 			scenario)
193 
194 
195 
196 			Note: for
197 
198 			<legal 0-2>
199 
200 sw_frame_group_id
201 
202 			SW processes frames based on certain classifications.
203 			This field indicates to what sw classification this MPDU is
204 			mapped.
205 
206 			The classification is given in priority order
207 
208 
209 
210 			<enum 0 sw_frame_group_NDP_frame> Note: The
211 			corresponding Rxpcu_Mpdu_filter_in_category can be
212 			rxpcu_filter_pass or rxpcu_monitor_other
213 
214 
215 
216 			<enum 1 sw_frame_group_Multicast_data>
217 
218 			<enum 2 sw_frame_group_Unicast_data>
219 
220 			<enum 3 sw_frame_group_Null_data > This includes mpdus
221 			of type Data Null as well as QoS Data Null
222 
223 
224 
225 			<enum 4 sw_frame_group_mgmt_0000 >
226 
227 			<enum 5 sw_frame_group_mgmt_0001 >
228 
229 			<enum 6 sw_frame_group_mgmt_0010 >
230 
231 			<enum 7 sw_frame_group_mgmt_0011 >
232 
233 			<enum 8 sw_frame_group_mgmt_0100 >
234 
235 			<enum 9 sw_frame_group_mgmt_0101 >
236 
237 			<enum 10 sw_frame_group_mgmt_0110 >
238 
239 			<enum 11 sw_frame_group_mgmt_0111 >
240 
241 			<enum 12 sw_frame_group_mgmt_1000 >
242 
243 			<enum 13 sw_frame_group_mgmt_1001 >
244 
245 			<enum 14 sw_frame_group_mgmt_1010 >
246 
247 			<enum 15 sw_frame_group_mgmt_1011 >
248 
249 			<enum 16 sw_frame_group_mgmt_1100 >
250 
251 			<enum 17 sw_frame_group_mgmt_1101 >
252 
253 			<enum 18 sw_frame_group_mgmt_1110 >
254 
255 			<enum 19 sw_frame_group_mgmt_1111 >
256 
257 
258 
259 			<enum 20 sw_frame_group_ctrl_0000 >
260 
261 			<enum 21 sw_frame_group_ctrl_0001 >
262 
263 			<enum 22 sw_frame_group_ctrl_0010 >
264 
265 			<enum 23 sw_frame_group_ctrl_0011 >
266 
267 			<enum 24 sw_frame_group_ctrl_0100 >
268 
269 			<enum 25 sw_frame_group_ctrl_0101 >
270 
271 			<enum 26 sw_frame_group_ctrl_0110 >
272 
273 			<enum 27 sw_frame_group_ctrl_0111 >
274 
275 			<enum 28 sw_frame_group_ctrl_1000 >
276 
277 			<enum 29 sw_frame_group_ctrl_1001 >
278 
279 			<enum 30 sw_frame_group_ctrl_1010 >
280 
281 			<enum 31 sw_frame_group_ctrl_1011 >
282 
283 			<enum 32 sw_frame_group_ctrl_1100 >
284 
285 			<enum 33 sw_frame_group_ctrl_1101 >
286 
287 			<enum 34 sw_frame_group_ctrl_1110 >
288 
289 			<enum 35 sw_frame_group_ctrl_1111 >
290 
291 
292 
293 			<enum 36 sw_frame_group_unsupported> This covers type 3
294 			and protocol version != 0
295 
296 			Note: The corresponding Rxpcu_Mpdu_filter_in_category
297 			can only be rxpcu_monitor_other
298 
299 
300 
301 
302 			Note: The corresponding Rxpcu_Mpdu_filter_in_category
303 			can be rxpcu_filter_pass
304 
305 
306 
307 			<legal 0-37>
308 
309 ndp_frame
310 
311 			When set, the received frame was an NDP frame, and thus
312 			there will be no MPDU data.
313 
314 			<legal all>
315 
316 phy_err
317 
318 			When set, a PHY error was received before MAC received
319 			any data, and thus there will be no MPDU data.
320 
321 			<legal all>
322 
323 phy_err_during_mpdu_header
324 
325 			When set, a PHY error was received before MAC received
326 			the complete MPDU header which was needed for proper
327 			decoding
328 
329 			<legal all>
330 
331 protocol_version_err
332 
333 			Set when RXPCU detected a version error in the Frame
334 			control field
335 
336 			<legal all>
337 
338 ast_based_lookup_valid
339 
340 			When set, AST based lookup for this frame has found a
341 			valid result.
342 
343 
344 
345 			Note that for NDP frame this will never be set
346 
347 			<legal all>
348 
349 reserved_0a
350 
351 			<legal 0>
352 
353 phy_ppdu_id
354 
355 			A ppdu counter value that PHY increments for every PPDU
356 			received. The counter value wraps around
357 
358 			<legal all>
359 
360 ast_index
361 
362 			This field indicates the index of the AST entry
363 			corresponding to this MPDU. It is provided by the GSE module
364 			instantiated in RXPCU.
365 
366 			A value of 0xFFFF indicates an invalid AST index,
367 			meaning that No AST entry was found or NO AST search was
368 			performed
369 
370 
371 
372 			In case of ndp or phy_err, this field will be set to
373 			0xFFFF
374 
375 			<legal all>
376 
377 sw_peer_id
378 
379 			In case of ndp or phy_err or AST_based_lookup_valid ==
380 			0, this field will be set to 0
381 
382 
383 
384 			This field indicates a unique peer identifier. It is set
385 			equal to field 'sw_peer_id' from the AST entry
386 
387 
388 
389 			<legal all>
390 
391 mpdu_frame_control_valid
392 
393 			When set, the field Mpdu_Frame_control_field has valid
394 			information
395 
396 
397 
398 
399 			<legal all>
400 
401 mpdu_duration_valid
402 
403 			When set, the field Mpdu_duration_field has valid
404 			information
405 
406 
407 
408 
409 			<legal all>
410 
411 mac_addr_ad1_valid
412 
413 			When set, the fields mac_addr_ad1_..... have valid
414 			information
415 
416 
417 
418 
419 			<legal all>
420 
421 mac_addr_ad2_valid
422 
423 			When set, the fields mac_addr_ad2_..... have valid
424 			information
425 
426 
427 
428 
429 
430 
431 
432 			<legal all>
433 
434 mac_addr_ad3_valid
435 
436 			When set, the fields mac_addr_ad3_..... have valid
437 			information
438 
439 
440 
441 
442 
443 
444 
445 			<legal all>
446 
447 mac_addr_ad4_valid
448 
449 			When set, the fields mac_addr_ad4_..... have valid
450 			information
451 
452 
453 
454 
455 
456 
457 
458 			<legal all>
459 
460 mpdu_sequence_control_valid
461 
462 			When set, the fields mpdu_sequence_control_field and
463 			mpdu_sequence_number have valid information as well as field
464 
465 
466 
467 			For MPDUs without a sequence control field, this field
468 			will not be set.
469 
470 
471 
472 
473 			<legal all>
474 
475 mpdu_qos_control_valid
476 
477 			When set, the field mpdu_qos_control_field has valid
478 			information
479 
480 
481 
482 			For MPDUs without a QoS control field, this field will
483 			not be set.
484 
485 
486 
487 
488 			<legal all>
489 
490 mpdu_ht_control_valid
491 
492 			When set, the field mpdu_HT_control_field has valid
493 			information
494 
495 
496 
497 			For MPDUs without a HT control field, this field will
498 			not be set.
499 
500 
501 
502 
503 			<legal all>
504 
505 frame_encryption_info_valid
506 
507 			When set, the encryption related info fields, like IV
508 			and PN are valid
509 
510 
511 
512 			For MPDUs that are not encrypted, this will not be set.
513 
514 
515 
516 
517 			<legal all>
518 
519 mpdu_fragment_number
520 
521 			Field only valid when Mpdu_sequence_control_valid is set
522 			AND Fragment_flag is set
523 
524 
525 
526 			The fragment number from the 802.11 header.
527 
528 			<legal all>
529 
530 more_fragment_flag
531 
532 			The More Fragment bit setting from the MPDU header of
533 			the received frame
534 
535 
536 
537 			<legal all>
538 
539 reserved_2a
540 
541 			<legal 0>
542 
543 fr_ds
544 
545 			Field only valid when Mpdu_frame_control_valid is set
546 
547 
548 
549 			Set if the from DS bit is set in the frame control.
550 
551 			<legal all>
552 
553 to_ds
554 
555 			Field only valid when Mpdu_frame_control_valid is set
556 
557 
558 
559 			Set if the to DS bit is set in the frame control.
560 
561 			<legal all>
562 
563 encrypted
564 
565 			Field only valid when Mpdu_frame_control_valid is set.
566 
567 
568 
569 			Protected bit from the frame control.
570 
571 			<legal all>
572 
573 mpdu_retry
574 
575 			Field only valid when Mpdu_frame_control_valid is set.
576 
577 
578 
579 			Retry bit from the frame control.  Only valid when
580 			first_msdu is set.
581 
582 			<legal all>
583 
584 mpdu_sequence_number
585 
586 			Field only valid when Mpdu_sequence_control_valid is
587 			set.
588 
589 
590 
591 			The sequence number from the 802.11 header.
592 
593 			<legal all>
594 
595 epd_en
596 
597 			Field only valid when AST_based_lookup_valid == 1.
598 
599 
600 
601 
602 
603 			In case of ndp or phy_err or AST_based_lookup_valid ==
604 			0, this field will be set to 0
605 
606 
607 
608 			If set to one use EPD instead of LPD
609 
610 
611 
612 
613 			<legal all>
614 
615 all_frames_shall_be_encrypted
616 
617 			In case of ndp or phy_err or AST_based_lookup_valid ==
618 			0, this field will be set to 0
619 
620 
621 
622 			When set, all frames (data only ?) shall be encrypted.
623 			If not, RX CRYPTO shall set an error flag.
624 
625 			<legal all>
626 
627 encrypt_type
628 
629 			In case of ndp or phy_err or AST_based_lookup_valid ==
630 			0, this field will be set to 0
631 
632 
633 
634 			Indicates type of decrypt cipher used (as defined in the
635 			peer entry)
636 
637 
638 
639 			<enum 0 wep_40> WEP 40-bit
640 
641 			<enum 1 wep_104> WEP 104-bit
642 
643 			<enum 2 tkip_no_mic> TKIP without MIC
644 
645 			<enum 3 wep_128> WEP 128-bit
646 
647 			<enum 4 tkip_with_mic> TKIP with MIC
648 
649 			<enum 5 wapi> WAPI
650 
651 			<enum 6 aes_ccmp_128> AES CCMP 128
652 
653 			<enum 7 no_cipher> No crypto
654 
655 			<enum 8 aes_ccmp_256> AES CCMP 256
656 
657 			<enum 9 aes_gcmp_128> AES CCMP 128
658 
659 			<enum 10 aes_gcmp_256> AES CCMP 256
660 
661 			<enum 11 wapi_gcm_sm4> WAPI GCM SM4
662 
663 
664 
665 			<enum 12 wep_varied_width> WEP encryption. As for WEP
666 			per keyid the key bit width can vary, the key bit width for
667 			this MPDU will be indicated in field
668 			wep_key_width_for_variable key
669 
670 			<legal 0-12>
671 
672 wep_key_width_for_variable_key
673 
674 			Field only valid when key_type is set to
675 			wep_varied_width.
676 
677 
678 
679 			This field indicates the size of the wep key for this
680 			MPDU.
681 
682 
683 
684 			<enum 0 wep_varied_width_40> WEP 40-bit
685 
686 			<enum 1 wep_varied_width_104> WEP 104-bit
687 
688 			<enum 2 wep_varied_width_128> WEP 128-bit
689 
690 
691 
692 			<legal 0-2>
693 
694 mesh_sta
695 
696 			In case of ndp or phy_err or AST_based_lookup_valid ==
697 			0, this field will be set to 0
698 
699 
700 
701 			When set, this is a Mesh (11s) STA
702 
703 			<legal all>
704 
705 bssid_hit
706 
707 			In case of ndp or phy_err or AST_based_lookup_valid ==
708 			0, this field will be set to 0
709 
710 
711 
712 			When set, the BSSID of the incoming frame matched one of
713 			the 8 BSSID register values
714 
715 
716 
717 			<legal all>
718 
719 bssid_number
720 
721 			Field only valid when bssid_hit is set.
722 
723 
724 
725 			This number indicates which one out of the 8 BSSID
726 			register values matched the incoming frame
727 
728 			<legal all>
729 
730 tid
731 
732 			Field only valid when mpdu_qos_control_valid is set
733 
734 
735 
736 			The TID field in the QoS control field
737 
738 			<legal all>
739 
740 reserved_3a
741 
742 			<legal 0>
743 
744 pn_31_0
745 
746 
747 
748 
749 
750 			WEP: IV = {key_id_octet, pn2, pn1, pn0}.  Only pn[23:0]
751 			is valid.
752 
753 			TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0,
754 			WEPSeed[1], pn1}.  Only pn[47:0] is valid.
755 
756 			AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0,
757 			pn1, pn0}.  Only pn[47:0] is valid.
758 
759 			WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12,
760 			pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1,
761 			pn0}.  pn[127:0] are valid.
762 
763 
764 
765 
766 pn_63_32
767 
768 
769 
770 
771 			Bits [63:32] of the PN number.   See description for
772 			pn_31_0.
773 
774 
775 
776 
777 pn_95_64
778 
779 
780 
781 
782 			Bits [95:64] of the PN number.  See description for
783 			pn_31_0.
784 
785 
786 
787 
788 pn_127_96
789 
790 
791 
792 
793 			Bits [127:96] of the PN number.  See description for
794 			pn_31_0.
795 
796 
797 
798 
799 peer_meta_data
800 
801 			In case of ndp or phy_err or AST_based_lookup_valid ==
802 			0, this field will be set to 0
803 
804 
805 
806 			Meta data that SW has programmed in the Peer table entry
807 			of the transmitting STA.
808 
809 			<legal all>
810 
811 struct rxpt_classify_info rxpt_classify_info_details
812 
813 			In case of ndp or phy_err or AST_based_lookup_valid ==
814 			0, this field will be set to 0
815 
816 
817 
818 			RXOLE related classification info
819 
820 			<legal all
821 
822 rx_reo_queue_desc_addr_31_0
823 
824 			In case of ndp or phy_err or AST_based_lookup_valid ==
825 			0, this field will be set to 0
826 
827 
828 
829 			Address (lower 32 bits) of the REO queue descriptor.
830 
831 
832 
833 			If no Peer entry lookup happened for this frame, the
834 			value wil be set to 0, and the frame shall never be pushed
835 			to REO entrance ring.
836 
837 			<legal all>
838 
839 rx_reo_queue_desc_addr_39_32
840 
841 			In case of ndp or phy_err or AST_based_lookup_valid ==
842 			0, this field will be set to 0
843 
844 
845 
846 			Address (upper 8 bits) of the REO queue descriptor.
847 
848 
849 
850 			If no Peer entry lookup happened for this frame, the
851 			value wil be set to 0, and the frame shall never be pushed
852 			to REO entrance ring.
853 
854 			<legal all>
855 
856 receive_queue_number
857 
858 			In case of ndp or phy_err or AST_based_lookup_valid ==
859 			0, this field will be set to 0
860 
861 
862 
863 			Indicates the MPDU queue ID to which this MPDU link
864 			descriptor belongs
865 
866 			Used for tracking and debugging
867 
868 			<legal all>
869 
870 pre_delim_err_warning
871 
872 			Indicates that a delimiter FCS error was found in
873 			between the Previous MPDU and this MPDU.
874 
875 
876 
877 			Note that this is just a warning, and does not mean that
878 			this MPDU is corrupted in any way. If it is, there will be
879 			other errors indicated such as FCS or decrypt errors
880 
881 
882 
883 			In case of ndp or phy_err, this field will indicate at
884 			least one of delimiters located after the last MPDU in the
885 			previous PPDU has been corrupted.
886 
887 first_delim_err
888 
889 			Indicates that the first delimiter had a FCS failure.
890 			Only valid when first_mpdu and first_msdu are set.
891 
892 
893 
894 
895 reserved_11
896 
897 			<legal 0>
898 
899 key_id_octet
900 
901 
902 
903 
904 			The key ID octet from the IV.
905 
906 
907 
908 			In case of ndp or phy_err or AST_based_lookup_valid ==
909 			0, this field will be set to 0
910 
911 			<legal all>
912 
913 new_peer_entry
914 
915 			In case of ndp or phy_err or AST_based_lookup_valid ==
916 			0, this field will be set to 0
917 
918 
919 
920 			Set if new RX_PEER_ENTRY TLV follows. If clear,
921 			RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either
922 			uses old peer entry or not decrypt.
923 
924 			<legal all>
925 
926 decrypt_needed
927 
928 			In case of ndp or phy_err or AST_based_lookup_valid ==
929 			0, this field will be set to 0
930 
931 
932 
933 			Set if decryption is needed.
934 
935 
936 
937 			Note:
938 
939 			When RXPCU sets bit 'ast_index_not_found' and/or
940 			ast_index_timeout', RXPCU will also ensure that this bit is
941 			NOT set
942 
943 			CRYPTO for that reason only needs to evaluate this bit
944 			and non of the other ones.
945 
946 			<legal all>
947 
948 decap_type
949 
950 			In case of ndp or phy_err or AST_based_lookup_valid ==
951 			0, this field will be set to 0
952 
953 
954 
955 			Used by the OLE during decapsulation.
956 
957 
958 
959 			Indicates the decapsulation that HW will perform:
960 
961 
962 
963 			<enum 0 RAW> No encapsulation
964 
965 			<enum 1 Native_WiFi>
966 
967 			<enum 2 Ethernet> Ethernet 2 (DIX)  or 802.3 (uses
968 			SNAP/LLC)
969 
970 			<enum 3 802_3> Indicate Ethernet
971 
972 
973 
974 			<legal all>
975 
976 rx_insert_vlan_c_tag_padding
977 
978 			In case of ndp or phy_err or AST_based_lookup_valid ==
979 			0, this field will be set to 0
980 
981 
982 
983 			Insert 4 byte of all zeros as VLAN tag if the rx payload
984 			does not have VLAN. Used during decapsulation.
985 
986 			<legal all>
987 
988 rx_insert_vlan_s_tag_padding
989 
990 			In case of ndp or phy_err or AST_based_lookup_valid ==
991 			0, this field will be set to 0
992 
993 
994 
995 			Insert 4 byte of all zeros as double VLAN tag if the rx
996 			payload does not have VLAN. Used during
997 
998 			<legal all>
999 
1000 strip_vlan_c_tag_decap
1001 
1002 			In case of ndp or phy_err or AST_based_lookup_valid ==
1003 			0, this field will be set to 0
1004 
1005 
1006 
1007 			Strip the VLAN during decapsulation.  Used by the OLE.
1008 
1009 			<legal all>
1010 
1011 strip_vlan_s_tag_decap
1012 
1013 			In case of ndp or phy_err or AST_based_lookup_valid ==
1014 			0, this field will be set to 0
1015 
1016 
1017 
1018 			Strip the double VLAN during decapsulation.  Used by
1019 			the OLE.
1020 
1021 			<legal all>
1022 
1023 pre_delim_count
1024 
1025 			The number of delimiters before this MPDU.
1026 
1027 
1028 
1029 			Note that this number is cleared at PPDU start.
1030 
1031 
1032 
1033 			If this MPDU is the first received MPDU in the PPDU and
1034 			this MPDU gets filtered-in, this field will indicate the
1035 			number of delimiters located after the last MPDU in the
1036 			previous PPDU.
1037 
1038 
1039 
1040 			If this MPDU is located after the first received MPDU in
1041 			an PPDU, this field will indicate the number of delimiters
1042 			located between the previous MPDU and this MPDU.
1043 
1044 
1045 
1046 			In case of ndp or phy_err, this field will indicate the
1047 			number of delimiters located after the last MPDU in the
1048 			previous PPDU.
1049 
1050 			<legal all>
1051 
1052 ampdu_flag
1053 
1054 			When set, received frame was part of an A-MPDU.
1055 
1056 
1057 
1058 
1059 			<legal all>
1060 
1061 bar_frame
1062 
1063 			In case of ndp or phy_err or AST_based_lookup_valid ==
1064 			0, this field will be set to 0
1065 
1066 
1067 
1068 			When set, received frame is a BAR frame
1069 
1070 			<legal all>
1071 
1072 reserved_12
1073 
1074 			<legal 0>.
1075 
1076 mpdu_length
1077 
1078 			In case of ndp or phy_err this field will be set to 0
1079 
1080 
1081 
1082 			MPDU length before decapsulation.
1083 
1084 			<legal all>
1085 
1086 first_mpdu
1087 
1088 			See definition in RX attention descriptor
1089 
1090 
1091 
1092 			In case of ndp or phy_err, this field will be set. Note
1093 			however that there will not actually be any data contents in
1094 			the MPDU.
1095 
1096 			<legal all>
1097 
1098 mcast_bcast
1099 
1100 			In case of ndp or phy_err or Phy_err_during_mpdu_header
1101 			this field will be set to 0
1102 
1103 
1104 
1105 			See definition in RX attention descriptor
1106 
1107 			<legal all>
1108 
1109 ast_index_not_found
1110 
1111 			In case of ndp or phy_err or Phy_err_during_mpdu_header
1112 			this field will be set to 0
1113 
1114 
1115 
1116 			See definition in RX attention descriptor
1117 
1118 			<legal all>
1119 
1120 ast_index_timeout
1121 
1122 			In case of ndp or phy_err or Phy_err_during_mpdu_header
1123 			this field will be set to 0
1124 
1125 
1126 
1127 			See definition in RX attention descriptor
1128 
1129 			<legal all>
1130 
1131 power_mgmt
1132 
1133 			In case of ndp or phy_err or Phy_err_during_mpdu_header
1134 			this field will be set to 0
1135 
1136 
1137 
1138 			See definition in RX attention descriptor
1139 
1140 			<legal all>
1141 
1142 non_qos
1143 
1144 			In case of ndp or phy_err or Phy_err_during_mpdu_header
1145 			this field will be set to 1
1146 
1147 
1148 
1149 			See definition in RX attention descriptor
1150 
1151 			<legal all>
1152 
1153 null_data
1154 
1155 			In case of ndp or phy_err or Phy_err_during_mpdu_header
1156 			this field will be set to 0
1157 
1158 
1159 
1160 			See definition in RX attention descriptor
1161 
1162 			<legal all>
1163 
1164 mgmt_type
1165 
1166 			In case of ndp or phy_err or Phy_err_during_mpdu_header
1167 			this field will be set to 0
1168 
1169 
1170 
1171 			See definition in RX attention descriptor
1172 
1173 			<legal all>
1174 
1175 ctrl_type
1176 
1177 			In case of ndp or phy_err or Phy_err_during_mpdu_header
1178 			this field will be set to 0
1179 
1180 
1181 
1182 			See definition in RX attention descriptor
1183 
1184 			<legal all>
1185 
1186 more_data
1187 
1188 			In case of ndp or phy_err or Phy_err_during_mpdu_header
1189 			this field will be set to 0
1190 
1191 
1192 
1193 			See definition in RX attention descriptor
1194 
1195 			<legal all>
1196 
1197 eosp
1198 
1199 			In case of ndp or phy_err or Phy_err_during_mpdu_header
1200 			this field will be set to 0
1201 
1202 
1203 
1204 			See definition in RX attention descriptor
1205 
1206 			<legal all>
1207 
1208 fragment_flag
1209 
1210 			In case of ndp or phy_err or Phy_err_during_mpdu_header
1211 			this field will be set to 0
1212 
1213 
1214 
1215 			See definition in RX attention descriptor
1216 
1217 			<legal all>
1218 
1219 order
1220 
1221 			In case of ndp or phy_err or Phy_err_during_mpdu_header
1222 			this field will be set to 0
1223 
1224 
1225 
1226 			See definition in RX attention descriptor
1227 
1228 
1229 
1230 			<legal all>
1231 
1232 u_apsd_trigger
1233 
1234 			In case of ndp or phy_err or Phy_err_during_mpdu_header
1235 			this field will be set to 0
1236 
1237 
1238 
1239 			See definition in RX attention descriptor
1240 
1241 			<legal all>
1242 
1243 encrypt_required
1244 
1245 			In case of ndp or phy_err or Phy_err_during_mpdu_header
1246 			this field will be set to 0
1247 
1248 
1249 
1250 			See definition in RX attention descriptor
1251 
1252 			<legal all>
1253 
1254 directed
1255 
1256 			In case of ndp or phy_err or Phy_err_during_mpdu_header
1257 			this field will be set to 0
1258 
1259 
1260 
1261 			See definition in RX attention descriptor
1262 
1263 			<legal all>
1264 
1265 reserved_13
1266 
1267 			<legal 0>
1268 
1269 mpdu_frame_control_field
1270 
1271 			Field only valid when Mpdu_frame_control_valid is set
1272 
1273 
1274 
1275 			The frame control field of this received MPDU.
1276 
1277 
1278 
1279 			Field only valid when Ndp_frame and phy_err are NOT set
1280 
1281 
1282 
1283 			Bytes 0 + 1 of the received MPDU
1284 
1285 			<legal all>
1286 
1287 mpdu_duration_field
1288 
1289 			Field only valid when Mpdu_duration_valid is set
1290 
1291 
1292 
1293 			The duration field of this received MPDU.
1294 
1295 			<legal all>
1296 
1297 mac_addr_ad1_31_0
1298 
1299 			Field only valid when mac_addr_ad1_valid is set
1300 
1301 
1302 
1303 			The Least Significant 4 bytes of the Received Frames MAC
1304 			Address AD1
1305 
1306 			<legal all>
1307 
1308 mac_addr_ad1_47_32
1309 
1310 			Field only valid when mac_addr_ad1_valid is set
1311 
1312 
1313 
1314 			The 2 most significant bytes of the Received Frames MAC
1315 			Address AD1
1316 
1317 			<legal all>
1318 
1319 mac_addr_ad2_15_0
1320 
1321 			Field only valid when mac_addr_ad2_valid is set
1322 
1323 
1324 
1325 			The Least Significant 2 bytes of the Received Frames MAC
1326 			Address AD2
1327 
1328 			<legal all>
1329 
1330 mac_addr_ad2_47_16
1331 
1332 			Field only valid when mac_addr_ad2_valid is set
1333 
1334 
1335 
1336 			The 4 most significant bytes of the Received Frames MAC
1337 			Address AD2
1338 
1339 			<legal all>
1340 
1341 mac_addr_ad3_31_0
1342 
1343 			Field only valid when mac_addr_ad3_valid is set
1344 
1345 
1346 
1347 			The Least Significant 4 bytes of the Received Frames MAC
1348 			Address AD3
1349 
1350 			<legal all>
1351 
1352 mac_addr_ad3_47_32
1353 
1354 			Field only valid when mac_addr_ad3_valid is set
1355 
1356 
1357 
1358 			The 2 most significant bytes of the Received Frames MAC
1359 			Address AD3
1360 
1361 			<legal all>
1362 
1363 mpdu_sequence_control_field
1364 
1365 
1366 
1367 
1368 			The sequence control field of the MPDU
1369 
1370 			<legal all>
1371 
1372 mac_addr_ad4_31_0
1373 
1374 			Field only valid when mac_addr_ad4_valid is set
1375 
1376 
1377 
1378 			The Least Significant 4 bytes of the Received Frames MAC
1379 			Address AD4
1380 
1381 			<legal all>
1382 
1383 mac_addr_ad4_47_32
1384 
1385 			Field only valid when mac_addr_ad4_valid is set
1386 
1387 
1388 
1389 			The 2 most significant bytes of the Received Frames MAC
1390 			Address AD4
1391 
1392 			<legal all>
1393 
1394 mpdu_qos_control_field
1395 
1396 			Field only valid when mpdu_qos_control_valid is set
1397 
1398 
1399 
1400 			The sequence control field of the MPDU
1401 
1402 			<legal all>
1403 
1404 mpdu_ht_control_field
1405 
1406 			Field only valid when mpdu_qos_control_valid is set
1407 
1408 
1409 
1410 			The HT control field of the MPDU
1411 
1412 			<legal all>
1413 */
1414 
1415 
1416 /* Description		RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY
1417 
1418 			Field indicates what the reason was that this MPDU frame
1419 			was allowed to come into the receive path by RXPCU
1420 
1421 			<enum 0 rxpcu_filter_pass> This MPDU passed the normal
1422 			frame filter programming of rxpcu
1423 
1424 			<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
1425 			regular frame filter and would have been dropped, were it
1426 			not for the frame fitting into the 'monitor_client'
1427 			category.
1428 
1429 			<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
1430 			regular frame filter and also did not pass the
1431 			rxpcu_monitor_client filter. It would have been dropped
1432 			accept that it did pass the 'monitor_other' category.
1433 
1434 
1435 
1436 			Note: for ndp frame, if it was expected because the
1437 			preceding NDPA was filter_pass, the setting
1438 			rxpcu_filter_pass will be used. This setting will also be
1439 			used for every ndp frame in case Promiscuous mode is
1440 			enabled.
1441 
1442 
1443 
1444 			In case promiscuous is not enabled, and an NDP is not
1445 			preceded by a NPDA filter pass frame, the only other setting
1446 			that could appear here for the NDP is rxpcu_monitor_other.
1447 
1448 			(rxpcu has a configuration bit specifically for this
1449 			scenario)
1450 
1451 
1452 
1453 			Note: for
1454 
1455 			<legal 0-2>
1456 */
1457 #define RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET          0x00000000
1458 #define RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB             0
1459 #define RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK            0x00000003
1460 
1461 /* Description		RX_MPDU_INFO_0_SW_FRAME_GROUP_ID
1462 
1463 			SW processes frames based on certain classifications.
1464 			This field indicates to what sw classification this MPDU is
1465 			mapped.
1466 
1467 			The classification is given in priority order
1468 
1469 
1470 
1471 			<enum 0 sw_frame_group_NDP_frame> Note: The
1472 			corresponding Rxpcu_Mpdu_filter_in_category can be
1473 			rxpcu_filter_pass or rxpcu_monitor_other
1474 
1475 
1476 
1477 			<enum 1 sw_frame_group_Multicast_data>
1478 
1479 			<enum 2 sw_frame_group_Unicast_data>
1480 
1481 			<enum 3 sw_frame_group_Null_data > This includes mpdus
1482 			of type Data Null as well as QoS Data Null
1483 
1484 
1485 
1486 			<enum 4 sw_frame_group_mgmt_0000 >
1487 
1488 			<enum 5 sw_frame_group_mgmt_0001 >
1489 
1490 			<enum 6 sw_frame_group_mgmt_0010 >
1491 
1492 			<enum 7 sw_frame_group_mgmt_0011 >
1493 
1494 			<enum 8 sw_frame_group_mgmt_0100 >
1495 
1496 			<enum 9 sw_frame_group_mgmt_0101 >
1497 
1498 			<enum 10 sw_frame_group_mgmt_0110 >
1499 
1500 			<enum 11 sw_frame_group_mgmt_0111 >
1501 
1502 			<enum 12 sw_frame_group_mgmt_1000 >
1503 
1504 			<enum 13 sw_frame_group_mgmt_1001 >
1505 
1506 			<enum 14 sw_frame_group_mgmt_1010 >
1507 
1508 			<enum 15 sw_frame_group_mgmt_1011 >
1509 
1510 			<enum 16 sw_frame_group_mgmt_1100 >
1511 
1512 			<enum 17 sw_frame_group_mgmt_1101 >
1513 
1514 			<enum 18 sw_frame_group_mgmt_1110 >
1515 
1516 			<enum 19 sw_frame_group_mgmt_1111 >
1517 
1518 
1519 
1520 			<enum 20 sw_frame_group_ctrl_0000 >
1521 
1522 			<enum 21 sw_frame_group_ctrl_0001 >
1523 
1524 			<enum 22 sw_frame_group_ctrl_0010 >
1525 
1526 			<enum 23 sw_frame_group_ctrl_0011 >
1527 
1528 			<enum 24 sw_frame_group_ctrl_0100 >
1529 
1530 			<enum 25 sw_frame_group_ctrl_0101 >
1531 
1532 			<enum 26 sw_frame_group_ctrl_0110 >
1533 
1534 			<enum 27 sw_frame_group_ctrl_0111 >
1535 
1536 			<enum 28 sw_frame_group_ctrl_1000 >
1537 
1538 			<enum 29 sw_frame_group_ctrl_1001 >
1539 
1540 			<enum 30 sw_frame_group_ctrl_1010 >
1541 
1542 			<enum 31 sw_frame_group_ctrl_1011 >
1543 
1544 			<enum 32 sw_frame_group_ctrl_1100 >
1545 
1546 			<enum 33 sw_frame_group_ctrl_1101 >
1547 
1548 			<enum 34 sw_frame_group_ctrl_1110 >
1549 
1550 			<enum 35 sw_frame_group_ctrl_1111 >
1551 
1552 
1553 
1554 			<enum 36 sw_frame_group_unsupported> This covers type 3
1555 			and protocol version != 0
1556 
1557 			Note: The corresponding Rxpcu_Mpdu_filter_in_category
1558 			can only be rxpcu_monitor_other
1559 
1560 
1561 
1562 
1563 			Note: The corresponding Rxpcu_Mpdu_filter_in_category
1564 			can be rxpcu_filter_pass
1565 
1566 
1567 
1568 			<legal 0-37>
1569 */
1570 #define RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET                      0x00000000
1571 #define RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB                         2
1572 #define RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK                        0x000001fc
1573 
1574 /* Description		RX_MPDU_INFO_0_NDP_FRAME
1575 
1576 			When set, the received frame was an NDP frame, and thus
1577 			there will be no MPDU data.
1578 
1579 			<legal all>
1580 */
1581 #define RX_MPDU_INFO_0_NDP_FRAME_OFFSET                              0x00000000
1582 #define RX_MPDU_INFO_0_NDP_FRAME_LSB                                 9
1583 #define RX_MPDU_INFO_0_NDP_FRAME_MASK                                0x00000200
1584 
1585 /* Description		RX_MPDU_INFO_0_PHY_ERR
1586 
1587 			When set, a PHY error was received before MAC received
1588 			any data, and thus there will be no MPDU data.
1589 
1590 			<legal all>
1591 */
1592 #define RX_MPDU_INFO_0_PHY_ERR_OFFSET                                0x00000000
1593 #define RX_MPDU_INFO_0_PHY_ERR_LSB                                   10
1594 #define RX_MPDU_INFO_0_PHY_ERR_MASK                                  0x00000400
1595 
1596 /* Description		RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER
1597 
1598 			When set, a PHY error was received before MAC received
1599 			the complete MPDU header which was needed for proper
1600 			decoding
1601 
1602 			<legal all>
1603 */
1604 #define RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER_OFFSET             0x00000000
1605 #define RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER_LSB                11
1606 #define RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER_MASK               0x00000800
1607 
1608 /* Description		RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR
1609 
1610 			Set when RXPCU detected a version error in the Frame
1611 			control field
1612 
1613 			<legal all>
1614 */
1615 #define RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR_OFFSET                   0x00000000
1616 #define RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR_LSB                      12
1617 #define RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR_MASK                     0x00001000
1618 
1619 /* Description		RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID
1620 
1621 			When set, AST based lookup for this frame has found a
1622 			valid result.
1623 
1624 
1625 
1626 			Note that for NDP frame this will never be set
1627 
1628 			<legal all>
1629 */
1630 #define RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID_OFFSET                 0x00000000
1631 #define RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID_LSB                    13
1632 #define RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID_MASK                   0x00002000
1633 
1634 /* Description		RX_MPDU_INFO_0_RESERVED_0A
1635 
1636 			<legal 0>
1637 */
1638 #define RX_MPDU_INFO_0_RESERVED_0A_OFFSET                            0x00000000
1639 #define RX_MPDU_INFO_0_RESERVED_0A_LSB                               14
1640 #define RX_MPDU_INFO_0_RESERVED_0A_MASK                              0x0000c000
1641 
1642 /* Description		RX_MPDU_INFO_0_PHY_PPDU_ID
1643 
1644 			A ppdu counter value that PHY increments for every PPDU
1645 			received. The counter value wraps around
1646 
1647 			<legal all>
1648 */
1649 #define RX_MPDU_INFO_0_PHY_PPDU_ID_OFFSET                            0x00000000
1650 #define RX_MPDU_INFO_0_PHY_PPDU_ID_LSB                               16
1651 #define RX_MPDU_INFO_0_PHY_PPDU_ID_MASK                              0xffff0000
1652 
1653 /* Description		RX_MPDU_INFO_1_AST_INDEX
1654 
1655 			This field indicates the index of the AST entry
1656 			corresponding to this MPDU. It is provided by the GSE module
1657 			instantiated in RXPCU.
1658 
1659 			A value of 0xFFFF indicates an invalid AST index,
1660 			meaning that No AST entry was found or NO AST search was
1661 			performed
1662 
1663 
1664 
1665 			In case of ndp or phy_err, this field will be set to
1666 			0xFFFF
1667 
1668 			<legal all>
1669 */
1670 #define RX_MPDU_INFO_1_AST_INDEX_OFFSET                              0x00000004
1671 #define RX_MPDU_INFO_1_AST_INDEX_LSB                                 0
1672 #define RX_MPDU_INFO_1_AST_INDEX_MASK                                0x0000ffff
1673 
1674 /* Description		RX_MPDU_INFO_1_SW_PEER_ID
1675 
1676 			In case of ndp or phy_err or AST_based_lookup_valid ==
1677 			0, this field will be set to 0
1678 
1679 
1680 
1681 			This field indicates a unique peer identifier. It is set
1682 			equal to field 'sw_peer_id' from the AST entry
1683 
1684 
1685 
1686 			<legal all>
1687 */
1688 #define RX_MPDU_INFO_1_SW_PEER_ID_OFFSET                             0x00000004
1689 #define RX_MPDU_INFO_1_SW_PEER_ID_LSB                                16
1690 #define RX_MPDU_INFO_1_SW_PEER_ID_MASK                               0xffff0000
1691 
1692 /* Description		RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID
1693 
1694 			When set, the field Mpdu_Frame_control_field has valid
1695 			information
1696 
1697 
1698 
1699 
1700 			<legal all>
1701 */
1702 #define RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET               0x00000008
1703 #define RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB                  0
1704 #define RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK                 0x00000001
1705 
1706 /* Description		RX_MPDU_INFO_2_MPDU_DURATION_VALID
1707 
1708 			When set, the field Mpdu_duration_field has valid
1709 			information
1710 
1711 
1712 
1713 
1714 			<legal all>
1715 */
1716 #define RX_MPDU_INFO_2_MPDU_DURATION_VALID_OFFSET                    0x00000008
1717 #define RX_MPDU_INFO_2_MPDU_DURATION_VALID_LSB                       1
1718 #define RX_MPDU_INFO_2_MPDU_DURATION_VALID_MASK                      0x00000002
1719 
1720 /* Description		RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID
1721 
1722 			When set, the fields mac_addr_ad1_..... have valid
1723 			information
1724 
1725 
1726 
1727 
1728 			<legal all>
1729 */
1730 #define RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET                     0x00000008
1731 #define RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB                        2
1732 #define RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK                       0x00000004
1733 
1734 /* Description		RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID
1735 
1736 			When set, the fields mac_addr_ad2_..... have valid
1737 			information
1738 
1739 
1740 
1741 
1742 
1743 
1744 
1745 			<legal all>
1746 */
1747 #define RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET                     0x00000008
1748 #define RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB                        3
1749 #define RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK                       0x00000008
1750 
1751 /* Description		RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID
1752 
1753 			When set, the fields mac_addr_ad3_..... have valid
1754 			information
1755 
1756 
1757 
1758 
1759 
1760 
1761 
1762 			<legal all>
1763 */
1764 #define RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_OFFSET                     0x00000008
1765 #define RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_LSB                        4
1766 #define RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_MASK                       0x00000010
1767 
1768 /* Description		RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID
1769 
1770 			When set, the fields mac_addr_ad4_..... have valid
1771 			information
1772 
1773 
1774 
1775 
1776 
1777 
1778 
1779 			<legal all>
1780 */
1781 #define RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET                     0x00000008
1782 #define RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB                        5
1783 #define RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK                       0x00000020
1784 
1785 /* Description		RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID
1786 
1787 			When set, the fields mpdu_sequence_control_field and
1788 			mpdu_sequence_number have valid information as well as field
1789 
1790 
1791 
1792 			For MPDUs without a sequence control field, this field
1793 			will not be set.
1794 
1795 
1796 
1797 
1798 			<legal all>
1799 */
1800 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET            0x00000008
1801 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB               6
1802 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK              0x00000040
1803 
1804 /* Description		RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID
1805 
1806 			When set, the field mpdu_qos_control_field has valid
1807 			information
1808 
1809 
1810 
1811 			For MPDUs without a QoS control field, this field will
1812 			not be set.
1813 
1814 
1815 
1816 
1817 			<legal all>
1818 */
1819 #define RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET                 0x00000008
1820 #define RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB                    7
1821 #define RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK                   0x00000080
1822 
1823 /* Description		RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID
1824 
1825 			When set, the field mpdu_HT_control_field has valid
1826 			information
1827 
1828 
1829 
1830 			For MPDUs without a HT control field, this field will
1831 			not be set.
1832 
1833 
1834 
1835 
1836 			<legal all>
1837 */
1838 #define RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID_OFFSET                  0x00000008
1839 #define RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID_LSB                     8
1840 #define RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID_MASK                    0x00000100
1841 
1842 /* Description		RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID
1843 
1844 			When set, the encryption related info fields, like IV
1845 			and PN are valid
1846 
1847 
1848 
1849 			For MPDUs that are not encrypted, this will not be set.
1850 
1851 
1852 
1853 
1854 			<legal all>
1855 */
1856 #define RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET            0x00000008
1857 #define RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB               9
1858 #define RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK              0x00000200
1859 
1860 /* Description		RX_MPDU_INFO_2_MPDU_FRAGMENT_NUMBER
1861 
1862 			Field only valid when Mpdu_sequence_control_valid is set
1863 			AND Fragment_flag is set
1864 
1865 
1866 
1867 			The fragment number from the 802.11 header.
1868 
1869 			<legal all>
1870 */
1871 #define RX_MPDU_INFO_2_MPDU_FRAGMENT_NUMBER_OFFSET                   0x00000008
1872 #define RX_MPDU_INFO_2_MPDU_FRAGMENT_NUMBER_LSB                      10
1873 #define RX_MPDU_INFO_2_MPDU_FRAGMENT_NUMBER_MASK                     0x00003c00
1874 
1875 /* Description		RX_MPDU_INFO_2_MORE_FRAGMENT_FLAG
1876 
1877 			The More Fragment bit setting from the MPDU header of
1878 			the received frame
1879 
1880 
1881 
1882 			<legal all>
1883 */
1884 #define RX_MPDU_INFO_2_MORE_FRAGMENT_FLAG_OFFSET                     0x00000008
1885 #define RX_MPDU_INFO_2_MORE_FRAGMENT_FLAG_LSB                        14
1886 #define RX_MPDU_INFO_2_MORE_FRAGMENT_FLAG_MASK                       0x00004000
1887 
1888 /* Description		RX_MPDU_INFO_2_RESERVED_2A
1889 
1890 			<legal 0>
1891 */
1892 #define RX_MPDU_INFO_2_RESERVED_2A_OFFSET                            0x00000008
1893 #define RX_MPDU_INFO_2_RESERVED_2A_LSB                               15
1894 #define RX_MPDU_INFO_2_RESERVED_2A_MASK                              0x00008000
1895 
1896 /* Description		RX_MPDU_INFO_2_FR_DS
1897 
1898 			Field only valid when Mpdu_frame_control_valid is set
1899 
1900 
1901 
1902 			Set if the from DS bit is set in the frame control.
1903 
1904 			<legal all>
1905 */
1906 #define RX_MPDU_INFO_2_FR_DS_OFFSET                                  0x00000008
1907 #define RX_MPDU_INFO_2_FR_DS_LSB                                     16
1908 #define RX_MPDU_INFO_2_FR_DS_MASK                                    0x00010000
1909 
1910 /* Description		RX_MPDU_INFO_2_TO_DS
1911 
1912 			Field only valid when Mpdu_frame_control_valid is set
1913 
1914 
1915 
1916 			Set if the to DS bit is set in the frame control.
1917 
1918 			<legal all>
1919 */
1920 #define RX_MPDU_INFO_2_TO_DS_OFFSET                                  0x00000008
1921 #define RX_MPDU_INFO_2_TO_DS_LSB                                     17
1922 #define RX_MPDU_INFO_2_TO_DS_MASK                                    0x00020000
1923 
1924 /* Description		RX_MPDU_INFO_2_ENCRYPTED
1925 
1926 			Field only valid when Mpdu_frame_control_valid is set.
1927 
1928 
1929 
1930 			Protected bit from the frame control.
1931 
1932 			<legal all>
1933 */
1934 #define RX_MPDU_INFO_2_ENCRYPTED_OFFSET                              0x00000008
1935 #define RX_MPDU_INFO_2_ENCRYPTED_LSB                                 18
1936 #define RX_MPDU_INFO_2_ENCRYPTED_MASK                                0x00040000
1937 
1938 /* Description		RX_MPDU_INFO_2_MPDU_RETRY
1939 
1940 			Field only valid when Mpdu_frame_control_valid is set.
1941 
1942 
1943 
1944 			Retry bit from the frame control.  Only valid when
1945 			first_msdu is set.
1946 
1947 			<legal all>
1948 */
1949 #define RX_MPDU_INFO_2_MPDU_RETRY_OFFSET                             0x00000008
1950 #define RX_MPDU_INFO_2_MPDU_RETRY_LSB                                19
1951 #define RX_MPDU_INFO_2_MPDU_RETRY_MASK                               0x00080000
1952 
1953 /* Description		RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER
1954 
1955 			Field only valid when Mpdu_sequence_control_valid is
1956 			set.
1957 
1958 
1959 
1960 			The sequence number from the 802.11 header.
1961 
1962 			<legal all>
1963 */
1964 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET                   0x00000008
1965 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB                      20
1966 #define RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK                     0xfff00000
1967 
1968 /* Description		RX_MPDU_INFO_3_EPD_EN
1969 
1970 			Field only valid when AST_based_lookup_valid == 1.
1971 
1972 
1973 
1974 
1975 
1976 			In case of ndp or phy_err or AST_based_lookup_valid ==
1977 			0, this field will be set to 0
1978 
1979 
1980 
1981 			If set to one use EPD instead of LPD
1982 
1983 
1984 
1985 
1986 			<legal all>
1987 */
1988 #define RX_MPDU_INFO_3_EPD_EN_OFFSET                                 0x0000000c
1989 #define RX_MPDU_INFO_3_EPD_EN_LSB                                    0
1990 #define RX_MPDU_INFO_3_EPD_EN_MASK                                   0x00000001
1991 
1992 /* Description		RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED
1993 
1994 			In case of ndp or phy_err or AST_based_lookup_valid ==
1995 			0, this field will be set to 0
1996 
1997 
1998 
1999 			When set, all frames (data only ?) shall be encrypted.
2000 			If not, RX CRYPTO shall set an error flag.
2001 
2002 			<legal all>
2003 */
2004 #define RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET          0x0000000c
2005 #define RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB             1
2006 #define RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK            0x00000002
2007 
2008 /* Description		RX_MPDU_INFO_3_ENCRYPT_TYPE
2009 
2010 			In case of ndp or phy_err or AST_based_lookup_valid ==
2011 			0, this field will be set to 0
2012 
2013 
2014 
2015 			Indicates type of decrypt cipher used (as defined in the
2016 			peer entry)
2017 
2018 
2019 
2020 			<enum 0 wep_40> WEP 40-bit
2021 
2022 			<enum 1 wep_104> WEP 104-bit
2023 
2024 			<enum 2 tkip_no_mic> TKIP without MIC
2025 
2026 			<enum 3 wep_128> WEP 128-bit
2027 
2028 			<enum 4 tkip_with_mic> TKIP with MIC
2029 
2030 			<enum 5 wapi> WAPI
2031 
2032 			<enum 6 aes_ccmp_128> AES CCMP 128
2033 
2034 			<enum 7 no_cipher> No crypto
2035 
2036 			<enum 8 aes_ccmp_256> AES CCMP 256
2037 
2038 			<enum 9 aes_gcmp_128> AES CCMP 128
2039 
2040 			<enum 10 aes_gcmp_256> AES CCMP 256
2041 
2042 			<enum 11 wapi_gcm_sm4> WAPI GCM SM4
2043 
2044 
2045 
2046 			<enum 12 wep_varied_width> WEP encryption. As for WEP
2047 			per keyid the key bit width can vary, the key bit width for
2048 			this MPDU will be indicated in field
2049 			wep_key_width_for_variable key
2050 
2051 			<legal 0-12>
2052 */
2053 #define RX_MPDU_INFO_3_ENCRYPT_TYPE_OFFSET                           0x0000000c
2054 #define RX_MPDU_INFO_3_ENCRYPT_TYPE_LSB                              2
2055 #define RX_MPDU_INFO_3_ENCRYPT_TYPE_MASK                             0x0000003c
2056 
2057 /* Description		RX_MPDU_INFO_3_WEP_KEY_WIDTH_FOR_VARIABLE_KEY
2058 
2059 			Field only valid when key_type is set to
2060 			wep_varied_width.
2061 
2062 
2063 
2064 			This field indicates the size of the wep key for this
2065 			MPDU.
2066 
2067 
2068 
2069 			<enum 0 wep_varied_width_40> WEP 40-bit
2070 
2071 			<enum 1 wep_varied_width_104> WEP 104-bit
2072 
2073 			<enum 2 wep_varied_width_128> WEP 128-bit
2074 
2075 
2076 
2077 			<legal 0-2>
2078 */
2079 #define RX_MPDU_INFO_3_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET         0x0000000c
2080 #define RX_MPDU_INFO_3_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB            6
2081 #define RX_MPDU_INFO_3_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK           0x000000c0
2082 
2083 /* Description		RX_MPDU_INFO_3_MESH_STA
2084 
2085 			In case of ndp or phy_err or AST_based_lookup_valid ==
2086 			0, this field will be set to 0
2087 
2088 
2089 
2090 			When set, this is a Mesh (11s) STA
2091 
2092 			<legal all>
2093 */
2094 #define RX_MPDU_INFO_3_MESH_STA_OFFSET                               0x0000000c
2095 #define RX_MPDU_INFO_3_MESH_STA_LSB                                  8
2096 #define RX_MPDU_INFO_3_MESH_STA_MASK                                 0x00000100
2097 
2098 /* Description		RX_MPDU_INFO_3_BSSID_HIT
2099 
2100 			In case of ndp or phy_err or AST_based_lookup_valid ==
2101 			0, this field will be set to 0
2102 
2103 
2104 
2105 			When set, the BSSID of the incoming frame matched one of
2106 			the 8 BSSID register values
2107 
2108 
2109 
2110 			<legal all>
2111 */
2112 #define RX_MPDU_INFO_3_BSSID_HIT_OFFSET                              0x0000000c
2113 #define RX_MPDU_INFO_3_BSSID_HIT_LSB                                 9
2114 #define RX_MPDU_INFO_3_BSSID_HIT_MASK                                0x00000200
2115 
2116 /* Description		RX_MPDU_INFO_3_BSSID_NUMBER
2117 
2118 			Field only valid when bssid_hit is set.
2119 
2120 
2121 
2122 			This number indicates which one out of the 8 BSSID
2123 			register values matched the incoming frame
2124 
2125 			<legal all>
2126 */
2127 #define RX_MPDU_INFO_3_BSSID_NUMBER_OFFSET                           0x0000000c
2128 #define RX_MPDU_INFO_3_BSSID_NUMBER_LSB                              10
2129 #define RX_MPDU_INFO_3_BSSID_NUMBER_MASK                             0x00003c00
2130 
2131 /* Description		RX_MPDU_INFO_3_TID
2132 
2133 			Field only valid when mpdu_qos_control_valid is set
2134 
2135 
2136 
2137 			The TID field in the QoS control field
2138 
2139 			<legal all>
2140 */
2141 #define RX_MPDU_INFO_3_TID_OFFSET                                    0x0000000c
2142 #define RX_MPDU_INFO_3_TID_LSB                                       14
2143 #define RX_MPDU_INFO_3_TID_MASK                                      0x0003c000
2144 
2145 /* Description		RX_MPDU_INFO_3_RESERVED_3A
2146 
2147 			<legal 0>
2148 */
2149 #define RX_MPDU_INFO_3_RESERVED_3A_OFFSET                            0x0000000c
2150 #define RX_MPDU_INFO_3_RESERVED_3A_LSB                               18
2151 #define RX_MPDU_INFO_3_RESERVED_3A_MASK                              0xfffc0000
2152 
2153 /* Description		RX_MPDU_INFO_4_PN_31_0
2154 
2155 
2156 
2157 
2158 
2159 			WEP: IV = {key_id_octet, pn2, pn1, pn0}.  Only pn[23:0]
2160 			is valid.
2161 
2162 			TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0,
2163 			WEPSeed[1], pn1}.  Only pn[47:0] is valid.
2164 
2165 			AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0,
2166 			pn1, pn0}.  Only pn[47:0] is valid.
2167 
2168 			WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12,
2169 			pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1,
2170 			pn0}.  pn[127:0] are valid.
2171 
2172 
2173 
2174 */
2175 #define RX_MPDU_INFO_4_PN_31_0_OFFSET                                0x00000010
2176 #define RX_MPDU_INFO_4_PN_31_0_LSB                                   0
2177 #define RX_MPDU_INFO_4_PN_31_0_MASK                                  0xffffffff
2178 
2179 /* Description		RX_MPDU_INFO_5_PN_63_32
2180 
2181 
2182 
2183 
2184 			Bits [63:32] of the PN number.   See description for
2185 			pn_31_0.
2186 
2187 
2188 
2189 */
2190 #define RX_MPDU_INFO_5_PN_63_32_OFFSET                               0x00000014
2191 #define RX_MPDU_INFO_5_PN_63_32_LSB                                  0
2192 #define RX_MPDU_INFO_5_PN_63_32_MASK                                 0xffffffff
2193 
2194 /* Description		RX_MPDU_INFO_6_PN_95_64
2195 
2196 
2197 
2198 
2199 			Bits [95:64] of the PN number.  See description for
2200 			pn_31_0.
2201 
2202 
2203 
2204 */
2205 #define RX_MPDU_INFO_6_PN_95_64_OFFSET                               0x00000018
2206 #define RX_MPDU_INFO_6_PN_95_64_LSB                                  0
2207 #define RX_MPDU_INFO_6_PN_95_64_MASK                                 0xffffffff
2208 
2209 /* Description		RX_MPDU_INFO_7_PN_127_96
2210 
2211 
2212 
2213 
2214 			Bits [127:96] of the PN number.  See description for
2215 			pn_31_0.
2216 
2217 
2218 
2219 */
2220 #define RX_MPDU_INFO_7_PN_127_96_OFFSET                              0x0000001c
2221 #define RX_MPDU_INFO_7_PN_127_96_LSB                                 0
2222 #define RX_MPDU_INFO_7_PN_127_96_MASK                                0xffffffff
2223 
2224 /* Description		RX_MPDU_INFO_8_PEER_META_DATA
2225 
2226 			In case of ndp or phy_err or AST_based_lookup_valid ==
2227 			0, this field will be set to 0
2228 
2229 
2230 
2231 			Meta data that SW has programmed in the Peer table entry
2232 			of the transmitting STA.
2233 
2234 			<legal all>
2235 */
2236 #define RX_MPDU_INFO_8_PEER_META_DATA_OFFSET                         0x00000020
2237 #define RX_MPDU_INFO_8_PEER_META_DATA_LSB                            0
2238 #define RX_MPDU_INFO_8_PEER_META_DATA_MASK                           0xffffffff
2239 
2240  /* EXTERNAL REFERENCE : struct rxpt_classify_info rxpt_classify_info_details */
2241 
2242 
2243 /* Description		RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION
2244 
2245 			The ID of the REO exit ring where the MSDU frame shall
2246 			push after (MPDU level) reordering has finished.
2247 
2248 
2249 
2250 			<enum 0 reo_destination_tcl> Reo will push the frame
2251 			into the REO2TCL ring
2252 
2253 			<enum 1 reo_destination_sw1> Reo will push the frame
2254 			into the REO2SW1 ring
2255 
2256 			<enum 2 reo_destination_sw2> Reo will push the frame
2257 			into the REO2SW1 ring
2258 
2259 			<enum 3 reo_destination_sw3> Reo will push the frame
2260 			into the REO2SW1 ring
2261 
2262 			<enum 4 reo_destination_sw4> Reo will push the frame
2263 			into the REO2SW1 ring
2264 
2265 			<enum 5 reo_destination_release> Reo will push the frame
2266 			into the REO_release ring
2267 
2268 			<enum 6 reo_destination_fw> Reo will push the frame into
2269 			the REO2FW ring
2270 
2271 			<enum 7 reo_destination_7> REO remaps this
2272 
2273 			<enum 8 reo_destination_8> REO remaps this <enum 9
2274 			reo_destination_9> REO remaps this <enum 10
2275 			reo_destination_10> REO remaps this
2276 
2277 			<enum 11 reo_destination_11> REO remaps this
2278 
2279 			<enum 12 reo_destination_12> REO remaps this <enum 13
2280 			reo_destination_13> REO remaps this
2281 
2282 			<enum 14 reo_destination_14> REO remaps this
2283 
2284 			<enum 15 reo_destination_15> REO remaps this
2285 
2286 			<enum 16 reo_destination_16> REO remaps this
2287 
2288 			<enum 17 reo_destination_17> REO remaps this
2289 
2290 			<enum 18 reo_destination_18> REO remaps this
2291 
2292 			<enum 19 reo_destination_19> REO remaps this
2293 
2294 			<enum 20 reo_destination_20> REO remaps this
2295 
2296 			<enum 21 reo_destination_21> REO remaps this
2297 
2298 			<enum 22 reo_destination_22> REO remaps this
2299 
2300 			<enum 23 reo_destination_23> REO remaps this
2301 
2302 			<enum 24 reo_destination_24> REO remaps this
2303 
2304 			<enum 25 reo_destination_25> REO remaps this
2305 
2306 			<enum 26 reo_destination_26> REO remaps this
2307 
2308 			<enum 27 reo_destination_27> REO remaps this
2309 
2310 			<enum 28 reo_destination_28> REO remaps this
2311 
2312 			<enum 29 reo_destination_29> REO remaps this
2313 
2314 			<enum 30 reo_destination_30> REO remaps this
2315 
2316 			<enum 31 reo_destination_31> REO remaps this
2317 
2318 
2319 
2320 			<legal all>
2321 */
2322 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000024
2323 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
2324 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
2325 
2326 /* Description		RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0A
2327 
2328 			<legal 0>
2329 */
2330 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000024
2331 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0A_LSB    5
2332 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0A_MASK   0x00000060
2333 
2334 /* Description		RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY
2335 
2336 			Field is used to enable classification based on the
2337 			chosen Toeplitz hash from Common Parser (without reference
2338 			to each hash type).
2339 
2340 			<legal all>
2341 */
2342 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000024
2343 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7
2344 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080
2345 
2346 /* Description		RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA
2347 
2348 			Filter pass ucast data frame routing selection.
2349 
2350 
2351 
2352 			1'b0: source and destination rings are selected from the
2353 			RxOLE register settings for the packet type
2354 
2355 
2356 
2357 			1'b1: source ring and destination ring is selected from
2358 			the rxdma0_source_ring_selection and
2359 			rxdma0_destination_ring_selection fields in this STRUCT
2360 
2361 			<legal all>
2362 */
2363 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000024
2364 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8
2365 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100
2366 
2367 /* Description		RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA
2368 
2369 			Filter pass multicase data frame routing selection.
2370 
2371 
2372 
2373 			1'b0: source and destination rings are selected from the
2374 			RxOLE register settings for the packet type
2375 
2376 
2377 
2378 			1'b1: source ring and destination ring is selected from
2379 			the rxdma0_source_ring_selection and
2380 			rxdma0_destination_ring_selection fields in this STRUCT
2381 
2382 			<legal all>
2383 */
2384 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000024
2385 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9
2386 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200
2387 
2388 /* Description		RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000
2389 
2390 			Filter pass control bar frame routing selection.
2391 
2392 
2393 
2394 			1'b0: source and destination rings are selected from the
2395 			RxOLE register settings for the packet type
2396 
2397 
2398 
2399 			1'b1: source ring and destination ring is selected from
2400 			the rxdma0_source_ring_selection and
2401 			rxdma0_destination_ring_selection fields in this STRUCT
2402 
2403 			<legal all>
2404 */
2405 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000024
2406 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10
2407 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400
2408 
2409 /* Description		RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION
2410 
2411 			Field only valid when for the received frame type the
2412 			corresponding pkt_selection_fp_... bit is set
2413 
2414 
2415 
2416 			<enum 0 wbm2rxdma_buf_source_ring> The data buffer for
2417 			this frame shall be sourced by wbm2rxdma buffer source ring
2418 
2419 			<enum 1 fw2rxdma_buf_source_ring> The data buffer for
2420 			this frame shall be sourced by fw2rxdma buffer source ring
2421 
2422 			<enum 2 sw2rxdma_buf_source_ring> The data buffer for
2423 			this frame shall be sourced by sw2rxdma buffer source ring
2424 
2425 			<enum 3 no_buffer_ring> The frame shall not be written
2426 			to any data buffer
2427 
2428 			<legal all>
2429 */
2430 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000024
2431 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11
2432 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00001800
2433 
2434 /* Description		RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION
2435 
2436 			Field only valid when for the received frame type the
2437 			corresponding pkt_selection_fp_... bit is set
2438 
2439 
2440 
2441 			<enum 0  rxdma_release_ring >  RXDMA0 shall push the
2442 			frame to the Release ring. Effectively this means the frame
2443 			needs to be dropped.
2444 
2445 
2446 
2447 			<enum 1  rxdma2fw_ring >  RXDMA0 shall push the frame to
2448 			the FW ring
2449 
2450 
2451 
2452 			<enum 2  rxdma2sw_ring >  RXDMA0 shall push the frame to
2453 			the SW ring
2454 
2455 
2456 
2457 			<enum 3  rxdma2reo_ring >  RXDMA0 shall push the frame
2458 			to the REO entrance ring
2459 
2460 			<legal all>
2461 */
2462 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000024
2463 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 13
2464 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x00006000
2465 
2466 /* Description		RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B
2467 
2468 			<legal 0>
2469 */
2470 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000024
2471 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB    15
2472 #define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK   0xffff8000
2473 
2474 /* Description		RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0
2475 
2476 			In case of ndp or phy_err or AST_based_lookup_valid ==
2477 			0, this field will be set to 0
2478 
2479 
2480 
2481 			Address (lower 32 bits) of the REO queue descriptor.
2482 
2483 
2484 
2485 			If no Peer entry lookup happened for this frame, the
2486 			value wil be set to 0, and the frame shall never be pushed
2487 			to REO entrance ring.
2488 
2489 			<legal all>
2490 */
2491 #define RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET           0x00000028
2492 #define RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0_LSB              0
2493 #define RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0_MASK             0xffffffff
2494 
2495 /* Description		RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32
2496 
2497 			In case of ndp or phy_err or AST_based_lookup_valid ==
2498 			0, this field will be set to 0
2499 
2500 
2501 
2502 			Address (upper 8 bits) of the REO queue descriptor.
2503 
2504 
2505 
2506 			If no Peer entry lookup happened for this frame, the
2507 			value wil be set to 0, and the frame shall never be pushed
2508 			to REO entrance ring.
2509 
2510 			<legal all>
2511 */
2512 #define RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET          0x0000002c
2513 #define RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32_LSB             0
2514 #define RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32_MASK            0x000000ff
2515 
2516 /* Description		RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER
2517 
2518 			In case of ndp or phy_err or AST_based_lookup_valid ==
2519 			0, this field will be set to 0
2520 
2521 
2522 
2523 			Indicates the MPDU queue ID to which this MPDU link
2524 			descriptor belongs
2525 
2526 			Used for tracking and debugging
2527 
2528 			<legal all>
2529 */
2530 #define RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER_OFFSET                  0x0000002c
2531 #define RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER_LSB                     8
2532 #define RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER_MASK                    0x00ffff00
2533 
2534 /* Description		RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING
2535 
2536 			Indicates that a delimiter FCS error was found in
2537 			between the Previous MPDU and this MPDU.
2538 
2539 
2540 
2541 			Note that this is just a warning, and does not mean that
2542 			this MPDU is corrupted in any way. If it is, there will be
2543 			other errors indicated such as FCS or decrypt errors
2544 
2545 
2546 
2547 			In case of ndp or phy_err, this field will indicate at
2548 			least one of delimiters located after the last MPDU in the
2549 			previous PPDU has been corrupted.
2550 */
2551 #define RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING_OFFSET                 0x0000002c
2552 #define RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING_LSB                    24
2553 #define RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING_MASK                   0x01000000
2554 
2555 /* Description		RX_MPDU_INFO_11_FIRST_DELIM_ERR
2556 
2557 			Indicates that the first delimiter had a FCS failure.
2558 			Only valid when first_mpdu and first_msdu are set.
2559 
2560 
2561 
2562 */
2563 #define RX_MPDU_INFO_11_FIRST_DELIM_ERR_OFFSET                       0x0000002c
2564 #define RX_MPDU_INFO_11_FIRST_DELIM_ERR_LSB                          25
2565 #define RX_MPDU_INFO_11_FIRST_DELIM_ERR_MASK                         0x02000000
2566 
2567 /* Description		RX_MPDU_INFO_11_RESERVED_11
2568 
2569 			<legal 0>
2570 */
2571 #define RX_MPDU_INFO_11_RESERVED_11_OFFSET                           0x0000002c
2572 #define RX_MPDU_INFO_11_RESERVED_11_LSB                              26
2573 #define RX_MPDU_INFO_11_RESERVED_11_MASK                             0xfc000000
2574 
2575 /* Description		RX_MPDU_INFO_12_KEY_ID_OCTET
2576 
2577 
2578 
2579 
2580 			The key ID octet from the IV.
2581 
2582 
2583 
2584 			In case of ndp or phy_err or AST_based_lookup_valid ==
2585 			0, this field will be set to 0
2586 
2587 			<legal all>
2588 */
2589 #define RX_MPDU_INFO_12_KEY_ID_OCTET_OFFSET                          0x00000030
2590 #define RX_MPDU_INFO_12_KEY_ID_OCTET_LSB                             0
2591 #define RX_MPDU_INFO_12_KEY_ID_OCTET_MASK                            0x000000ff
2592 
2593 /* Description		RX_MPDU_INFO_12_NEW_PEER_ENTRY
2594 
2595 			In case of ndp or phy_err or AST_based_lookup_valid ==
2596 			0, this field will be set to 0
2597 
2598 
2599 
2600 			Set if new RX_PEER_ENTRY TLV follows. If clear,
2601 			RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either
2602 			uses old peer entry or not decrypt.
2603 
2604 			<legal all>
2605 */
2606 #define RX_MPDU_INFO_12_NEW_PEER_ENTRY_OFFSET                        0x00000030
2607 #define RX_MPDU_INFO_12_NEW_PEER_ENTRY_LSB                           8
2608 #define RX_MPDU_INFO_12_NEW_PEER_ENTRY_MASK                          0x00000100
2609 
2610 /* Description		RX_MPDU_INFO_12_DECRYPT_NEEDED
2611 
2612 			In case of ndp or phy_err or AST_based_lookup_valid ==
2613 			0, this field will be set to 0
2614 
2615 
2616 
2617 			Set if decryption is needed.
2618 
2619 
2620 
2621 			Note:
2622 
2623 			When RXPCU sets bit 'ast_index_not_found' and/or
2624 			ast_index_timeout', RXPCU will also ensure that this bit is
2625 			NOT set
2626 
2627 			CRYPTO for that reason only needs to evaluate this bit
2628 			and non of the other ones.
2629 
2630 			<legal all>
2631 */
2632 #define RX_MPDU_INFO_12_DECRYPT_NEEDED_OFFSET                        0x00000030
2633 #define RX_MPDU_INFO_12_DECRYPT_NEEDED_LSB                           9
2634 #define RX_MPDU_INFO_12_DECRYPT_NEEDED_MASK                          0x00000200
2635 
2636 /* Description		RX_MPDU_INFO_12_DECAP_TYPE
2637 
2638 			In case of ndp or phy_err or AST_based_lookup_valid ==
2639 			0, this field will be set to 0
2640 
2641 
2642 
2643 			Used by the OLE during decapsulation.
2644 
2645 
2646 
2647 			Indicates the decapsulation that HW will perform:
2648 
2649 
2650 
2651 			<enum 0 RAW> No encapsulation
2652 
2653 			<enum 1 Native_WiFi>
2654 
2655 			<enum 2 Ethernet> Ethernet 2 (DIX)  or 802.3 (uses
2656 			SNAP/LLC)
2657 
2658 			<enum 3 802_3> Indicate Ethernet
2659 
2660 
2661 
2662 			<legal all>
2663 */
2664 #define RX_MPDU_INFO_12_DECAP_TYPE_OFFSET                            0x00000030
2665 #define RX_MPDU_INFO_12_DECAP_TYPE_LSB                               10
2666 #define RX_MPDU_INFO_12_DECAP_TYPE_MASK                              0x00000c00
2667 
2668 /* Description		RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING
2669 
2670 			In case of ndp or phy_err or AST_based_lookup_valid ==
2671 			0, this field will be set to 0
2672 
2673 
2674 
2675 			Insert 4 byte of all zeros as VLAN tag if the rx payload
2676 			does not have VLAN. Used during decapsulation.
2677 
2678 			<legal all>
2679 */
2680 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET          0x00000030
2681 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_LSB             12
2682 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_MASK            0x00001000
2683 
2684 /* Description		RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING
2685 
2686 			In case of ndp or phy_err or AST_based_lookup_valid ==
2687 			0, this field will be set to 0
2688 
2689 
2690 
2691 			Insert 4 byte of all zeros as double VLAN tag if the rx
2692 			payload does not have VLAN. Used during
2693 
2694 			<legal all>
2695 */
2696 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET          0x00000030
2697 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_LSB             13
2698 #define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_MASK            0x00002000
2699 
2700 /* Description		RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP
2701 
2702 			In case of ndp or phy_err or AST_based_lookup_valid ==
2703 			0, this field will be set to 0
2704 
2705 
2706 
2707 			Strip the VLAN during decapsulation.  Used by the OLE.
2708 
2709 			<legal all>
2710 */
2711 #define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_OFFSET                0x00000030
2712 #define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_LSB                   14
2713 #define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_MASK                  0x00004000
2714 
2715 /* Description		RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP
2716 
2717 			In case of ndp or phy_err or AST_based_lookup_valid ==
2718 			0, this field will be set to 0
2719 
2720 
2721 
2722 			Strip the double VLAN during decapsulation.  Used by
2723 			the OLE.
2724 
2725 			<legal all>
2726 */
2727 #define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_OFFSET                0x00000030
2728 #define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_LSB                   15
2729 #define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_MASK                  0x00008000
2730 
2731 /* Description		RX_MPDU_INFO_12_PRE_DELIM_COUNT
2732 
2733 			The number of delimiters before this MPDU.
2734 
2735 
2736 
2737 			Note that this number is cleared at PPDU start.
2738 
2739 
2740 
2741 			If this MPDU is the first received MPDU in the PPDU and
2742 			this MPDU gets filtered-in, this field will indicate the
2743 			number of delimiters located after the last MPDU in the
2744 			previous PPDU.
2745 
2746 
2747 
2748 			If this MPDU is located after the first received MPDU in
2749 			an PPDU, this field will indicate the number of delimiters
2750 			located between the previous MPDU and this MPDU.
2751 
2752 
2753 
2754 			In case of ndp or phy_err, this field will indicate the
2755 			number of delimiters located after the last MPDU in the
2756 			previous PPDU.
2757 
2758 			<legal all>
2759 */
2760 #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_OFFSET                       0x00000030
2761 #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_LSB                          16
2762 #define RX_MPDU_INFO_12_PRE_DELIM_COUNT_MASK                         0x0fff0000
2763 
2764 /* Description		RX_MPDU_INFO_12_AMPDU_FLAG
2765 
2766 			When set, received frame was part of an A-MPDU.
2767 
2768 
2769 
2770 
2771 			<legal all>
2772 */
2773 #define RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET                            0x00000030
2774 #define RX_MPDU_INFO_12_AMPDU_FLAG_LSB                               28
2775 #define RX_MPDU_INFO_12_AMPDU_FLAG_MASK                              0x10000000
2776 
2777 /* Description		RX_MPDU_INFO_12_BAR_FRAME
2778 
2779 			In case of ndp or phy_err or AST_based_lookup_valid ==
2780 			0, this field will be set to 0
2781 
2782 
2783 
2784 			When set, received frame is a BAR frame
2785 
2786 			<legal all>
2787 */
2788 #define RX_MPDU_INFO_12_BAR_FRAME_OFFSET                             0x00000030
2789 #define RX_MPDU_INFO_12_BAR_FRAME_LSB                                29
2790 #define RX_MPDU_INFO_12_BAR_FRAME_MASK                               0x20000000
2791 
2792 /* Description		RX_MPDU_INFO_12_RESERVED_12
2793 
2794 			<legal 0>.
2795 */
2796 #define RX_MPDU_INFO_12_RESERVED_12_OFFSET                           0x00000030
2797 #define RX_MPDU_INFO_12_RESERVED_12_LSB                              30
2798 #define RX_MPDU_INFO_12_RESERVED_12_MASK                             0xc0000000
2799 
2800 /* Description		RX_MPDU_INFO_13_MPDU_LENGTH
2801 
2802 			In case of ndp or phy_err this field will be set to 0
2803 
2804 
2805 
2806 			MPDU length before decapsulation.
2807 
2808 			<legal all>
2809 */
2810 #define RX_MPDU_INFO_13_MPDU_LENGTH_OFFSET                           0x00000034
2811 #define RX_MPDU_INFO_13_MPDU_LENGTH_LSB                              0
2812 #define RX_MPDU_INFO_13_MPDU_LENGTH_MASK                             0x00003fff
2813 
2814 /* Description		RX_MPDU_INFO_13_FIRST_MPDU
2815 
2816 			See definition in RX attention descriptor
2817 
2818 
2819 
2820 			In case of ndp or phy_err, this field will be set. Note
2821 			however that there will not actually be any data contents in
2822 			the MPDU.
2823 
2824 			<legal all>
2825 */
2826 #define RX_MPDU_INFO_13_FIRST_MPDU_OFFSET                            0x00000034
2827 #define RX_MPDU_INFO_13_FIRST_MPDU_LSB                               14
2828 #define RX_MPDU_INFO_13_FIRST_MPDU_MASK                              0x00004000
2829 
2830 /* Description		RX_MPDU_INFO_13_MCAST_BCAST
2831 
2832 			In case of ndp or phy_err or Phy_err_during_mpdu_header
2833 			this field will be set to 0
2834 
2835 
2836 
2837 			See definition in RX attention descriptor
2838 
2839 			<legal all>
2840 */
2841 #define RX_MPDU_INFO_13_MCAST_BCAST_OFFSET                           0x00000034
2842 #define RX_MPDU_INFO_13_MCAST_BCAST_LSB                              15
2843 #define RX_MPDU_INFO_13_MCAST_BCAST_MASK                             0x00008000
2844 
2845 /* Description		RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND
2846 
2847 			In case of ndp or phy_err or Phy_err_during_mpdu_header
2848 			this field will be set to 0
2849 
2850 
2851 
2852 			See definition in RX attention descriptor
2853 
2854 			<legal all>
2855 */
2856 #define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_OFFSET                   0x00000034
2857 #define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_LSB                      16
2858 #define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_MASK                     0x00010000
2859 
2860 /* Description		RX_MPDU_INFO_13_AST_INDEX_TIMEOUT
2861 
2862 			In case of ndp or phy_err or Phy_err_during_mpdu_header
2863 			this field will be set to 0
2864 
2865 
2866 
2867 			See definition in RX attention descriptor
2868 
2869 			<legal all>
2870 */
2871 #define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_OFFSET                     0x00000034
2872 #define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_LSB                        17
2873 #define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_MASK                       0x00020000
2874 
2875 /* Description		RX_MPDU_INFO_13_POWER_MGMT
2876 
2877 			In case of ndp or phy_err or Phy_err_during_mpdu_header
2878 			this field will be set to 0
2879 
2880 
2881 
2882 			See definition in RX attention descriptor
2883 
2884 			<legal all>
2885 */
2886 #define RX_MPDU_INFO_13_POWER_MGMT_OFFSET                            0x00000034
2887 #define RX_MPDU_INFO_13_POWER_MGMT_LSB                               18
2888 #define RX_MPDU_INFO_13_POWER_MGMT_MASK                              0x00040000
2889 
2890 /* Description		RX_MPDU_INFO_13_NON_QOS
2891 
2892 			In case of ndp or phy_err or Phy_err_during_mpdu_header
2893 			this field will be set to 1
2894 
2895 
2896 
2897 			See definition in RX attention descriptor
2898 
2899 			<legal all>
2900 */
2901 #define RX_MPDU_INFO_13_NON_QOS_OFFSET                               0x00000034
2902 #define RX_MPDU_INFO_13_NON_QOS_LSB                                  19
2903 #define RX_MPDU_INFO_13_NON_QOS_MASK                                 0x00080000
2904 
2905 /* Description		RX_MPDU_INFO_13_NULL_DATA
2906 
2907 			In case of ndp or phy_err or Phy_err_during_mpdu_header
2908 			this field will be set to 0
2909 
2910 
2911 
2912 			See definition in RX attention descriptor
2913 
2914 			<legal all>
2915 */
2916 #define RX_MPDU_INFO_13_NULL_DATA_OFFSET                             0x00000034
2917 #define RX_MPDU_INFO_13_NULL_DATA_LSB                                20
2918 #define RX_MPDU_INFO_13_NULL_DATA_MASK                               0x00100000
2919 
2920 /* Description		RX_MPDU_INFO_13_MGMT_TYPE
2921 
2922 			In case of ndp or phy_err or Phy_err_during_mpdu_header
2923 			this field will be set to 0
2924 
2925 
2926 
2927 			See definition in RX attention descriptor
2928 
2929 			<legal all>
2930 */
2931 #define RX_MPDU_INFO_13_MGMT_TYPE_OFFSET                             0x00000034
2932 #define RX_MPDU_INFO_13_MGMT_TYPE_LSB                                21
2933 #define RX_MPDU_INFO_13_MGMT_TYPE_MASK                               0x00200000
2934 
2935 /* Description		RX_MPDU_INFO_13_CTRL_TYPE
2936 
2937 			In case of ndp or phy_err or Phy_err_during_mpdu_header
2938 			this field will be set to 0
2939 
2940 
2941 
2942 			See definition in RX attention descriptor
2943 
2944 			<legal all>
2945 */
2946 #define RX_MPDU_INFO_13_CTRL_TYPE_OFFSET                             0x00000034
2947 #define RX_MPDU_INFO_13_CTRL_TYPE_LSB                                22
2948 #define RX_MPDU_INFO_13_CTRL_TYPE_MASK                               0x00400000
2949 
2950 /* Description		RX_MPDU_INFO_13_MORE_DATA
2951 
2952 			In case of ndp or phy_err or Phy_err_during_mpdu_header
2953 			this field will be set to 0
2954 
2955 
2956 
2957 			See definition in RX attention descriptor
2958 
2959 			<legal all>
2960 */
2961 #define RX_MPDU_INFO_13_MORE_DATA_OFFSET                             0x00000034
2962 #define RX_MPDU_INFO_13_MORE_DATA_LSB                                23
2963 #define RX_MPDU_INFO_13_MORE_DATA_MASK                               0x00800000
2964 
2965 /* Description		RX_MPDU_INFO_13_EOSP
2966 
2967 			In case of ndp or phy_err or Phy_err_during_mpdu_header
2968 			this field will be set to 0
2969 
2970 
2971 
2972 			See definition in RX attention descriptor
2973 
2974 			<legal all>
2975 */
2976 #define RX_MPDU_INFO_13_EOSP_OFFSET                                  0x00000034
2977 #define RX_MPDU_INFO_13_EOSP_LSB                                     24
2978 #define RX_MPDU_INFO_13_EOSP_MASK                                    0x01000000
2979 
2980 /* Description		RX_MPDU_INFO_13_FRAGMENT_FLAG
2981 
2982 			In case of ndp or phy_err or Phy_err_during_mpdu_header
2983 			this field will be set to 0
2984 
2985 
2986 
2987 			See definition in RX attention descriptor
2988 
2989 			<legal all>
2990 */
2991 #define RX_MPDU_INFO_13_FRAGMENT_FLAG_OFFSET                         0x00000034
2992 #define RX_MPDU_INFO_13_FRAGMENT_FLAG_LSB                            25
2993 #define RX_MPDU_INFO_13_FRAGMENT_FLAG_MASK                           0x02000000
2994 
2995 /* Description		RX_MPDU_INFO_13_ORDER
2996 
2997 			In case of ndp or phy_err or Phy_err_during_mpdu_header
2998 			this field will be set to 0
2999 
3000 
3001 
3002 			See definition in RX attention descriptor
3003 
3004 
3005 
3006 			<legal all>
3007 */
3008 #define RX_MPDU_INFO_13_ORDER_OFFSET                                 0x00000034
3009 #define RX_MPDU_INFO_13_ORDER_LSB                                    26
3010 #define RX_MPDU_INFO_13_ORDER_MASK                                   0x04000000
3011 
3012 /* Description		RX_MPDU_INFO_13_U_APSD_TRIGGER
3013 
3014 			In case of ndp or phy_err or Phy_err_during_mpdu_header
3015 			this field will be set to 0
3016 
3017 
3018 
3019 			See definition in RX attention descriptor
3020 
3021 			<legal all>
3022 */
3023 #define RX_MPDU_INFO_13_U_APSD_TRIGGER_OFFSET                        0x00000034
3024 #define RX_MPDU_INFO_13_U_APSD_TRIGGER_LSB                           27
3025 #define RX_MPDU_INFO_13_U_APSD_TRIGGER_MASK                          0x08000000
3026 
3027 /* Description		RX_MPDU_INFO_13_ENCRYPT_REQUIRED
3028 
3029 			In case of ndp or phy_err or Phy_err_during_mpdu_header
3030 			this field will be set to 0
3031 
3032 
3033 
3034 			See definition in RX attention descriptor
3035 
3036 			<legal all>
3037 */
3038 #define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_OFFSET                      0x00000034
3039 #define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_LSB                         28
3040 #define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_MASK                        0x10000000
3041 
3042 /* Description		RX_MPDU_INFO_13_DIRECTED
3043 
3044 			In case of ndp or phy_err or Phy_err_during_mpdu_header
3045 			this field will be set to 0
3046 
3047 
3048 
3049 			See definition in RX attention descriptor
3050 
3051 			<legal all>
3052 */
3053 #define RX_MPDU_INFO_13_DIRECTED_OFFSET                              0x00000034
3054 #define RX_MPDU_INFO_13_DIRECTED_LSB                                 29
3055 #define RX_MPDU_INFO_13_DIRECTED_MASK                                0x20000000
3056 
3057 /* Description		RX_MPDU_INFO_13_RESERVED_13
3058 
3059 			<legal 0>
3060 */
3061 #define RX_MPDU_INFO_13_RESERVED_13_OFFSET                           0x00000034
3062 #define RX_MPDU_INFO_13_RESERVED_13_LSB                              30
3063 #define RX_MPDU_INFO_13_RESERVED_13_MASK                             0xc0000000
3064 
3065 /* Description		RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD
3066 
3067 			Field only valid when Mpdu_frame_control_valid is set
3068 
3069 
3070 
3071 			The frame control field of this received MPDU.
3072 
3073 
3074 
3075 			Field only valid when Ndp_frame and phy_err are NOT set
3076 
3077 
3078 
3079 			Bytes 0 + 1 of the received MPDU
3080 
3081 			<legal all>
3082 */
3083 #define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET              0x00000038
3084 #define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB                 0
3085 #define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK                0x0000ffff
3086 
3087 /* Description		RX_MPDU_INFO_14_MPDU_DURATION_FIELD
3088 
3089 			Field only valid when Mpdu_duration_valid is set
3090 
3091 
3092 
3093 			The duration field of this received MPDU.
3094 
3095 			<legal all>
3096 */
3097 #define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_OFFSET                   0x00000038
3098 #define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_LSB                      16
3099 #define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_MASK                     0xffff0000
3100 
3101 /* Description		RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0
3102 
3103 			Field only valid when mac_addr_ad1_valid is set
3104 
3105 
3106 
3107 			The Least Significant 4 bytes of the Received Frames MAC
3108 			Address AD1
3109 
3110 			<legal all>
3111 */
3112 #define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET                     0x0000003c
3113 #define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB                        0
3114 #define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK                       0xffffffff
3115 
3116 /* Description		RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32
3117 
3118 			Field only valid when mac_addr_ad1_valid is set
3119 
3120 
3121 
3122 			The 2 most significant bytes of the Received Frames MAC
3123 			Address AD1
3124 
3125 			<legal all>
3126 */
3127 #define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET                    0x00000040
3128 #define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB                       0
3129 #define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK                      0x0000ffff
3130 
3131 /* Description		RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0
3132 
3133 			Field only valid when mac_addr_ad2_valid is set
3134 
3135 
3136 
3137 			The Least Significant 2 bytes of the Received Frames MAC
3138 			Address AD2
3139 
3140 			<legal all>
3141 */
3142 #define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET                     0x00000040
3143 #define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB                        16
3144 #define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK                       0xffff0000
3145 
3146 /* Description		RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16
3147 
3148 			Field only valid when mac_addr_ad2_valid is set
3149 
3150 
3151 
3152 			The 4 most significant bytes of the Received Frames MAC
3153 			Address AD2
3154 
3155 			<legal all>
3156 */
3157 #define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET                    0x00000044
3158 #define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB                       0
3159 #define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK                      0xffffffff
3160 
3161 /* Description		RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0
3162 
3163 			Field only valid when mac_addr_ad3_valid is set
3164 
3165 
3166 
3167 			The Least Significant 4 bytes of the Received Frames MAC
3168 			Address AD3
3169 
3170 			<legal all>
3171 */
3172 #define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET                     0x00000048
3173 #define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB                        0
3174 #define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK                       0xffffffff
3175 
3176 /* Description		RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32
3177 
3178 			Field only valid when mac_addr_ad3_valid is set
3179 
3180 
3181 
3182 			The 2 most significant bytes of the Received Frames MAC
3183 			Address AD3
3184 
3185 			<legal all>
3186 */
3187 #define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET                    0x0000004c
3188 #define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB                       0
3189 #define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK                      0x0000ffff
3190 
3191 /* Description		RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD
3192 
3193 
3194 
3195 
3196 			The sequence control field of the MPDU
3197 
3198 			<legal all>
3199 */
3200 #define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET           0x0000004c
3201 #define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_LSB              16
3202 #define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_MASK             0xffff0000
3203 
3204 /* Description		RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0
3205 
3206 			Field only valid when mac_addr_ad4_valid is set
3207 
3208 
3209 
3210 			The Least Significant 4 bytes of the Received Frames MAC
3211 			Address AD4
3212 
3213 			<legal all>
3214 */
3215 #define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET                     0x00000050
3216 #define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB                        0
3217 #define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK                       0xffffffff
3218 
3219 /* Description		RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32
3220 
3221 			Field only valid when mac_addr_ad4_valid is set
3222 
3223 
3224 
3225 			The 2 most significant bytes of the Received Frames MAC
3226 			Address AD4
3227 
3228 			<legal all>
3229 */
3230 #define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET                    0x00000054
3231 #define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB                       0
3232 #define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK                      0x0000ffff
3233 
3234 /* Description		RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD
3235 
3236 			Field only valid when mpdu_qos_control_valid is set
3237 
3238 
3239 
3240 			The sequence control field of the MPDU
3241 
3242 			<legal all>
3243 */
3244 #define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_OFFSET                0x00000054
3245 #define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_LSB                   16
3246 #define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_MASK                  0xffff0000
3247 
3248 /* Description		RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD
3249 
3250 			Field only valid when mpdu_qos_control_valid is set
3251 
3252 
3253 
3254 			The HT control field of the MPDU
3255 
3256 			<legal all>
3257 */
3258 #define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_OFFSET                 0x00000058
3259 #define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_LSB                    0
3260 #define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_MASK                   0xffffffff
3261 
3262 
3263 #endif // _RX_MPDU_INFO_H_
3264