1 /* 2 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 // $ATH_LICENSE_HW_HDR_C$ 18 // 19 // DO NOT EDIT! This file is automatically generated 20 // These definitions are tied to a particular hardware layout 21 22 23 #ifndef _RX_MSDU_DETAILS_H_ 24 #define _RX_MSDU_DETAILS_H_ 25 #if !defined(__ASSEMBLER__) 26 #endif 27 28 #include "buffer_addr_info.h" 29 #include "rx_msdu_desc_info.h" 30 31 // ################ START SUMMARY ################# 32 // 33 // Dword Fields 34 // 0-1 struct buffer_addr_info buffer_addr_info_details; 35 // 2-3 struct rx_msdu_desc_info rx_msdu_desc_info_details; 36 // 37 // ################ END SUMMARY ################# 38 39 #define NUM_OF_DWORDS_RX_MSDU_DETAILS 4 40 41 struct rx_msdu_details { 42 struct buffer_addr_info buffer_addr_info_details; 43 struct rx_msdu_desc_info rx_msdu_desc_info_details; 44 }; 45 46 /* 47 48 struct buffer_addr_info buffer_addr_info_details 49 50 Consumer: REO/SW 51 52 Producer: RXDMA 53 54 55 56 Details of the physical address of the buffer containing 57 an MSDU (or entire MPDU) 58 59 struct rx_msdu_desc_info rx_msdu_desc_info_details 60 61 Consumer: REO/SW 62 63 Producer: RXDMA 64 65 66 67 General information related to the MSDU that should be 68 passed on from RXDMA all the way to to the REO destination 69 ring. 70 */ 71 72 73 /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ 74 75 76 /* Description RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 77 78 Address (lower 32 bits) of the MSDU buffer OR 79 MSDU_EXTENSION descriptor OR Link Descriptor 80 81 82 83 In case of 'NULL' pointer, this field is set to 0 84 85 <legal all> 86 */ 87 #define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 88 #define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 89 #define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 90 91 /* Description RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 92 93 Address (upper 8 bits) of the MSDU buffer OR 94 MSDU_EXTENSION descriptor OR Link Descriptor 95 96 97 98 In case of 'NULL' pointer, this field is set to 0 99 100 <legal all> 101 */ 102 #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 103 #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 104 #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 105 106 /* Description RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER 107 108 Consumer: WBM 109 110 Producer: SW/FW 111 112 113 114 In case of 'NULL' pointer, this field is set to 0 115 116 117 118 Indicates to which buffer manager the buffer OR 119 MSDU_EXTENSION descriptor OR link descriptor that is being 120 pointed to shall be returned after the frame has been 121 processed. It is used by WBM for routing purposes. 122 123 124 125 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 126 to the WMB buffer idle list 127 128 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 129 returned to the WMB idle link descriptor idle list 130 131 <enum 2 FW_BM> This buffer shall be returned to the FW 132 133 <enum 3 SW0_BM> This buffer shall be returned to the SW, 134 ring 0 135 136 <enum 4 SW1_BM> This buffer shall be returned to the SW, 137 ring 1 138 139 <enum 5 SW2_BM> This buffer shall be returned to the SW, 140 ring 2 141 142 <enum 6 SW3_BM> This buffer shall be returned to the SW, 143 ring 3 144 145 <enum 7 SW4_BM> This buffer shall be returned to the SW, 146 ring 3 147 148 149 150 <legal all> 151 */ 152 #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 153 #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 154 #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 155 156 /* Description RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE 157 158 Cookie field exclusively used by SW. 159 160 161 162 In case of 'NULL' pointer, this field is set to 0 163 164 165 166 HW ignores the contents, accept that it passes the 167 programmed value on to other descriptors together with the 168 physical address 169 170 171 172 Field can be used by SW to for example associate the 173 buffers physical address with the virtual address 174 175 The bit definitions as used by SW are within SW HLD 176 specification 177 178 179 180 NOTE: 181 182 The three most significant bits can have a special 183 meaning in case this struct is embedded in a TX_MPDU_DETAILS 184 STRUCT, and field transmit_bw_restriction is set 185 186 187 188 In case of NON punctured transmission: 189 190 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 191 192 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 193 194 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 195 196 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 197 198 199 200 In case of punctured transmission: 201 202 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 203 204 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 205 206 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 207 208 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 209 210 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 211 212 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 213 214 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 215 216 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 217 218 219 220 Note: a punctured transmission is indicated by the 221 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 222 TLV 223 224 225 226 <legal all> 227 */ 228 #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 229 #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 230 #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 231 232 /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ 233 234 235 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG 236 237 Parsed from RX_MSDU_END TLV . In the case MSDU spans 238 over multiple buffers, this field will be valid in the Last 239 buffer used by the MSDU 240 241 242 243 <enum 0 Not_first_msdu> This is not the first MSDU in 244 the MPDU. 245 246 <enum 1 first_msdu> This MSDU is the first one in the 247 MPDU. 248 249 250 251 <legal all> 252 */ 253 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 254 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 255 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 256 257 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG 258 259 Consumer: WBM/REO/SW/FW 260 261 Producer: RXDMA 262 263 264 265 Parsed from RX_MSDU_END TLV . In the case MSDU spans 266 over multiple buffers, this field will be valid in the Last 267 buffer used by the MSDU 268 269 270 271 <enum 0 Not_last_msdu> There are more MSDUs linked to 272 this MSDU that belongs to this MPDU 273 274 <enum 1 Last_msdu> this MSDU is the last one in the 275 MPDU. This setting is only allowed in combination with 276 'Msdu_continuation' set to 0. This implies that when an msdu 277 is spread out over multiple buffers and thus 278 msdu_continuation is set, only for the very last buffer of 279 the msdu, can the 'last_msdu_in_mpdu_flag' be set. 280 281 282 283 When both first_msdu_in_mpdu_flag and 284 last_msdu_in_mpdu_flag are set, the MPDU that this MSDU 285 belongs to only contains a single MSDU. 286 287 288 289 290 291 <legal all> 292 */ 293 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 294 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 295 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 296 297 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION 298 299 When set, this MSDU buffer was not able to hold the 300 entire MSDU. The next buffer will therefor contain 301 additional information related to this MSDU. 302 303 304 305 <legal all> 306 */ 307 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008 308 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 309 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 310 311 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH 312 313 Parsed from RX_MSDU_START TLV . In the case MSDU spans 314 over multiple buffers, this field will be valid in the First 315 buffer used by MSDU. 316 317 318 319 Full MSDU length in bytes after decapsulation. 320 321 322 323 This field is still valid for MPDU frames without 324 A-MSDU. It still represents MSDU length after decapsulation 325 326 327 328 Or in case of RAW MPDUs, it indicates the length of the 329 entire MPDU (without FCS field) 330 331 <legal all> 332 */ 333 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008 334 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 335 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 336 337 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION 338 339 Parsed from RX_MSDU_END TLV . In the case MSDU spans 340 over multiple buffers, this field will be valid in the Last 341 buffer used by the MSDU 342 343 344 345 The ID of the REO exit ring where the MSDU frame shall 346 push after (MPDU level) reordering has finished. 347 348 349 350 <enum 0 reo_destination_tcl> Reo will push the frame 351 into the REO2TCL ring 352 353 <enum 1 reo_destination_sw1> Reo will push the frame 354 into the REO2SW1 ring 355 356 <enum 2 reo_destination_sw2> Reo will push the frame 357 into the REO2SW1 ring 358 359 <enum 3 reo_destination_sw3> Reo will push the frame 360 into the REO2SW1 ring 361 362 <enum 4 reo_destination_sw4> Reo will push the frame 363 into the REO2SW1 ring 364 365 <enum 5 reo_destination_release> Reo will push the frame 366 into the REO_release ring 367 368 <enum 6 reo_destination_fw> Reo will push the frame into 369 the REO2FW ring 370 371 <enum 7 reo_destination_7> REO remaps this 372 373 <enum 8 reo_destination_8> REO remaps this <enum 9 374 reo_destination_9> REO remaps this <enum 10 375 reo_destination_10> REO remaps this 376 377 <enum 11 reo_destination_11> REO remaps this 378 379 <enum 12 reo_destination_12> REO remaps this <enum 13 380 reo_destination_13> REO remaps this 381 382 <enum 14 reo_destination_14> REO remaps this 383 384 <enum 15 reo_destination_15> REO remaps this 385 386 <enum 16 reo_destination_16> REO remaps this 387 388 <enum 17 reo_destination_17> REO remaps this 389 390 <enum 18 reo_destination_18> REO remaps this 391 392 <enum 19 reo_destination_19> REO remaps this 393 394 <enum 20 reo_destination_20> REO remaps this 395 396 <enum 21 reo_destination_21> REO remaps this 397 398 <enum 22 reo_destination_22> REO remaps this 399 400 <enum 23 reo_destination_23> REO remaps this 401 402 <enum 24 reo_destination_24> REO remaps this 403 404 <enum 25 reo_destination_25> REO remaps this 405 406 <enum 26 reo_destination_26> REO remaps this 407 408 <enum 27 reo_destination_27> REO remaps this 409 410 <enum 28 reo_destination_28> REO remaps this 411 412 <enum 29 reo_destination_29> REO remaps this 413 414 <enum 30 reo_destination_30> REO remaps this 415 416 <enum 31 reo_destination_31> REO remaps this 417 418 419 420 <legal all> 421 */ 422 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000008 423 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 424 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 425 426 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP 427 428 Parsed from RX_MSDU_END TLV . In the case MSDU spans 429 over multiple buffers, this field will be valid in the Last 430 buffer used by the MSDU 431 432 433 434 When set, REO shall drop this MSDU and not forward it to 435 any other ring... 436 437 <legal all> 438 */ 439 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008 440 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 441 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 442 443 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID 444 445 Parsed from RX_MSDU_END TLV . In the case MSDU spans 446 over multiple buffers, this field will be valid in the Last 447 buffer used by the MSDU 448 449 450 451 Indicates that OLE found a valid SA entry for this MSDU 452 453 <legal all> 454 */ 455 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 456 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 457 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 458 459 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 460 461 Parsed from RX_MSDU_END TLV . In the case MSDU spans 462 over multiple buffers, this field will be valid in the Last 463 buffer used by the MSDU 464 465 466 467 Indicates an unsuccessful MAC source address search due 468 to the expiring of the search timer for this MSDU 469 470 <legal all> 471 */ 472 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 473 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 474 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 475 476 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID 477 478 Parsed from RX_MSDU_END TLV . In the case MSDU spans 479 over multiple buffers, this field will be valid in the Last 480 buffer used by the MSDU 481 482 483 484 Indicates that OLE found a valid DA entry for this MSDU 485 486 <legal all> 487 */ 488 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 489 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 490 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 491 492 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC 493 494 Field Only valid if da_is_valid is set 495 496 497 498 Indicates the DA address was a Multicast of Broadcast 499 address for this MSDU 500 501 <legal all> 502 */ 503 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 504 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 505 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 506 507 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 508 509 Parsed from RX_MSDU_END TLV . In the case MSDU spans 510 over multiple buffers, this field will be valid in the Last 511 buffer used by the MSDU 512 513 514 515 Indicates an unsuccessful MAC destination address search 516 due to the expiring of the search timer for this MSDU 517 518 <legal all> 519 */ 520 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 521 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 522 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 523 524 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A 525 526 <legal 0> 527 */ 528 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000008 529 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28 530 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000 531 532 /* Description RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A 533 534 <legal 0> 535 */ 536 #define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000c 537 #define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0 538 #define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff 539 540 541 #endif // _RX_MSDU_DETAILS_H_ 542