1 /* 2 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 // $ATH_LICENSE_HW_HDR_C$ 18 // 19 // DO NOT EDIT! This file is automatically generated 20 // These definitions are tied to a particular hardware layout 21 22 23 #ifndef _RX_REO_QUEUE_H_ 24 #define _RX_REO_QUEUE_H_ 25 #if !defined(__ASSEMBLER__) 26 #endif 27 28 #include "uniform_descriptor_header.h" 29 30 // ################ START SUMMARY ################# 31 // 32 // Dword Fields 33 // 0 struct uniform_descriptor_header descriptor_header; 34 // 1 receive_queue_number[15:0], reserved_1b[31:16] 35 // 2 vld[0], associated_link_descriptor_counter[2:1], disable_duplicate_detection[3], soft_reorder_enable[4], ac[6:5], bar[7], rty[8], chk_2k_mode[9], oor_mode[10], ba_window_size[18:11], pn_check_needed[19], pn_shall_be_even[20], pn_shall_be_uneven[21], pn_handling_enable[22], pn_size[24:23], ignore_ampdu_flag[25], reserved_2b[31:26] 36 // 3 svld[0], ssn[12:1], current_index[20:13], seq_2k_error_detected_flag[21], pn_error_detected_flag[22], reserved_3a[30:23], pn_valid[31] 37 // 4 pn_31_0[31:0] 38 // 5 pn_63_32[31:0] 39 // 6 pn_95_64[31:0] 40 // 7 pn_127_96[31:0] 41 // 8 last_rx_enqueue_timestamp[31:0] 42 // 9 last_rx_dequeue_timestamp[31:0] 43 // 10 ptr_to_next_aging_queue_31_0[31:0] 44 // 11 ptr_to_next_aging_queue_39_32[7:0], reserved_11a[31:8] 45 // 12 ptr_to_previous_aging_queue_31_0[31:0] 46 // 13 ptr_to_previous_aging_queue_39_32[7:0], reserved_13a[31:8] 47 // 14 rx_bitmap_31_0[31:0] 48 // 15 rx_bitmap_63_32[31:0] 49 // 16 rx_bitmap_95_64[31:0] 50 // 17 rx_bitmap_127_96[31:0] 51 // 18 rx_bitmap_159_128[31:0] 52 // 19 rx_bitmap_191_160[31:0] 53 // 20 rx_bitmap_223_192[31:0] 54 // 21 rx_bitmap_255_224[31:0] 55 // 22 current_mpdu_count[6:0], current_msdu_count[31:7] 56 // 23 reserved_23[3:0], timeout_count[9:4], forward_due_to_bar_count[15:10], duplicate_count[31:16] 57 // 24 frames_in_order_count[23:0], bar_received_count[31:24] 58 // 25 mpdu_frames_processed_count[31:0] 59 // 26 msdu_frames_processed_count[31:0] 60 // 27 total_processed_byte_count[31:0] 61 // 28 late_receive_mpdu_count[11:0], window_jump_2k[15:12], hole_count[31:16] 62 // 29 reserved_29[31:0] 63 // 30 reserved_30[31:0] 64 // 31 reserved_31[31:0] 65 // 66 // ################ END SUMMARY ################# 67 68 #define NUM_OF_DWORDS_RX_REO_QUEUE 32 69 70 struct rx_reo_queue { 71 struct uniform_descriptor_header descriptor_header; 72 uint32_t receive_queue_number : 16, //[15:0] 73 reserved_1b : 16; //[31:16] 74 uint32_t vld : 1, //[0] 75 associated_link_descriptor_counter: 2, //[2:1] 76 disable_duplicate_detection : 1, //[3] 77 soft_reorder_enable : 1, //[4] 78 ac : 2, //[6:5] 79 bar : 1, //[7] 80 rty : 1, //[8] 81 chk_2k_mode : 1, //[9] 82 oor_mode : 1, //[10] 83 ba_window_size : 8, //[18:11] 84 pn_check_needed : 1, //[19] 85 pn_shall_be_even : 1, //[20] 86 pn_shall_be_uneven : 1, //[21] 87 pn_handling_enable : 1, //[22] 88 pn_size : 2, //[24:23] 89 ignore_ampdu_flag : 1, //[25] 90 reserved_2b : 6; //[31:26] 91 uint32_t svld : 1, //[0] 92 ssn : 12, //[12:1] 93 current_index : 8, //[20:13] 94 seq_2k_error_detected_flag : 1, //[21] 95 pn_error_detected_flag : 1, //[22] 96 reserved_3a : 8, //[30:23] 97 pn_valid : 1; //[31] 98 uint32_t pn_31_0 : 32; //[31:0] 99 uint32_t pn_63_32 : 32; //[31:0] 100 uint32_t pn_95_64 : 32; //[31:0] 101 uint32_t pn_127_96 : 32; //[31:0] 102 uint32_t last_rx_enqueue_timestamp : 32; //[31:0] 103 uint32_t last_rx_dequeue_timestamp : 32; //[31:0] 104 uint32_t ptr_to_next_aging_queue_31_0 : 32; //[31:0] 105 uint32_t ptr_to_next_aging_queue_39_32 : 8, //[7:0] 106 reserved_11a : 24; //[31:8] 107 uint32_t ptr_to_previous_aging_queue_31_0: 32; //[31:0] 108 uint32_t ptr_to_previous_aging_queue_39_32: 8, //[7:0] 109 reserved_13a : 24; //[31:8] 110 uint32_t rx_bitmap_31_0 : 32; //[31:0] 111 uint32_t rx_bitmap_63_32 : 32; //[31:0] 112 uint32_t rx_bitmap_95_64 : 32; //[31:0] 113 uint32_t rx_bitmap_127_96 : 32; //[31:0] 114 uint32_t rx_bitmap_159_128 : 32; //[31:0] 115 uint32_t rx_bitmap_191_160 : 32; //[31:0] 116 uint32_t rx_bitmap_223_192 : 32; //[31:0] 117 uint32_t rx_bitmap_255_224 : 32; //[31:0] 118 uint32_t current_mpdu_count : 7, //[6:0] 119 current_msdu_count : 25; //[31:7] 120 uint32_t reserved_23 : 4, //[3:0] 121 timeout_count : 6, //[9:4] 122 forward_due_to_bar_count : 6, //[15:10] 123 duplicate_count : 16; //[31:16] 124 uint32_t frames_in_order_count : 24, //[23:0] 125 bar_received_count : 8; //[31:24] 126 uint32_t mpdu_frames_processed_count : 32; //[31:0] 127 uint32_t msdu_frames_processed_count : 32; //[31:0] 128 uint32_t total_processed_byte_count : 32; //[31:0] 129 uint32_t late_receive_mpdu_count : 12, //[11:0] 130 window_jump_2k : 4, //[15:12] 131 hole_count : 16; //[31:16] 132 uint32_t reserved_29 : 32; //[31:0] 133 uint32_t reserved_30 : 32; //[31:0] 134 uint32_t reserved_31 : 32; //[31:0] 135 }; 136 137 /* 138 139 struct uniform_descriptor_header descriptor_header 140 141 Details about which module owns this struct. 142 143 Note that sub field Buffer_type shall be set to 144 Receive_REO_queue_descriptor 145 146 receive_queue_number 147 148 Indicates the MPDU queue ID to which this MPDU link 149 descriptor belongs 150 151 Used for tracking and debugging 152 153 <legal all> 154 155 reserved_1b 156 157 <legal 0> 158 159 vld 160 161 Valid bit indicating a session is established and the 162 queue descriptor is valid(Filled by SW) 163 164 <legal all> 165 166 associated_link_descriptor_counter 167 168 Indicates which of the 3 link descriptor counters shall 169 be incremented or decremented when link descriptors are 170 added or removed from this flow queue. 171 172 MSDU link descriptors related with MPDUs stored in the 173 re-order buffer shall also be included in this count. 174 175 176 177 <legal 0-2> 178 179 disable_duplicate_detection 180 181 When set, do not perform any duplicate detection. 182 183 184 185 <legal all> 186 187 soft_reorder_enable 188 189 When set, REO has been instructed to not perform the 190 actual re-ordering of frames for this queue, but just to 191 insert the reorder opcodes. 192 193 194 195 Note that this implies that REO is also not going to 196 perform any MSDU level operations, and the entire MPDU (and 197 thus pointer to the MSDU link descriptor) will be pushed to 198 a destination ring that SW has programmed in a SW 199 programmable configuration register in REO 200 201 202 203 <legal all> 204 205 ac 206 207 Indicates which access category the queue descriptor 208 belongs to(filled by SW) 209 210 <legal all> 211 212 bar 213 214 Indicates if BAR has been received (mostly used for 215 debug purpose and this is filled by REO) 216 217 <legal all> 218 219 rty 220 221 Retry bit is checked if this bit is set. 222 223 <legal all> 224 225 chk_2k_mode 226 227 Indicates what type of operation is expected from Reo 228 when the received frame SN falls within the 2K window 229 230 231 232 See REO MLD document for programming details. 233 234 <legal all> 235 236 oor_mode 237 238 Out of Order mode: 239 240 Indicates what type of operation is expected when the 241 received frame falls within the OOR window. 242 243 244 245 See REO MLD document for programming details. 246 247 <legal all> 248 249 ba_window_size 250 251 Indicates the negotiated (window size + 1). 252 253 it can go up to Max of 256bits. 254 255 256 257 A value 255 means 256 bitmap, 63 means 64 bitmap, 0 258 (means non-BA session, with window size of 0). The 3 values 259 here are the main values validated, but other values should 260 work as well. 261 262 263 264 A BA window size of 0 (=> one frame entry bitmat), means 265 that there is NO RX_REO_QUEUE_EXT descriptor following this 266 RX_REO_QUEUE STRUCT in memory 267 268 269 270 A BA window size of 1 - 105, means that there is 1 271 RX_REO_QUEUE_EXT descriptor directly following this 272 RX_REO_QUEUE STRUCT in memory. 273 274 275 276 A BA window size of 106 - 210, means that there are 2 277 RX_REO_QUEUE_EXT descriptors directly following this 278 RX_REO_QUEUE STRUCT in memory 279 280 281 282 A BA window size of 211 - 256, means that there are 3 283 RX_REO_QUEUE_EXT descriptors directly following this 284 RX_REO_QUEUE STRUCT in memory 285 286 287 288 <legal 0 - 255> 289 290 pn_check_needed 291 292 When set, REO shall perform the PN increment check 293 294 <legal all> 295 296 pn_shall_be_even 297 298 Field only valid when 'pn_check_needed' is set. 299 300 301 302 When set, REO shall confirm that the received PN number 303 is not only incremented, but also always an even number 304 305 <legal all> 306 307 pn_shall_be_uneven 308 309 Field only valid when 'pn_check_needed' is set. 310 311 312 313 When set, REO shall confirm that the received PN number 314 is not only incremented, but also always an uneven number 315 316 <legal all> 317 318 pn_handling_enable 319 320 Field only valid when 'pn_check_needed' is set. 321 322 323 324 When set, and REO detected a PN error, HW shall set the 325 'pn_error_detected_flag'. 326 327 <legal all> 328 329 pn_size 330 331 Size of the PN field check. 332 333 Needed for wrap around handling... 334 335 336 337 <enum 0 pn_size_24> 338 339 <enum 1 pn_size_48> 340 341 <enum 2 pn_size_128> 342 343 344 345 <legal 0-2> 346 347 ignore_ampdu_flag 348 349 When set, REO shall ignore the ampdu_flag on the 350 entrance descriptor for this queue. 351 352 <legal all> 353 354 reserved_2b 355 356 <legal 0> 357 358 svld 359 360 Sequence number in next field is valid one. It can be 361 filled by SW if the want to fill in the any negotiated SSN, 362 otherwise REO will fill the sequence number of first 363 received packet and set this bit to 1. 364 365 <legal all> 366 367 ssn 368 369 Starting Sequence number of the session, this changes 370 whenever window moves. (can be filled by SW then maintained 371 by REO) 372 373 <legal all> 374 375 current_index 376 377 Points to last forwarded packet 378 379 <legal all> 380 381 seq_2k_error_detected_flag 382 383 Set by REO, can only be cleared by SW 384 385 386 387 When set, REO has detected a 2k error jump in the 388 sequence number and from that moment forward, all new frames 389 are forwarded directly to FW, without duplicate detect, 390 reordering, etc. 391 392 <legal all> 393 394 pn_error_detected_flag 395 396 Set by REO, can only be cleared by SW 397 398 399 400 When set, REO has detected a PN error and from that 401 moment forward, all new frames are forwarded directly to FW, 402 without duplicate detect, reordering, etc. 403 404 <legal all> 405 406 reserved_3a 407 408 <legal 0> 409 410 pn_valid 411 412 PN number in next fields are valid. It can be filled by 413 SW if it wants to fill in the any negotiated SSN, otherwise 414 REO will fill the pn based on the first received packet and 415 set this bit to 1. 416 417 <legal all> 418 419 pn_31_0 420 421 422 <legal all> 423 424 pn_63_32 425 426 Bits [63:32] of the PN number. 427 428 <legal all> 429 430 pn_95_64 431 432 Bits [95:64] of the PN number. 433 434 <legal all> 435 436 pn_127_96 437 438 Bits [127:96] of the PN number. 439 440 <legal all> 441 442 last_rx_enqueue_timestamp 443 444 This timestamp is updated when an MPDU is received and 445 accesses this Queue Descriptor. It does not include the 446 access due to Command TLVs or Aging (which will be updated 447 in Last_rx_dequeue_timestamp). 448 449 <legal all> 450 451 last_rx_dequeue_timestamp 452 453 This timestamp is used for Aging. When an MPDU or 454 multiple MPDUs are forwarded, either due to window movement, 455 bar, aging or command flush, this timestamp is updated. Also 456 when the bitmap is all zero and the first time an MPDU is 457 queued (opcode=QCUR), this timestamp is updated for aging. 458 459 <legal all> 460 461 ptr_to_next_aging_queue_31_0 462 463 Address (address bits 31-0)of next RX_REO_QUEUE 464 descriptor in the 'receive timestamp' ordered list. 465 466 From it the Position of this queue descriptor in the per 467 AC aging waitlist can be derived. 468 469 Value 0x0 indicates the 'NULL' pointer which implies 470 that this is the last entry in the list. 471 472 <legal all> 473 474 ptr_to_next_aging_queue_39_32 475 476 Address (address bits 39-32)of next RX_REO_QUEUE 477 descriptor in the 'receive timestamp' ordered list. 478 479 From it the Position of this queue descriptor in the per 480 AC aging waitlist can be derived. 481 482 Value 0x0 indicates the 'NULL' pointer which implies 483 that this is the last entry in the list. 484 485 <legal all> 486 487 reserved_11a 488 489 <legal 0> 490 491 ptr_to_previous_aging_queue_31_0 492 493 Address (address bits 31-0)of next RX_REO_QUEUE 494 descriptor in the 'receive timestamp' ordered list. 495 496 From it the Position of this queue descriptor in the per 497 AC aging waitlist can be derived. 498 499 Value 0x0 indicates the 'NULL' pointer which implies 500 that this is the first entry in the list. 501 502 <legal all> 503 504 ptr_to_previous_aging_queue_39_32 505 506 Address (address bits 39-32)of next RX_REO_QUEUE 507 descriptor in the 'receive timestamp' ordered list. 508 509 From it the Position of this queue descriptor in the per 510 AC aging waitlist can be derived. 511 512 Value 0x0 indicates the 'NULL' pointer which implies 513 that this is the first entry in the list. 514 515 <legal all> 516 517 reserved_13a 518 519 <legal 0> 520 521 rx_bitmap_31_0 522 523 When a bit is set, the corresponding frame is currently 524 held in the re-order queue. 525 526 The bitmap is Fully managed by HW. 527 528 SW shall init this to 0, and then never ever change it 529 530 <legal all> 531 532 rx_bitmap_63_32 533 534 See Rx_bitmap_31_0 description 535 536 <legal all> 537 538 rx_bitmap_95_64 539 540 See Rx_bitmap_31_0 description 541 542 <legal all> 543 544 rx_bitmap_127_96 545 546 See Rx_bitmap_31_0 description 547 548 <legal all> 549 550 rx_bitmap_159_128 551 552 See Rx_bitmap_31_0 description 553 554 <legal all> 555 556 rx_bitmap_191_160 557 558 See Rx_bitmap_31_0 description 559 560 <legal all> 561 562 rx_bitmap_223_192 563 564 See Rx_bitmap_31_0 description 565 566 <legal all> 567 568 rx_bitmap_255_224 569 570 See Rx_bitmap_31_0 description 571 572 <legal all> 573 574 current_mpdu_count 575 576 The number of MPDUs in the queue. 577 578 579 580 <legal all> 581 582 current_msdu_count 583 584 The number of MSDUs in the queue. 585 586 <legal all> 587 588 reserved_23 589 590 <legal 0> 591 592 timeout_count 593 594 The number of times that REO started forwarding frames 595 even though there is a hole in the bitmap. Forwarding reason 596 is Timeout 597 598 599 600 The counter saturates and freezes at 0x3F 601 602 603 604 <legal all> 605 606 forward_due_to_bar_count 607 608 The number of times that REO started forwarding frames 609 even though there is a hole in the bitmap. Forwarding reason 610 is reception of BAR frame. 611 612 613 614 The counter saturates and freezes at 0x3F 615 616 617 618 <legal all> 619 620 duplicate_count 621 622 The number of duplicate frames that have been detected 623 624 <legal all> 625 626 frames_in_order_count 627 628 The number of frames that have been received in order 629 (without a hole that prevented them from being forwarded 630 immediately) 631 632 633 634 This corresponds to the Reorder opcodes: 635 636 'FWDCUR' and 'FWD BUF' 637 638 639 640 <legal all> 641 642 bar_received_count 643 644 The number of times a BAR frame is received. 645 646 647 648 This corresponds to the Reorder opcodes with 'DROP' 649 650 651 652 The counter saturates and freezes at 0xFF 653 654 <legal all> 655 656 mpdu_frames_processed_count 657 658 The total number of MPDU frames that have been processed 659 by REO. 'Processing' here means that REO has received them 660 out of the entrance ring, and retrieved the corresponding 661 RX_REO_QUEUE Descriptor. 662 663 664 665 Note that this count includes duplicates, frames that 666 later had errors, etc. 667 668 669 670 Note that field 'Duplicate_count' indicates how many of 671 these MPDUs were duplicates. 672 673 674 675 <legal all> 676 677 msdu_frames_processed_count 678 679 The total number of MSDU frames that have been processed 680 by REO. 'Processing' here means that REO has received them 681 out of the entrance ring, and retrieved the corresponding 682 RX_REO_QUEUE Descriptor. 683 684 685 686 Note that this count includes duplicates, frames that 687 later had errors, etc. 688 689 690 691 <legal all> 692 693 total_processed_byte_count 694 695 An approximation of the number of bytes processed for 696 this queue. 697 698 'Processing' here means that REO has received them out 699 of the entrance ring, and retrieved the corresponding 700 RX_REO_QUEUE Descriptor. 701 702 703 704 Note that this count includes duplicates, frames that 705 later had errors, etc. 706 707 708 709 In 64 byte units 710 711 <legal all> 712 713 late_receive_mpdu_count 714 715 The number of MPDUs received after the window had 716 already moved on. The 'late' sequence window is defined as 717 (Window SSN - 256) - (Window SSN - 1) 718 719 720 721 This corresponds with Out of order detection in 722 duplicate detect FSM 723 724 725 726 The counter saturates and freezes at 0xFFF 727 728 729 730 <legal all> 731 732 window_jump_2k 733 734 The number of times the window moved more then 2K 735 736 737 738 The counter saturates and freezes at 0xF 739 740 741 742 (Note: field name can not start with number: previous 743 2k_window_jump) 744 745 746 747 <legal all> 748 749 hole_count 750 751 The number of times a hole was created in the receive 752 bitmap. 753 754 755 756 This corresponds to the Reorder opcodes with 'QCUR' 757 758 759 760 <legal all> 761 762 reserved_29 763 764 <legal 0> 765 766 reserved_30 767 768 <legal 0> 769 770 reserved_31 771 772 <legal 0> 773 */ 774 775 776 /* EXTERNAL REFERENCE : struct uniform_descriptor_header descriptor_header */ 777 778 779 /* Description RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER 780 781 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 782 783 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 784 785 786 787 The owner of this data structure: 788 789 <enum 0 WBM_owned> Buffer Manager currently owns this 790 data structure. 791 792 <enum 1 SW_OR_FW_owned> Software of FW currently owns 793 this data structure. 794 795 <enum 2 TQM_owned> Transmit Queue Manager currently owns 796 this data structure. 797 798 <enum 3 RXDMA_owned> Receive DMA currently owns this 799 data structure. 800 801 <enum 4 REO_owned> Reorder currently owns this data 802 structure. 803 804 <enum 5 SWITCH_owned> SWITCH currently owns this data 805 structure. 806 807 808 809 <legal 0-5> 810 */ 811 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 812 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_LSB 0 813 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 814 815 /* Description RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE 816 817 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 818 819 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 820 821 822 823 Field describing what contents format is of this 824 descriptor 825 826 827 828 <enum 0 Transmit_MSDU_Link_descriptor > 829 830 <enum 1 Transmit_MPDU_Link_descriptor > 831 832 <enum 2 Transmit_MPDU_Queue_head_descriptor> 833 834 <enum 3 Transmit_MPDU_Queue_ext_descriptor> 835 836 <enum 4 Transmit_flow_descriptor> 837 838 <enum 5 Transmit_buffer > NOT TO BE USED: 839 840 841 842 <enum 6 Receive_MSDU_Link_descriptor > 843 844 <enum 7 Receive_MPDU_Link_descriptor > 845 846 <enum 8 Receive_REO_queue_descriptor > 847 848 <enum 9 Receive_REO_queue_ext_descriptor > 849 850 851 852 <enum 10 Receive_buffer > 853 854 855 856 <enum 11 Idle_link_list_entry> 857 858 859 860 <legal 0-11> 861 */ 862 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 863 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 864 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 865 866 /* Description RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A 867 868 <legal 0> 869 */ 870 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 871 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 872 #define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 873 874 /* Description RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER 875 876 Indicates the MPDU queue ID to which this MPDU link 877 descriptor belongs 878 879 Used for tracking and debugging 880 881 <legal all> 882 */ 883 #define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 884 #define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_LSB 0 885 #define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff 886 887 /* Description RX_REO_QUEUE_1_RESERVED_1B 888 889 <legal 0> 890 */ 891 #define RX_REO_QUEUE_1_RESERVED_1B_OFFSET 0x00000004 892 #define RX_REO_QUEUE_1_RESERVED_1B_LSB 16 893 #define RX_REO_QUEUE_1_RESERVED_1B_MASK 0xffff0000 894 895 /* Description RX_REO_QUEUE_2_VLD 896 897 Valid bit indicating a session is established and the 898 queue descriptor is valid(Filled by SW) 899 900 <legal all> 901 */ 902 #define RX_REO_QUEUE_2_VLD_OFFSET 0x00000008 903 #define RX_REO_QUEUE_2_VLD_LSB 0 904 #define RX_REO_QUEUE_2_VLD_MASK 0x00000001 905 906 /* Description RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER 907 908 Indicates which of the 3 link descriptor counters shall 909 be incremented or decremented when link descriptors are 910 added or removed from this flow queue. 911 912 MSDU link descriptors related with MPDUs stored in the 913 re-order buffer shall also be included in this count. 914 915 916 917 <legal 0-2> 918 */ 919 #define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 920 #define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 1 921 #define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000006 922 923 /* Description RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION 924 925 When set, do not perform any duplicate detection. 926 927 928 929 <legal all> 930 */ 931 #define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 932 #define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_LSB 3 933 #define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_MASK 0x00000008 934 935 /* Description RX_REO_QUEUE_2_SOFT_REORDER_ENABLE 936 937 When set, REO has been instructed to not perform the 938 actual re-ordering of frames for this queue, but just to 939 insert the reorder opcodes. 940 941 942 943 Note that this implies that REO is also not going to 944 perform any MSDU level operations, and the entire MPDU (and 945 thus pointer to the MSDU link descriptor) will be pushed to 946 a destination ring that SW has programmed in a SW 947 programmable configuration register in REO 948 949 950 951 <legal all> 952 */ 953 #define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_OFFSET 0x00000008 954 #define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_LSB 4 955 #define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_MASK 0x00000010 956 957 /* Description RX_REO_QUEUE_2_AC 958 959 Indicates which access category the queue descriptor 960 belongs to(filled by SW) 961 962 <legal all> 963 */ 964 #define RX_REO_QUEUE_2_AC_OFFSET 0x00000008 965 #define RX_REO_QUEUE_2_AC_LSB 5 966 #define RX_REO_QUEUE_2_AC_MASK 0x00000060 967 968 /* Description RX_REO_QUEUE_2_BAR 969 970 Indicates if BAR has been received (mostly used for 971 debug purpose and this is filled by REO) 972 973 <legal all> 974 */ 975 #define RX_REO_QUEUE_2_BAR_OFFSET 0x00000008 976 #define RX_REO_QUEUE_2_BAR_LSB 7 977 #define RX_REO_QUEUE_2_BAR_MASK 0x00000080 978 979 /* Description RX_REO_QUEUE_2_RTY 980 981 Retry bit is checked if this bit is set. 982 983 <legal all> 984 */ 985 #define RX_REO_QUEUE_2_RTY_OFFSET 0x00000008 986 #define RX_REO_QUEUE_2_RTY_LSB 8 987 #define RX_REO_QUEUE_2_RTY_MASK 0x00000100 988 989 /* Description RX_REO_QUEUE_2_CHK_2K_MODE 990 991 Indicates what type of operation is expected from Reo 992 when the received frame SN falls within the 2K window 993 994 995 996 See REO MLD document for programming details. 997 998 <legal all> 999 */ 1000 #define RX_REO_QUEUE_2_CHK_2K_MODE_OFFSET 0x00000008 1001 #define RX_REO_QUEUE_2_CHK_2K_MODE_LSB 9 1002 #define RX_REO_QUEUE_2_CHK_2K_MODE_MASK 0x00000200 1003 1004 /* Description RX_REO_QUEUE_2_OOR_MODE 1005 1006 Out of Order mode: 1007 1008 Indicates what type of operation is expected when the 1009 received frame falls within the OOR window. 1010 1011 1012 1013 See REO MLD document for programming details. 1014 1015 <legal all> 1016 */ 1017 #define RX_REO_QUEUE_2_OOR_MODE_OFFSET 0x00000008 1018 #define RX_REO_QUEUE_2_OOR_MODE_LSB 10 1019 #define RX_REO_QUEUE_2_OOR_MODE_MASK 0x00000400 1020 1021 /* Description RX_REO_QUEUE_2_BA_WINDOW_SIZE 1022 1023 Indicates the negotiated (window size + 1). 1024 1025 it can go up to Max of 256bits. 1026 1027 1028 1029 A value 255 means 256 bitmap, 63 means 64 bitmap, 0 1030 (means non-BA session, with window size of 0). The 3 values 1031 here are the main values validated, but other values should 1032 work as well. 1033 1034 1035 1036 A BA window size of 0 (=> one frame entry bitmat), means 1037 that there is NO RX_REO_QUEUE_EXT descriptor following this 1038 RX_REO_QUEUE STRUCT in memory 1039 1040 1041 1042 A BA window size of 1 - 105, means that there is 1 1043 RX_REO_QUEUE_EXT descriptor directly following this 1044 RX_REO_QUEUE STRUCT in memory. 1045 1046 1047 1048 A BA window size of 106 - 210, means that there are 2 1049 RX_REO_QUEUE_EXT descriptors directly following this 1050 RX_REO_QUEUE STRUCT in memory 1051 1052 1053 1054 A BA window size of 211 - 256, means that there are 3 1055 RX_REO_QUEUE_EXT descriptors directly following this 1056 RX_REO_QUEUE STRUCT in memory 1057 1058 1059 1060 <legal 0 - 255> 1061 */ 1062 #define RX_REO_QUEUE_2_BA_WINDOW_SIZE_OFFSET 0x00000008 1063 #define RX_REO_QUEUE_2_BA_WINDOW_SIZE_LSB 11 1064 #define RX_REO_QUEUE_2_BA_WINDOW_SIZE_MASK 0x0007f800 1065 1066 /* Description RX_REO_QUEUE_2_PN_CHECK_NEEDED 1067 1068 When set, REO shall perform the PN increment check 1069 1070 <legal all> 1071 */ 1072 #define RX_REO_QUEUE_2_PN_CHECK_NEEDED_OFFSET 0x00000008 1073 #define RX_REO_QUEUE_2_PN_CHECK_NEEDED_LSB 19 1074 #define RX_REO_QUEUE_2_PN_CHECK_NEEDED_MASK 0x00080000 1075 1076 /* Description RX_REO_QUEUE_2_PN_SHALL_BE_EVEN 1077 1078 Field only valid when 'pn_check_needed' is set. 1079 1080 1081 1082 When set, REO shall confirm that the received PN number 1083 is not only incremented, but also always an even number 1084 1085 <legal all> 1086 */ 1087 #define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_OFFSET 0x00000008 1088 #define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_LSB 20 1089 #define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_MASK 0x00100000 1090 1091 /* Description RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN 1092 1093 Field only valid when 'pn_check_needed' is set. 1094 1095 1096 1097 When set, REO shall confirm that the received PN number 1098 is not only incremented, but also always an uneven number 1099 1100 <legal all> 1101 */ 1102 #define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 1103 #define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_LSB 21 1104 #define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_MASK 0x00200000 1105 1106 /* Description RX_REO_QUEUE_2_PN_HANDLING_ENABLE 1107 1108 Field only valid when 'pn_check_needed' is set. 1109 1110 1111 1112 When set, and REO detected a PN error, HW shall set the 1113 'pn_error_detected_flag'. 1114 1115 <legal all> 1116 */ 1117 #define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_OFFSET 0x00000008 1118 #define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_LSB 22 1119 #define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_MASK 0x00400000 1120 1121 /* Description RX_REO_QUEUE_2_PN_SIZE 1122 1123 Size of the PN field check. 1124 1125 Needed for wrap around handling... 1126 1127 1128 1129 <enum 0 pn_size_24> 1130 1131 <enum 1 pn_size_48> 1132 1133 <enum 2 pn_size_128> 1134 1135 1136 1137 <legal 0-2> 1138 */ 1139 #define RX_REO_QUEUE_2_PN_SIZE_OFFSET 0x00000008 1140 #define RX_REO_QUEUE_2_PN_SIZE_LSB 23 1141 #define RX_REO_QUEUE_2_PN_SIZE_MASK 0x01800000 1142 1143 /* Description RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG 1144 1145 When set, REO shall ignore the ampdu_flag on the 1146 entrance descriptor for this queue. 1147 1148 <legal all> 1149 */ 1150 #define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 1151 #define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_LSB 25 1152 #define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_MASK 0x02000000 1153 1154 /* Description RX_REO_QUEUE_2_RESERVED_2B 1155 1156 <legal 0> 1157 */ 1158 #define RX_REO_QUEUE_2_RESERVED_2B_OFFSET 0x00000008 1159 #define RX_REO_QUEUE_2_RESERVED_2B_LSB 26 1160 #define RX_REO_QUEUE_2_RESERVED_2B_MASK 0xfc000000 1161 1162 /* Description RX_REO_QUEUE_3_SVLD 1163 1164 Sequence number in next field is valid one. It can be 1165 filled by SW if the want to fill in the any negotiated SSN, 1166 otherwise REO will fill the sequence number of first 1167 received packet and set this bit to 1. 1168 1169 <legal all> 1170 */ 1171 #define RX_REO_QUEUE_3_SVLD_OFFSET 0x0000000c 1172 #define RX_REO_QUEUE_3_SVLD_LSB 0 1173 #define RX_REO_QUEUE_3_SVLD_MASK 0x00000001 1174 1175 /* Description RX_REO_QUEUE_3_SSN 1176 1177 Starting Sequence number of the session, this changes 1178 whenever window moves. (can be filled by SW then maintained 1179 by REO) 1180 1181 <legal all> 1182 */ 1183 #define RX_REO_QUEUE_3_SSN_OFFSET 0x0000000c 1184 #define RX_REO_QUEUE_3_SSN_LSB 1 1185 #define RX_REO_QUEUE_3_SSN_MASK 0x00001ffe 1186 1187 /* Description RX_REO_QUEUE_3_CURRENT_INDEX 1188 1189 Points to last forwarded packet 1190 1191 <legal all> 1192 */ 1193 #define RX_REO_QUEUE_3_CURRENT_INDEX_OFFSET 0x0000000c 1194 #define RX_REO_QUEUE_3_CURRENT_INDEX_LSB 13 1195 #define RX_REO_QUEUE_3_CURRENT_INDEX_MASK 0x001fe000 1196 1197 /* Description RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG 1198 1199 Set by REO, can only be cleared by SW 1200 1201 1202 1203 When set, REO has detected a 2k error jump in the 1204 sequence number and from that moment forward, all new frames 1205 are forwarded directly to FW, without duplicate detect, 1206 reordering, etc. 1207 1208 <legal all> 1209 */ 1210 #define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000c 1211 #define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_LSB 21 1212 #define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00200000 1213 1214 /* Description RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG 1215 1216 Set by REO, can only be cleared by SW 1217 1218 1219 1220 When set, REO has detected a PN error and from that 1221 moment forward, all new frames are forwarded directly to FW, 1222 without duplicate detect, reordering, etc. 1223 1224 <legal all> 1225 */ 1226 #define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000c 1227 #define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_LSB 22 1228 #define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_MASK 0x00400000 1229 1230 /* Description RX_REO_QUEUE_3_RESERVED_3A 1231 1232 <legal 0> 1233 */ 1234 #define RX_REO_QUEUE_3_RESERVED_3A_OFFSET 0x0000000c 1235 #define RX_REO_QUEUE_3_RESERVED_3A_LSB 23 1236 #define RX_REO_QUEUE_3_RESERVED_3A_MASK 0x7f800000 1237 1238 /* Description RX_REO_QUEUE_3_PN_VALID 1239 1240 PN number in next fields are valid. It can be filled by 1241 SW if it wants to fill in the any negotiated SSN, otherwise 1242 REO will fill the pn based on the first received packet and 1243 set this bit to 1. 1244 1245 <legal all> 1246 */ 1247 #define RX_REO_QUEUE_3_PN_VALID_OFFSET 0x0000000c 1248 #define RX_REO_QUEUE_3_PN_VALID_LSB 31 1249 #define RX_REO_QUEUE_3_PN_VALID_MASK 0x80000000 1250 1251 /* Description RX_REO_QUEUE_4_PN_31_0 1252 1253 1254 <legal all> 1255 */ 1256 #define RX_REO_QUEUE_4_PN_31_0_OFFSET 0x00000010 1257 #define RX_REO_QUEUE_4_PN_31_0_LSB 0 1258 #define RX_REO_QUEUE_4_PN_31_0_MASK 0xffffffff 1259 1260 /* Description RX_REO_QUEUE_5_PN_63_32 1261 1262 Bits [63:32] of the PN number. 1263 1264 <legal all> 1265 */ 1266 #define RX_REO_QUEUE_5_PN_63_32_OFFSET 0x00000014 1267 #define RX_REO_QUEUE_5_PN_63_32_LSB 0 1268 #define RX_REO_QUEUE_5_PN_63_32_MASK 0xffffffff 1269 1270 /* Description RX_REO_QUEUE_6_PN_95_64 1271 1272 Bits [95:64] of the PN number. 1273 1274 <legal all> 1275 */ 1276 #define RX_REO_QUEUE_6_PN_95_64_OFFSET 0x00000018 1277 #define RX_REO_QUEUE_6_PN_95_64_LSB 0 1278 #define RX_REO_QUEUE_6_PN_95_64_MASK 0xffffffff 1279 1280 /* Description RX_REO_QUEUE_7_PN_127_96 1281 1282 Bits [127:96] of the PN number. 1283 1284 <legal all> 1285 */ 1286 #define RX_REO_QUEUE_7_PN_127_96_OFFSET 0x0000001c 1287 #define RX_REO_QUEUE_7_PN_127_96_LSB 0 1288 #define RX_REO_QUEUE_7_PN_127_96_MASK 0xffffffff 1289 1290 /* Description RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP 1291 1292 This timestamp is updated when an MPDU is received and 1293 accesses this Queue Descriptor. It does not include the 1294 access due to Command TLVs or Aging (which will be updated 1295 in Last_rx_dequeue_timestamp). 1296 1297 <legal all> 1298 */ 1299 #define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020 1300 #define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 1301 #define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff 1302 1303 /* Description RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP 1304 1305 This timestamp is used for Aging. When an MPDU or 1306 multiple MPDUs are forwarded, either due to window movement, 1307 bar, aging or command flush, this timestamp is updated. Also 1308 when the bitmap is all zero and the first time an MPDU is 1309 queued (opcode=QCUR), this timestamp is updated for aging. 1310 1311 <legal all> 1312 */ 1313 #define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024 1314 #define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 1315 #define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff 1316 1317 /* Description RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0 1318 1319 Address (address bits 31-0)of next RX_REO_QUEUE 1320 descriptor in the 'receive timestamp' ordered list. 1321 1322 From it the Position of this queue descriptor in the per 1323 AC aging waitlist can be derived. 1324 1325 Value 0x0 indicates the 'NULL' pointer which implies 1326 that this is the last entry in the list. 1327 1328 <legal all> 1329 */ 1330 #define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET 0x00000028 1331 #define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB 0 1332 #define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK 0xffffffff 1333 1334 /* Description RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32 1335 1336 Address (address bits 39-32)of next RX_REO_QUEUE 1337 descriptor in the 'receive timestamp' ordered list. 1338 1339 From it the Position of this queue descriptor in the per 1340 AC aging waitlist can be derived. 1341 1342 Value 0x0 indicates the 'NULL' pointer which implies 1343 that this is the last entry in the list. 1344 1345 <legal all> 1346 */ 1347 #define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET 0x0000002c 1348 #define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB 0 1349 #define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK 0x000000ff 1350 1351 /* Description RX_REO_QUEUE_11_RESERVED_11A 1352 1353 <legal 0> 1354 */ 1355 #define RX_REO_QUEUE_11_RESERVED_11A_OFFSET 0x0000002c 1356 #define RX_REO_QUEUE_11_RESERVED_11A_LSB 8 1357 #define RX_REO_QUEUE_11_RESERVED_11A_MASK 0xffffff00 1358 1359 /* Description RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0 1360 1361 Address (address bits 31-0)of next RX_REO_QUEUE 1362 descriptor in the 'receive timestamp' ordered list. 1363 1364 From it the Position of this queue descriptor in the per 1365 AC aging waitlist can be derived. 1366 1367 Value 0x0 indicates the 'NULL' pointer which implies 1368 that this is the first entry in the list. 1369 1370 <legal all> 1371 */ 1372 #define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET 0x00000030 1373 #define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB 0 1374 #define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK 0xffffffff 1375 1376 /* Description RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32 1377 1378 Address (address bits 39-32)of next RX_REO_QUEUE 1379 descriptor in the 'receive timestamp' ordered list. 1380 1381 From it the Position of this queue descriptor in the per 1382 AC aging waitlist can be derived. 1383 1384 Value 0x0 indicates the 'NULL' pointer which implies 1385 that this is the first entry in the list. 1386 1387 <legal all> 1388 */ 1389 #define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET 0x00000034 1390 #define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB 0 1391 #define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK 0x000000ff 1392 1393 /* Description RX_REO_QUEUE_13_RESERVED_13A 1394 1395 <legal 0> 1396 */ 1397 #define RX_REO_QUEUE_13_RESERVED_13A_OFFSET 0x00000034 1398 #define RX_REO_QUEUE_13_RESERVED_13A_LSB 8 1399 #define RX_REO_QUEUE_13_RESERVED_13A_MASK 0xffffff00 1400 1401 /* Description RX_REO_QUEUE_14_RX_BITMAP_31_0 1402 1403 When a bit is set, the corresponding frame is currently 1404 held in the re-order queue. 1405 1406 The bitmap is Fully managed by HW. 1407 1408 SW shall init this to 0, and then never ever change it 1409 1410 <legal all> 1411 */ 1412 #define RX_REO_QUEUE_14_RX_BITMAP_31_0_OFFSET 0x00000038 1413 #define RX_REO_QUEUE_14_RX_BITMAP_31_0_LSB 0 1414 #define RX_REO_QUEUE_14_RX_BITMAP_31_0_MASK 0xffffffff 1415 1416 /* Description RX_REO_QUEUE_15_RX_BITMAP_63_32 1417 1418 See Rx_bitmap_31_0 description 1419 1420 <legal all> 1421 */ 1422 #define RX_REO_QUEUE_15_RX_BITMAP_63_32_OFFSET 0x0000003c 1423 #define RX_REO_QUEUE_15_RX_BITMAP_63_32_LSB 0 1424 #define RX_REO_QUEUE_15_RX_BITMAP_63_32_MASK 0xffffffff 1425 1426 /* Description RX_REO_QUEUE_16_RX_BITMAP_95_64 1427 1428 See Rx_bitmap_31_0 description 1429 1430 <legal all> 1431 */ 1432 #define RX_REO_QUEUE_16_RX_BITMAP_95_64_OFFSET 0x00000040 1433 #define RX_REO_QUEUE_16_RX_BITMAP_95_64_LSB 0 1434 #define RX_REO_QUEUE_16_RX_BITMAP_95_64_MASK 0xffffffff 1435 1436 /* Description RX_REO_QUEUE_17_RX_BITMAP_127_96 1437 1438 See Rx_bitmap_31_0 description 1439 1440 <legal all> 1441 */ 1442 #define RX_REO_QUEUE_17_RX_BITMAP_127_96_OFFSET 0x00000044 1443 #define RX_REO_QUEUE_17_RX_BITMAP_127_96_LSB 0 1444 #define RX_REO_QUEUE_17_RX_BITMAP_127_96_MASK 0xffffffff 1445 1446 /* Description RX_REO_QUEUE_18_RX_BITMAP_159_128 1447 1448 See Rx_bitmap_31_0 description 1449 1450 <legal all> 1451 */ 1452 #define RX_REO_QUEUE_18_RX_BITMAP_159_128_OFFSET 0x00000048 1453 #define RX_REO_QUEUE_18_RX_BITMAP_159_128_LSB 0 1454 #define RX_REO_QUEUE_18_RX_BITMAP_159_128_MASK 0xffffffff 1455 1456 /* Description RX_REO_QUEUE_19_RX_BITMAP_191_160 1457 1458 See Rx_bitmap_31_0 description 1459 1460 <legal all> 1461 */ 1462 #define RX_REO_QUEUE_19_RX_BITMAP_191_160_OFFSET 0x0000004c 1463 #define RX_REO_QUEUE_19_RX_BITMAP_191_160_LSB 0 1464 #define RX_REO_QUEUE_19_RX_BITMAP_191_160_MASK 0xffffffff 1465 1466 /* Description RX_REO_QUEUE_20_RX_BITMAP_223_192 1467 1468 See Rx_bitmap_31_0 description 1469 1470 <legal all> 1471 */ 1472 #define RX_REO_QUEUE_20_RX_BITMAP_223_192_OFFSET 0x00000050 1473 #define RX_REO_QUEUE_20_RX_BITMAP_223_192_LSB 0 1474 #define RX_REO_QUEUE_20_RX_BITMAP_223_192_MASK 0xffffffff 1475 1476 /* Description RX_REO_QUEUE_21_RX_BITMAP_255_224 1477 1478 See Rx_bitmap_31_0 description 1479 1480 <legal all> 1481 */ 1482 #define RX_REO_QUEUE_21_RX_BITMAP_255_224_OFFSET 0x00000054 1483 #define RX_REO_QUEUE_21_RX_BITMAP_255_224_LSB 0 1484 #define RX_REO_QUEUE_21_RX_BITMAP_255_224_MASK 0xffffffff 1485 1486 /* Description RX_REO_QUEUE_22_CURRENT_MPDU_COUNT 1487 1488 The number of MPDUs in the queue. 1489 1490 1491 1492 <legal all> 1493 */ 1494 #define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_OFFSET 0x00000058 1495 #define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_LSB 0 1496 #define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_MASK 0x0000007f 1497 1498 /* Description RX_REO_QUEUE_22_CURRENT_MSDU_COUNT 1499 1500 The number of MSDUs in the queue. 1501 1502 <legal all> 1503 */ 1504 #define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_OFFSET 0x00000058 1505 #define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_LSB 7 1506 #define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_MASK 0xffffff80 1507 1508 /* Description RX_REO_QUEUE_23_RESERVED_23 1509 1510 <legal 0> 1511 */ 1512 #define RX_REO_QUEUE_23_RESERVED_23_OFFSET 0x0000005c 1513 #define RX_REO_QUEUE_23_RESERVED_23_LSB 0 1514 #define RX_REO_QUEUE_23_RESERVED_23_MASK 0x0000000f 1515 1516 /* Description RX_REO_QUEUE_23_TIMEOUT_COUNT 1517 1518 The number of times that REO started forwarding frames 1519 even though there is a hole in the bitmap. Forwarding reason 1520 is Timeout 1521 1522 1523 1524 The counter saturates and freezes at 0x3F 1525 1526 1527 1528 <legal all> 1529 */ 1530 #define RX_REO_QUEUE_23_TIMEOUT_COUNT_OFFSET 0x0000005c 1531 #define RX_REO_QUEUE_23_TIMEOUT_COUNT_LSB 4 1532 #define RX_REO_QUEUE_23_TIMEOUT_COUNT_MASK 0x000003f0 1533 1534 /* Description RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT 1535 1536 The number of times that REO started forwarding frames 1537 even though there is a hole in the bitmap. Forwarding reason 1538 is reception of BAR frame. 1539 1540 1541 1542 The counter saturates and freezes at 0x3F 1543 1544 1545 1546 <legal all> 1547 */ 1548 #define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x0000005c 1549 #define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_LSB 10 1550 #define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 1551 1552 /* Description RX_REO_QUEUE_23_DUPLICATE_COUNT 1553 1554 The number of duplicate frames that have been detected 1555 1556 <legal all> 1557 */ 1558 #define RX_REO_QUEUE_23_DUPLICATE_COUNT_OFFSET 0x0000005c 1559 #define RX_REO_QUEUE_23_DUPLICATE_COUNT_LSB 16 1560 #define RX_REO_QUEUE_23_DUPLICATE_COUNT_MASK 0xffff0000 1561 1562 /* Description RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT 1563 1564 The number of frames that have been received in order 1565 (without a hole that prevented them from being forwarded 1566 immediately) 1567 1568 1569 1570 This corresponds to the Reorder opcodes: 1571 1572 'FWDCUR' and 'FWD BUF' 1573 1574 1575 1576 <legal all> 1577 */ 1578 #define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000060 1579 #define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_LSB 0 1580 #define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff 1581 1582 /* Description RX_REO_QUEUE_24_BAR_RECEIVED_COUNT 1583 1584 The number of times a BAR frame is received. 1585 1586 1587 1588 This corresponds to the Reorder opcodes with 'DROP' 1589 1590 1591 1592 The counter saturates and freezes at 0xFF 1593 1594 <legal all> 1595 */ 1596 #define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_OFFSET 0x00000060 1597 #define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_LSB 24 1598 #define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_MASK 0xff000000 1599 1600 /* Description RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT 1601 1602 The total number of MPDU frames that have been processed 1603 by REO. 'Processing' here means that REO has received them 1604 out of the entrance ring, and retrieved the corresponding 1605 RX_REO_QUEUE Descriptor. 1606 1607 1608 1609 Note that this count includes duplicates, frames that 1610 later had errors, etc. 1611 1612 1613 1614 Note that field 'Duplicate_count' indicates how many of 1615 these MPDUs were duplicates. 1616 1617 1618 1619 <legal all> 1620 */ 1621 #define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000064 1622 #define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 1623 #define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff 1624 1625 /* Description RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT 1626 1627 The total number of MSDU frames that have been processed 1628 by REO. 'Processing' here means that REO has received them 1629 out of the entrance ring, and retrieved the corresponding 1630 RX_REO_QUEUE Descriptor. 1631 1632 1633 1634 Note that this count includes duplicates, frames that 1635 later had errors, etc. 1636 1637 1638 1639 <legal all> 1640 */ 1641 #define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000068 1642 #define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 1643 #define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff 1644 1645 /* Description RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT 1646 1647 An approximation of the number of bytes processed for 1648 this queue. 1649 1650 'Processing' here means that REO has received them out 1651 of the entrance ring, and retrieved the corresponding 1652 RX_REO_QUEUE Descriptor. 1653 1654 1655 1656 Note that this count includes duplicates, frames that 1657 later had errors, etc. 1658 1659 1660 1661 In 64 byte units 1662 1663 <legal all> 1664 */ 1665 #define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x0000006c 1666 #define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 1667 #define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff 1668 1669 /* Description RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT 1670 1671 The number of MPDUs received after the window had 1672 already moved on. The 'late' sequence window is defined as 1673 (Window SSN - 256) - (Window SSN - 1) 1674 1675 1676 1677 This corresponds with Out of order detection in 1678 duplicate detect FSM 1679 1680 1681 1682 The counter saturates and freezes at 0xFFF 1683 1684 1685 1686 <legal all> 1687 */ 1688 #define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000070 1689 #define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_LSB 0 1690 #define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff 1691 1692 /* Description RX_REO_QUEUE_28_WINDOW_JUMP_2K 1693 1694 The number of times the window moved more then 2K 1695 1696 1697 1698 The counter saturates and freezes at 0xF 1699 1700 1701 1702 (Note: field name can not start with number: previous 1703 2k_window_jump) 1704 1705 1706 1707 <legal all> 1708 */ 1709 #define RX_REO_QUEUE_28_WINDOW_JUMP_2K_OFFSET 0x00000070 1710 #define RX_REO_QUEUE_28_WINDOW_JUMP_2K_LSB 12 1711 #define RX_REO_QUEUE_28_WINDOW_JUMP_2K_MASK 0x0000f000 1712 1713 /* Description RX_REO_QUEUE_28_HOLE_COUNT 1714 1715 The number of times a hole was created in the receive 1716 bitmap. 1717 1718 1719 1720 This corresponds to the Reorder opcodes with 'QCUR' 1721 1722 1723 1724 <legal all> 1725 */ 1726 #define RX_REO_QUEUE_28_HOLE_COUNT_OFFSET 0x00000070 1727 #define RX_REO_QUEUE_28_HOLE_COUNT_LSB 16 1728 #define RX_REO_QUEUE_28_HOLE_COUNT_MASK 0xffff0000 1729 1730 /* Description RX_REO_QUEUE_29_RESERVED_29 1731 1732 <legal 0> 1733 */ 1734 #define RX_REO_QUEUE_29_RESERVED_29_OFFSET 0x00000074 1735 #define RX_REO_QUEUE_29_RESERVED_29_LSB 0 1736 #define RX_REO_QUEUE_29_RESERVED_29_MASK 0xffffffff 1737 1738 /* Description RX_REO_QUEUE_30_RESERVED_30 1739 1740 <legal 0> 1741 */ 1742 #define RX_REO_QUEUE_30_RESERVED_30_OFFSET 0x00000078 1743 #define RX_REO_QUEUE_30_RESERVED_30_LSB 0 1744 #define RX_REO_QUEUE_30_RESERVED_30_MASK 0xffffffff 1745 1746 /* Description RX_REO_QUEUE_31_RESERVED_31 1747 1748 <legal 0> 1749 */ 1750 #define RX_REO_QUEUE_31_RESERVED_31_OFFSET 0x0000007c 1751 #define RX_REO_QUEUE_31_RESERVED_31_LSB 0 1752 #define RX_REO_QUEUE_31_RESERVED_31_MASK 0xffffffff 1753 1754 1755 #endif // _RX_REO_QUEUE_H_ 1756