1 /* 2 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 // $ATH_LICENSE_HW_HDR_C$ 18 // 19 // DO NOT EDIT! This file is automatically generated 20 // These definitions are tied to a particular hardware layout 21 22 23 #ifndef _RX_REO_QUEUE_EXT_H_ 24 #define _RX_REO_QUEUE_EXT_H_ 25 #if !defined(__ASSEMBLER__) 26 #endif 27 28 #include "uniform_descriptor_header.h" 29 #include "rx_mpdu_link_ptr.h" 30 31 // ################ START SUMMARY ################# 32 // 33 // Dword Fields 34 // 0 struct uniform_descriptor_header descriptor_header; 35 // 1 reserved_1a[31:0] 36 // 2-3 struct rx_mpdu_link_ptr mpdu_link_pointer_0; 37 // 4-5 struct rx_mpdu_link_ptr mpdu_link_pointer_1; 38 // 6-7 struct rx_mpdu_link_ptr mpdu_link_pointer_2; 39 // 8-9 struct rx_mpdu_link_ptr mpdu_link_pointer_3; 40 // 10-11 struct rx_mpdu_link_ptr mpdu_link_pointer_4; 41 // 12-13 struct rx_mpdu_link_ptr mpdu_link_pointer_5; 42 // 14-15 struct rx_mpdu_link_ptr mpdu_link_pointer_6; 43 // 16-17 struct rx_mpdu_link_ptr mpdu_link_pointer_7; 44 // 18-19 struct rx_mpdu_link_ptr mpdu_link_pointer_8; 45 // 20-21 struct rx_mpdu_link_ptr mpdu_link_pointer_9; 46 // 22-23 struct rx_mpdu_link_ptr mpdu_link_pointer_10; 47 // 24-25 struct rx_mpdu_link_ptr mpdu_link_pointer_11; 48 // 26-27 struct rx_mpdu_link_ptr mpdu_link_pointer_12; 49 // 28-29 struct rx_mpdu_link_ptr mpdu_link_pointer_13; 50 // 30-31 struct rx_mpdu_link_ptr mpdu_link_pointer_14; 51 // 52 // ################ END SUMMARY ################# 53 54 #define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32 55 56 struct rx_reo_queue_ext { 57 struct uniform_descriptor_header descriptor_header; 58 uint32_t reserved_1a : 32; //[31:0] 59 struct rx_mpdu_link_ptr mpdu_link_pointer_0; 60 struct rx_mpdu_link_ptr mpdu_link_pointer_1; 61 struct rx_mpdu_link_ptr mpdu_link_pointer_2; 62 struct rx_mpdu_link_ptr mpdu_link_pointer_3; 63 struct rx_mpdu_link_ptr mpdu_link_pointer_4; 64 struct rx_mpdu_link_ptr mpdu_link_pointer_5; 65 struct rx_mpdu_link_ptr mpdu_link_pointer_6; 66 struct rx_mpdu_link_ptr mpdu_link_pointer_7; 67 struct rx_mpdu_link_ptr mpdu_link_pointer_8; 68 struct rx_mpdu_link_ptr mpdu_link_pointer_9; 69 struct rx_mpdu_link_ptr mpdu_link_pointer_10; 70 struct rx_mpdu_link_ptr mpdu_link_pointer_11; 71 struct rx_mpdu_link_ptr mpdu_link_pointer_12; 72 struct rx_mpdu_link_ptr mpdu_link_pointer_13; 73 struct rx_mpdu_link_ptr mpdu_link_pointer_14; 74 }; 75 76 /* 77 78 struct uniform_descriptor_header descriptor_header 79 80 Details about which module owns this struct. 81 82 Note that sub field Buffer_type shall be set to 83 Receive_REO_queue_ext_descriptor 84 85 reserved_1a 86 87 <legal 0> 88 89 struct rx_mpdu_link_ptr mpdu_link_pointer_0 90 91 Consumer: REO 92 93 Producer: REO 94 95 96 97 Pointer to the next MPDU_link descriptor in the MPDU 98 queue 99 100 struct rx_mpdu_link_ptr mpdu_link_pointer_1 101 102 Consumer: REO 103 104 Producer: REO 105 106 107 108 Pointer to the next MPDU_link descriptor in the MPDU 109 queue 110 111 struct rx_mpdu_link_ptr mpdu_link_pointer_2 112 113 Consumer: REO 114 115 Producer: REO 116 117 118 119 Pointer to the next MPDU_link descriptor in the MPDU 120 queue 121 122 struct rx_mpdu_link_ptr mpdu_link_pointer_3 123 124 Consumer: REO 125 126 Producer: REO 127 128 129 130 Pointer to the next MPDU_link descriptor in the MPDU 131 queue 132 133 struct rx_mpdu_link_ptr mpdu_link_pointer_4 134 135 Consumer: REO 136 137 Producer: REO 138 139 140 141 Pointer to the next MPDU_link descriptor in the MPDU 142 queue 143 144 struct rx_mpdu_link_ptr mpdu_link_pointer_5 145 146 Consumer: REO 147 148 Producer: REO 149 150 151 152 Pointer to the next MPDU_link descriptor in the MPDU 153 queue 154 155 struct rx_mpdu_link_ptr mpdu_link_pointer_6 156 157 Consumer: REO 158 159 Producer: REO 160 161 162 163 Pointer to the next MPDU_link descriptor in the MPDU 164 queue 165 166 struct rx_mpdu_link_ptr mpdu_link_pointer_7 167 168 Consumer: REO 169 170 Producer: REO 171 172 173 174 Pointer to the next MPDU_link descriptor in the MPDU 175 queue 176 177 struct rx_mpdu_link_ptr mpdu_link_pointer_8 178 179 Consumer: REO 180 181 Producer: REO 182 183 184 185 Pointer to the next MPDU_link descriptor in the MPDU 186 queue 187 188 struct rx_mpdu_link_ptr mpdu_link_pointer_9 189 190 Consumer: REO 191 192 Producer: REO 193 194 195 196 Pointer to the next MPDU_link descriptor in the MPDU 197 queue 198 199 struct rx_mpdu_link_ptr mpdu_link_pointer_10 200 201 Consumer: REO 202 203 Producer: REO 204 205 206 207 Pointer to the next MPDU_link descriptor in the MPDU 208 queue 209 210 struct rx_mpdu_link_ptr mpdu_link_pointer_11 211 212 Consumer: REO 213 214 Producer: REO 215 216 217 218 Pointer to the next MPDU_link descriptor in the MPDU 219 queue 220 221 struct rx_mpdu_link_ptr mpdu_link_pointer_12 222 223 Consumer: REO 224 225 Producer: REO 226 227 228 229 Pointer to the next MPDU_link descriptor in the MPDU 230 queue 231 232 struct rx_mpdu_link_ptr mpdu_link_pointer_13 233 234 Consumer: REO 235 236 Producer: REO 237 238 239 240 Pointer to the next MPDU_link descriptor in the MPDU 241 queue 242 243 struct rx_mpdu_link_ptr mpdu_link_pointer_14 244 245 Consumer: REO 246 247 Producer: REO 248 249 250 251 Pointer to the next MPDU_link descriptor in the MPDU 252 queue 253 */ 254 255 256 /* EXTERNAL REFERENCE : struct uniform_descriptor_header descriptor_header */ 257 258 259 /* Description RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER 260 261 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 262 263 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 264 265 266 267 The owner of this data structure: 268 269 <enum 0 WBM_owned> Buffer Manager currently owns this 270 data structure. 271 272 <enum 1 SW_OR_FW_owned> Software of FW currently owns 273 this data structure. 274 275 <enum 2 TQM_owned> Transmit Queue Manager currently owns 276 this data structure. 277 278 <enum 3 RXDMA_owned> Receive DMA currently owns this 279 data structure. 280 281 <enum 4 REO_owned> Reorder currently owns this data 282 structure. 283 284 <enum 5 SWITCH_owned> SWITCH currently owns this data 285 structure. 286 287 288 289 <legal 0-5> 290 */ 291 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 292 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_LSB 0 293 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 294 295 /* Description RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE 296 297 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 298 299 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 300 301 302 303 Field describing what contents format is of this 304 descriptor 305 306 307 308 <enum 0 Transmit_MSDU_Link_descriptor > 309 310 <enum 1 Transmit_MPDU_Link_descriptor > 311 312 <enum 2 Transmit_MPDU_Queue_head_descriptor> 313 314 <enum 3 Transmit_MPDU_Queue_ext_descriptor> 315 316 <enum 4 Transmit_flow_descriptor> 317 318 <enum 5 Transmit_buffer > NOT TO BE USED: 319 320 321 322 <enum 6 Receive_MSDU_Link_descriptor > 323 324 <enum 7 Receive_MPDU_Link_descriptor > 325 326 <enum 8 Receive_REO_queue_descriptor > 327 328 <enum 9 Receive_REO_queue_ext_descriptor > 329 330 331 332 <enum 10 Receive_buffer > 333 334 335 336 <enum 11 Idle_link_list_entry> 337 338 339 340 <legal 0-11> 341 */ 342 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 343 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 344 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 345 346 /* Description RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A 347 348 <legal 0> 349 */ 350 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 351 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 352 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 353 354 /* Description RX_REO_QUEUE_EXT_1_RESERVED_1A 355 356 <legal 0> 357 */ 358 #define RX_REO_QUEUE_EXT_1_RESERVED_1A_OFFSET 0x00000004 359 #define RX_REO_QUEUE_EXT_1_RESERVED_1A_LSB 0 360 #define RX_REO_QUEUE_EXT_1_RESERVED_1A_MASK 0xffffffff 361 362 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_0 */ 363 364 365 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 366 367 368 /* Description RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 369 370 Address (lower 32 bits) of the MSDU buffer OR 371 MSDU_EXTENSION descriptor OR Link Descriptor 372 373 374 375 In case of 'NULL' pointer, this field is set to 0 376 377 <legal all> 378 */ 379 #define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000008 380 #define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 381 #define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 382 383 /* Description RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 384 385 Address (upper 8 bits) of the MSDU buffer OR 386 MSDU_EXTENSION descriptor OR Link Descriptor 387 388 389 390 In case of 'NULL' pointer, this field is set to 0 391 392 <legal all> 393 */ 394 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000000c 395 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 396 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 397 398 /* Description RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 399 400 Consumer: WBM 401 402 Producer: SW/FW 403 404 405 406 In case of 'NULL' pointer, this field is set to 0 407 408 409 410 Indicates to which buffer manager the buffer OR 411 MSDU_EXTENSION descriptor OR link descriptor that is being 412 pointed to shall be returned after the frame has been 413 processed. It is used by WBM for routing purposes. 414 415 416 417 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 418 to the WMB buffer idle list 419 420 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 421 returned to the WMB idle link descriptor idle list 422 423 <enum 2 FW_BM> This buffer shall be returned to the FW 424 425 <enum 3 SW0_BM> This buffer shall be returned to the SW, 426 ring 0 427 428 <enum 4 SW1_BM> This buffer shall be returned to the SW, 429 ring 1 430 431 <enum 5 SW2_BM> This buffer shall be returned to the SW, 432 ring 2 433 434 <enum 6 SW3_BM> This buffer shall be returned to the SW, 435 ring 3 436 437 <enum 7 SW4_BM> This buffer shall be returned to the SW, 438 ring 3 439 440 441 442 <legal all> 443 */ 444 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000000c 445 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 446 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 447 448 /* Description RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 449 450 Cookie field exclusively used by SW. 451 452 453 454 In case of 'NULL' pointer, this field is set to 0 455 456 457 458 HW ignores the contents, accept that it passes the 459 programmed value on to other descriptors together with the 460 physical address 461 462 463 464 Field can be used by SW to for example associate the 465 buffers physical address with the virtual address 466 467 The bit definitions as used by SW are within SW HLD 468 specification 469 470 471 472 NOTE: 473 474 The three most significant bits can have a special 475 meaning in case this struct is embedded in a TX_MPDU_DETAILS 476 STRUCT, and field transmit_bw_restriction is set 477 478 479 480 In case of NON punctured transmission: 481 482 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 483 484 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 485 486 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 487 488 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 489 490 491 492 In case of punctured transmission: 493 494 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 495 496 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 497 498 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 499 500 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 501 502 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 503 504 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 505 506 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 507 508 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 509 510 511 512 Note: a punctured transmission is indicated by the 513 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 514 TLV 515 516 517 518 <legal all> 519 */ 520 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000000c 521 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 522 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 523 524 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_1 */ 525 526 527 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 528 529 530 /* Description RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 531 532 Address (lower 32 bits) of the MSDU buffer OR 533 MSDU_EXTENSION descriptor OR Link Descriptor 534 535 536 537 In case of 'NULL' pointer, this field is set to 0 538 539 <legal all> 540 */ 541 #define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010 542 #define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 543 #define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 544 545 /* Description RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 546 547 Address (upper 8 bits) of the MSDU buffer OR 548 MSDU_EXTENSION descriptor OR Link Descriptor 549 550 551 552 In case of 'NULL' pointer, this field is set to 0 553 554 <legal all> 555 */ 556 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014 557 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 558 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 559 560 /* Description RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 561 562 Consumer: WBM 563 564 Producer: SW/FW 565 566 567 568 In case of 'NULL' pointer, this field is set to 0 569 570 571 572 Indicates to which buffer manager the buffer OR 573 MSDU_EXTENSION descriptor OR link descriptor that is being 574 pointed to shall be returned after the frame has been 575 processed. It is used by WBM for routing purposes. 576 577 578 579 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 580 to the WMB buffer idle list 581 582 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 583 returned to the WMB idle link descriptor idle list 584 585 <enum 2 FW_BM> This buffer shall be returned to the FW 586 587 <enum 3 SW0_BM> This buffer shall be returned to the SW, 588 ring 0 589 590 <enum 4 SW1_BM> This buffer shall be returned to the SW, 591 ring 1 592 593 <enum 5 SW2_BM> This buffer shall be returned to the SW, 594 ring 2 595 596 <enum 6 SW3_BM> This buffer shall be returned to the SW, 597 ring 3 598 599 <enum 7 SW4_BM> This buffer shall be returned to the SW, 600 ring 3 601 602 603 604 <legal all> 605 */ 606 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 607 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 608 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 609 610 /* Description RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 611 612 Cookie field exclusively used by SW. 613 614 615 616 In case of 'NULL' pointer, this field is set to 0 617 618 619 620 HW ignores the contents, accept that it passes the 621 programmed value on to other descriptors together with the 622 physical address 623 624 625 626 Field can be used by SW to for example associate the 627 buffers physical address with the virtual address 628 629 The bit definitions as used by SW are within SW HLD 630 specification 631 632 633 634 NOTE: 635 636 The three most significant bits can have a special 637 meaning in case this struct is embedded in a TX_MPDU_DETAILS 638 STRUCT, and field transmit_bw_restriction is set 639 640 641 642 In case of NON punctured transmission: 643 644 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 645 646 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 647 648 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 649 650 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 651 652 653 654 In case of punctured transmission: 655 656 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 657 658 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 659 660 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 661 662 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 663 664 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 665 666 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 667 668 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 669 670 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 671 672 673 674 Note: a punctured transmission is indicated by the 675 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 676 TLV 677 678 679 680 <legal all> 681 */ 682 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014 683 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 684 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 685 686 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_2 */ 687 688 689 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 690 691 692 /* Description RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 693 694 Address (lower 32 bits) of the MSDU buffer OR 695 MSDU_EXTENSION descriptor OR Link Descriptor 696 697 698 699 In case of 'NULL' pointer, this field is set to 0 700 701 <legal all> 702 */ 703 #define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000018 704 #define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 705 #define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 706 707 /* Description RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 708 709 Address (upper 8 bits) of the MSDU buffer OR 710 MSDU_EXTENSION descriptor OR Link Descriptor 711 712 713 714 In case of 'NULL' pointer, this field is set to 0 715 716 <legal all> 717 */ 718 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000001c 719 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 720 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 721 722 /* Description RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 723 724 Consumer: WBM 725 726 Producer: SW/FW 727 728 729 730 In case of 'NULL' pointer, this field is set to 0 731 732 733 734 Indicates to which buffer manager the buffer OR 735 MSDU_EXTENSION descriptor OR link descriptor that is being 736 pointed to shall be returned after the frame has been 737 processed. It is used by WBM for routing purposes. 738 739 740 741 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 742 to the WMB buffer idle list 743 744 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 745 returned to the WMB idle link descriptor idle list 746 747 <enum 2 FW_BM> This buffer shall be returned to the FW 748 749 <enum 3 SW0_BM> This buffer shall be returned to the SW, 750 ring 0 751 752 <enum 4 SW1_BM> This buffer shall be returned to the SW, 753 ring 1 754 755 <enum 5 SW2_BM> This buffer shall be returned to the SW, 756 ring 2 757 758 <enum 6 SW3_BM> This buffer shall be returned to the SW, 759 ring 3 760 761 <enum 7 SW4_BM> This buffer shall be returned to the SW, 762 ring 3 763 764 765 766 <legal all> 767 */ 768 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000001c 769 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 770 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 771 772 /* Description RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 773 774 Cookie field exclusively used by SW. 775 776 777 778 In case of 'NULL' pointer, this field is set to 0 779 780 781 782 HW ignores the contents, accept that it passes the 783 programmed value on to other descriptors together with the 784 physical address 785 786 787 788 Field can be used by SW to for example associate the 789 buffers physical address with the virtual address 790 791 The bit definitions as used by SW are within SW HLD 792 specification 793 794 795 796 NOTE: 797 798 The three most significant bits can have a special 799 meaning in case this struct is embedded in a TX_MPDU_DETAILS 800 STRUCT, and field transmit_bw_restriction is set 801 802 803 804 In case of NON punctured transmission: 805 806 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 807 808 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 809 810 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 811 812 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 813 814 815 816 In case of punctured transmission: 817 818 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 819 820 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 821 822 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 823 824 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 825 826 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 827 828 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 829 830 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 831 832 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 833 834 835 836 Note: a punctured transmission is indicated by the 837 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 838 TLV 839 840 841 842 <legal all> 843 */ 844 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000001c 845 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 846 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 847 848 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_3 */ 849 850 851 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 852 853 854 /* Description RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 855 856 Address (lower 32 bits) of the MSDU buffer OR 857 MSDU_EXTENSION descriptor OR Link Descriptor 858 859 860 861 In case of 'NULL' pointer, this field is set to 0 862 863 <legal all> 864 */ 865 #define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000020 866 #define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 867 #define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 868 869 /* Description RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 870 871 Address (upper 8 bits) of the MSDU buffer OR 872 MSDU_EXTENSION descriptor OR Link Descriptor 873 874 875 876 In case of 'NULL' pointer, this field is set to 0 877 878 <legal all> 879 */ 880 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000024 881 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 882 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 883 884 /* Description RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 885 886 Consumer: WBM 887 888 Producer: SW/FW 889 890 891 892 In case of 'NULL' pointer, this field is set to 0 893 894 895 896 Indicates to which buffer manager the buffer OR 897 MSDU_EXTENSION descriptor OR link descriptor that is being 898 pointed to shall be returned after the frame has been 899 processed. It is used by WBM for routing purposes. 900 901 902 903 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 904 to the WMB buffer idle list 905 906 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 907 returned to the WMB idle link descriptor idle list 908 909 <enum 2 FW_BM> This buffer shall be returned to the FW 910 911 <enum 3 SW0_BM> This buffer shall be returned to the SW, 912 ring 0 913 914 <enum 4 SW1_BM> This buffer shall be returned to the SW, 915 ring 1 916 917 <enum 5 SW2_BM> This buffer shall be returned to the SW, 918 ring 2 919 920 <enum 6 SW3_BM> This buffer shall be returned to the SW, 921 ring 3 922 923 <enum 7 SW4_BM> This buffer shall be returned to the SW, 924 ring 3 925 926 927 928 <legal all> 929 */ 930 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 931 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 932 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 933 934 /* Description RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 935 936 Cookie field exclusively used by SW. 937 938 939 940 In case of 'NULL' pointer, this field is set to 0 941 942 943 944 HW ignores the contents, accept that it passes the 945 programmed value on to other descriptors together with the 946 physical address 947 948 949 950 Field can be used by SW to for example associate the 951 buffers physical address with the virtual address 952 953 The bit definitions as used by SW are within SW HLD 954 specification 955 956 957 958 NOTE: 959 960 The three most significant bits can have a special 961 meaning in case this struct is embedded in a TX_MPDU_DETAILS 962 STRUCT, and field transmit_bw_restriction is set 963 964 965 966 In case of NON punctured transmission: 967 968 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 969 970 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 971 972 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 973 974 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 975 976 977 978 In case of punctured transmission: 979 980 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 981 982 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 983 984 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 985 986 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 987 988 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 989 990 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 991 992 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 993 994 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 995 996 997 998 Note: a punctured transmission is indicated by the 999 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1000 TLV 1001 1002 1003 1004 <legal all> 1005 */ 1006 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000024 1007 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 1008 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 1009 1010 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_4 */ 1011 1012 1013 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 1014 1015 1016 /* Description RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 1017 1018 Address (lower 32 bits) of the MSDU buffer OR 1019 MSDU_EXTENSION descriptor OR Link Descriptor 1020 1021 1022 1023 In case of 'NULL' pointer, this field is set to 0 1024 1025 <legal all> 1026 */ 1027 #define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000028 1028 #define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1029 #define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1030 1031 /* Description RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 1032 1033 Address (upper 8 bits) of the MSDU buffer OR 1034 MSDU_EXTENSION descriptor OR Link Descriptor 1035 1036 1037 1038 In case of 'NULL' pointer, this field is set to 0 1039 1040 <legal all> 1041 */ 1042 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000002c 1043 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1044 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1045 1046 /* Description RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 1047 1048 Consumer: WBM 1049 1050 Producer: SW/FW 1051 1052 1053 1054 In case of 'NULL' pointer, this field is set to 0 1055 1056 1057 1058 Indicates to which buffer manager the buffer OR 1059 MSDU_EXTENSION descriptor OR link descriptor that is being 1060 pointed to shall be returned after the frame has been 1061 processed. It is used by WBM for routing purposes. 1062 1063 1064 1065 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1066 to the WMB buffer idle list 1067 1068 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1069 returned to the WMB idle link descriptor idle list 1070 1071 <enum 2 FW_BM> This buffer shall be returned to the FW 1072 1073 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1074 ring 0 1075 1076 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1077 ring 1 1078 1079 <enum 5 SW2_BM> This buffer shall be returned to the SW, 1080 ring 2 1081 1082 <enum 6 SW3_BM> This buffer shall be returned to the SW, 1083 ring 3 1084 1085 <enum 7 SW4_BM> This buffer shall be returned to the SW, 1086 ring 3 1087 1088 1089 1090 <legal all> 1091 */ 1092 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000002c 1093 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1094 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 1095 1096 /* Description RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 1097 1098 Cookie field exclusively used by SW. 1099 1100 1101 1102 In case of 'NULL' pointer, this field is set to 0 1103 1104 1105 1106 HW ignores the contents, accept that it passes the 1107 programmed value on to other descriptors together with the 1108 physical address 1109 1110 1111 1112 Field can be used by SW to for example associate the 1113 buffers physical address with the virtual address 1114 1115 The bit definitions as used by SW are within SW HLD 1116 specification 1117 1118 1119 1120 NOTE: 1121 1122 The three most significant bits can have a special 1123 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1124 STRUCT, and field transmit_bw_restriction is set 1125 1126 1127 1128 In case of NON punctured transmission: 1129 1130 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1131 1132 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1133 1134 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1135 1136 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1137 1138 1139 1140 In case of punctured transmission: 1141 1142 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1143 1144 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1145 1146 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1147 1148 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1149 1150 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1151 1152 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1153 1154 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1155 1156 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1157 1158 1159 1160 Note: a punctured transmission is indicated by the 1161 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1162 TLV 1163 1164 1165 1166 <legal all> 1167 */ 1168 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000002c 1169 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 1170 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 1171 1172 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_5 */ 1173 1174 1175 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 1176 1177 1178 /* Description RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 1179 1180 Address (lower 32 bits) of the MSDU buffer OR 1181 MSDU_EXTENSION descriptor OR Link Descriptor 1182 1183 1184 1185 In case of 'NULL' pointer, this field is set to 0 1186 1187 <legal all> 1188 */ 1189 #define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000030 1190 #define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1191 #define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1192 1193 /* Description RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 1194 1195 Address (upper 8 bits) of the MSDU buffer OR 1196 MSDU_EXTENSION descriptor OR Link Descriptor 1197 1198 1199 1200 In case of 'NULL' pointer, this field is set to 0 1201 1202 <legal all> 1203 */ 1204 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000034 1205 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1206 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1207 1208 /* Description RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 1209 1210 Consumer: WBM 1211 1212 Producer: SW/FW 1213 1214 1215 1216 In case of 'NULL' pointer, this field is set to 0 1217 1218 1219 1220 Indicates to which buffer manager the buffer OR 1221 MSDU_EXTENSION descriptor OR link descriptor that is being 1222 pointed to shall be returned after the frame has been 1223 processed. It is used by WBM for routing purposes. 1224 1225 1226 1227 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1228 to the WMB buffer idle list 1229 1230 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1231 returned to the WMB idle link descriptor idle list 1232 1233 <enum 2 FW_BM> This buffer shall be returned to the FW 1234 1235 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1236 ring 0 1237 1238 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1239 ring 1 1240 1241 <enum 5 SW2_BM> This buffer shall be returned to the SW, 1242 ring 2 1243 1244 <enum 6 SW3_BM> This buffer shall be returned to the SW, 1245 ring 3 1246 1247 <enum 7 SW4_BM> This buffer shall be returned to the SW, 1248 ring 3 1249 1250 1251 1252 <legal all> 1253 */ 1254 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 1255 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1256 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 1257 1258 /* Description RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 1259 1260 Cookie field exclusively used by SW. 1261 1262 1263 1264 In case of 'NULL' pointer, this field is set to 0 1265 1266 1267 1268 HW ignores the contents, accept that it passes the 1269 programmed value on to other descriptors together with the 1270 physical address 1271 1272 1273 1274 Field can be used by SW to for example associate the 1275 buffers physical address with the virtual address 1276 1277 The bit definitions as used by SW are within SW HLD 1278 specification 1279 1280 1281 1282 NOTE: 1283 1284 The three most significant bits can have a special 1285 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1286 STRUCT, and field transmit_bw_restriction is set 1287 1288 1289 1290 In case of NON punctured transmission: 1291 1292 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1293 1294 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1295 1296 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1297 1298 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1299 1300 1301 1302 In case of punctured transmission: 1303 1304 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1305 1306 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1307 1308 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1309 1310 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1311 1312 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1313 1314 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1315 1316 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1317 1318 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1319 1320 1321 1322 Note: a punctured transmission is indicated by the 1323 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1324 TLV 1325 1326 1327 1328 <legal all> 1329 */ 1330 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000034 1331 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 1332 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 1333 1334 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_6 */ 1335 1336 1337 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 1338 1339 1340 /* Description RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 1341 1342 Address (lower 32 bits) of the MSDU buffer OR 1343 MSDU_EXTENSION descriptor OR Link Descriptor 1344 1345 1346 1347 In case of 'NULL' pointer, this field is set to 0 1348 1349 <legal all> 1350 */ 1351 #define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000038 1352 #define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1353 #define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1354 1355 /* Description RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 1356 1357 Address (upper 8 bits) of the MSDU buffer OR 1358 MSDU_EXTENSION descriptor OR Link Descriptor 1359 1360 1361 1362 In case of 'NULL' pointer, this field is set to 0 1363 1364 <legal all> 1365 */ 1366 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000003c 1367 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1368 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1369 1370 /* Description RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 1371 1372 Consumer: WBM 1373 1374 Producer: SW/FW 1375 1376 1377 1378 In case of 'NULL' pointer, this field is set to 0 1379 1380 1381 1382 Indicates to which buffer manager the buffer OR 1383 MSDU_EXTENSION descriptor OR link descriptor that is being 1384 pointed to shall be returned after the frame has been 1385 processed. It is used by WBM for routing purposes. 1386 1387 1388 1389 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1390 to the WMB buffer idle list 1391 1392 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1393 returned to the WMB idle link descriptor idle list 1394 1395 <enum 2 FW_BM> This buffer shall be returned to the FW 1396 1397 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1398 ring 0 1399 1400 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1401 ring 1 1402 1403 <enum 5 SW2_BM> This buffer shall be returned to the SW, 1404 ring 2 1405 1406 <enum 6 SW3_BM> This buffer shall be returned to the SW, 1407 ring 3 1408 1409 <enum 7 SW4_BM> This buffer shall be returned to the SW, 1410 ring 3 1411 1412 1413 1414 <legal all> 1415 */ 1416 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000003c 1417 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1418 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 1419 1420 /* Description RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 1421 1422 Cookie field exclusively used by SW. 1423 1424 1425 1426 In case of 'NULL' pointer, this field is set to 0 1427 1428 1429 1430 HW ignores the contents, accept that it passes the 1431 programmed value on to other descriptors together with the 1432 physical address 1433 1434 1435 1436 Field can be used by SW to for example associate the 1437 buffers physical address with the virtual address 1438 1439 The bit definitions as used by SW are within SW HLD 1440 specification 1441 1442 1443 1444 NOTE: 1445 1446 The three most significant bits can have a special 1447 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1448 STRUCT, and field transmit_bw_restriction is set 1449 1450 1451 1452 In case of NON punctured transmission: 1453 1454 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1455 1456 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1457 1458 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1459 1460 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1461 1462 1463 1464 In case of punctured transmission: 1465 1466 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1467 1468 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1469 1470 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1471 1472 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1473 1474 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1475 1476 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1477 1478 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1479 1480 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1481 1482 1483 1484 Note: a punctured transmission is indicated by the 1485 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1486 TLV 1487 1488 1489 1490 <legal all> 1491 */ 1492 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000003c 1493 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 1494 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 1495 1496 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_7 */ 1497 1498 1499 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 1500 1501 1502 /* Description RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 1503 1504 Address (lower 32 bits) of the MSDU buffer OR 1505 MSDU_EXTENSION descriptor OR Link Descriptor 1506 1507 1508 1509 In case of 'NULL' pointer, this field is set to 0 1510 1511 <legal all> 1512 */ 1513 #define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000040 1514 #define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1515 #define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1516 1517 /* Description RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 1518 1519 Address (upper 8 bits) of the MSDU buffer OR 1520 MSDU_EXTENSION descriptor OR Link Descriptor 1521 1522 1523 1524 In case of 'NULL' pointer, this field is set to 0 1525 1526 <legal all> 1527 */ 1528 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000044 1529 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1530 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1531 1532 /* Description RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 1533 1534 Consumer: WBM 1535 1536 Producer: SW/FW 1537 1538 1539 1540 In case of 'NULL' pointer, this field is set to 0 1541 1542 1543 1544 Indicates to which buffer manager the buffer OR 1545 MSDU_EXTENSION descriptor OR link descriptor that is being 1546 pointed to shall be returned after the frame has been 1547 processed. It is used by WBM for routing purposes. 1548 1549 1550 1551 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1552 to the WMB buffer idle list 1553 1554 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1555 returned to the WMB idle link descriptor idle list 1556 1557 <enum 2 FW_BM> This buffer shall be returned to the FW 1558 1559 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1560 ring 0 1561 1562 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1563 ring 1 1564 1565 <enum 5 SW2_BM> This buffer shall be returned to the SW, 1566 ring 2 1567 1568 <enum 6 SW3_BM> This buffer shall be returned to the SW, 1569 ring 3 1570 1571 <enum 7 SW4_BM> This buffer shall be returned to the SW, 1572 ring 3 1573 1574 1575 1576 <legal all> 1577 */ 1578 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 1579 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1580 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 1581 1582 /* Description RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 1583 1584 Cookie field exclusively used by SW. 1585 1586 1587 1588 In case of 'NULL' pointer, this field is set to 0 1589 1590 1591 1592 HW ignores the contents, accept that it passes the 1593 programmed value on to other descriptors together with the 1594 physical address 1595 1596 1597 1598 Field can be used by SW to for example associate the 1599 buffers physical address with the virtual address 1600 1601 The bit definitions as used by SW are within SW HLD 1602 specification 1603 1604 1605 1606 NOTE: 1607 1608 The three most significant bits can have a special 1609 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1610 STRUCT, and field transmit_bw_restriction is set 1611 1612 1613 1614 In case of NON punctured transmission: 1615 1616 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1617 1618 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1619 1620 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1621 1622 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1623 1624 1625 1626 In case of punctured transmission: 1627 1628 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1629 1630 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1631 1632 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1633 1634 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1635 1636 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1637 1638 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1639 1640 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1641 1642 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1643 1644 1645 1646 Note: a punctured transmission is indicated by the 1647 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1648 TLV 1649 1650 1651 1652 <legal all> 1653 */ 1654 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000044 1655 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 1656 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 1657 1658 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_8 */ 1659 1660 1661 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 1662 1663 1664 /* Description RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 1665 1666 Address (lower 32 bits) of the MSDU buffer OR 1667 MSDU_EXTENSION descriptor OR Link Descriptor 1668 1669 1670 1671 In case of 'NULL' pointer, this field is set to 0 1672 1673 <legal all> 1674 */ 1675 #define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000048 1676 #define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1677 #define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1678 1679 /* Description RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 1680 1681 Address (upper 8 bits) of the MSDU buffer OR 1682 MSDU_EXTENSION descriptor OR Link Descriptor 1683 1684 1685 1686 In case of 'NULL' pointer, this field is set to 0 1687 1688 <legal all> 1689 */ 1690 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000004c 1691 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1692 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1693 1694 /* Description RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 1695 1696 Consumer: WBM 1697 1698 Producer: SW/FW 1699 1700 1701 1702 In case of 'NULL' pointer, this field is set to 0 1703 1704 1705 1706 Indicates to which buffer manager the buffer OR 1707 MSDU_EXTENSION descriptor OR link descriptor that is being 1708 pointed to shall be returned after the frame has been 1709 processed. It is used by WBM for routing purposes. 1710 1711 1712 1713 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1714 to the WMB buffer idle list 1715 1716 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1717 returned to the WMB idle link descriptor idle list 1718 1719 <enum 2 FW_BM> This buffer shall be returned to the FW 1720 1721 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1722 ring 0 1723 1724 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1725 ring 1 1726 1727 <enum 5 SW2_BM> This buffer shall be returned to the SW, 1728 ring 2 1729 1730 <enum 6 SW3_BM> This buffer shall be returned to the SW, 1731 ring 3 1732 1733 <enum 7 SW4_BM> This buffer shall be returned to the SW, 1734 ring 3 1735 1736 1737 1738 <legal all> 1739 */ 1740 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000004c 1741 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1742 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 1743 1744 /* Description RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 1745 1746 Cookie field exclusively used by SW. 1747 1748 1749 1750 In case of 'NULL' pointer, this field is set to 0 1751 1752 1753 1754 HW ignores the contents, accept that it passes the 1755 programmed value on to other descriptors together with the 1756 physical address 1757 1758 1759 1760 Field can be used by SW to for example associate the 1761 buffers physical address with the virtual address 1762 1763 The bit definitions as used by SW are within SW HLD 1764 specification 1765 1766 1767 1768 NOTE: 1769 1770 The three most significant bits can have a special 1771 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1772 STRUCT, and field transmit_bw_restriction is set 1773 1774 1775 1776 In case of NON punctured transmission: 1777 1778 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1779 1780 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1781 1782 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1783 1784 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1785 1786 1787 1788 In case of punctured transmission: 1789 1790 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1791 1792 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1793 1794 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1795 1796 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1797 1798 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1799 1800 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1801 1802 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1803 1804 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1805 1806 1807 1808 Note: a punctured transmission is indicated by the 1809 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1810 TLV 1811 1812 1813 1814 <legal all> 1815 */ 1816 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000004c 1817 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 1818 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 1819 1820 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_9 */ 1821 1822 1823 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 1824 1825 1826 /* Description RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 1827 1828 Address (lower 32 bits) of the MSDU buffer OR 1829 MSDU_EXTENSION descriptor OR Link Descriptor 1830 1831 1832 1833 In case of 'NULL' pointer, this field is set to 0 1834 1835 <legal all> 1836 */ 1837 #define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000050 1838 #define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1839 #define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1840 1841 /* Description RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 1842 1843 Address (upper 8 bits) of the MSDU buffer OR 1844 MSDU_EXTENSION descriptor OR Link Descriptor 1845 1846 1847 1848 In case of 'NULL' pointer, this field is set to 0 1849 1850 <legal all> 1851 */ 1852 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000054 1853 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1854 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1855 1856 /* Description RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 1857 1858 Consumer: WBM 1859 1860 Producer: SW/FW 1861 1862 1863 1864 In case of 'NULL' pointer, this field is set to 0 1865 1866 1867 1868 Indicates to which buffer manager the buffer OR 1869 MSDU_EXTENSION descriptor OR link descriptor that is being 1870 pointed to shall be returned after the frame has been 1871 processed. It is used by WBM for routing purposes. 1872 1873 1874 1875 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1876 to the WMB buffer idle list 1877 1878 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1879 returned to the WMB idle link descriptor idle list 1880 1881 <enum 2 FW_BM> This buffer shall be returned to the FW 1882 1883 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1884 ring 0 1885 1886 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1887 ring 1 1888 1889 <enum 5 SW2_BM> This buffer shall be returned to the SW, 1890 ring 2 1891 1892 <enum 6 SW3_BM> This buffer shall be returned to the SW, 1893 ring 3 1894 1895 <enum 7 SW4_BM> This buffer shall be returned to the SW, 1896 ring 3 1897 1898 1899 1900 <legal all> 1901 */ 1902 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 1903 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1904 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 1905 1906 /* Description RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 1907 1908 Cookie field exclusively used by SW. 1909 1910 1911 1912 In case of 'NULL' pointer, this field is set to 0 1913 1914 1915 1916 HW ignores the contents, accept that it passes the 1917 programmed value on to other descriptors together with the 1918 physical address 1919 1920 1921 1922 Field can be used by SW to for example associate the 1923 buffers physical address with the virtual address 1924 1925 The bit definitions as used by SW are within SW HLD 1926 specification 1927 1928 1929 1930 NOTE: 1931 1932 The three most significant bits can have a special 1933 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1934 STRUCT, and field transmit_bw_restriction is set 1935 1936 1937 1938 In case of NON punctured transmission: 1939 1940 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1941 1942 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1943 1944 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1945 1946 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1947 1948 1949 1950 In case of punctured transmission: 1951 1952 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1953 1954 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1955 1956 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1957 1958 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1959 1960 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1961 1962 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1963 1964 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1965 1966 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1967 1968 1969 1970 Note: a punctured transmission is indicated by the 1971 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1972 TLV 1973 1974 1975 1976 <legal all> 1977 */ 1978 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000054 1979 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 1980 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 1981 1982 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_10 */ 1983 1984 1985 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 1986 1987 1988 /* Description RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 1989 1990 Address (lower 32 bits) of the MSDU buffer OR 1991 MSDU_EXTENSION descriptor OR Link Descriptor 1992 1993 1994 1995 In case of 'NULL' pointer, this field is set to 0 1996 1997 <legal all> 1998 */ 1999 #define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000058 2000 #define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2001 #define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2002 2003 /* Description RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 2004 2005 Address (upper 8 bits) of the MSDU buffer OR 2006 MSDU_EXTENSION descriptor OR Link Descriptor 2007 2008 2009 2010 In case of 'NULL' pointer, this field is set to 0 2011 2012 <legal all> 2013 */ 2014 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000005c 2015 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2016 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2017 2018 /* Description RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 2019 2020 Consumer: WBM 2021 2022 Producer: SW/FW 2023 2024 2025 2026 In case of 'NULL' pointer, this field is set to 0 2027 2028 2029 2030 Indicates to which buffer manager the buffer OR 2031 MSDU_EXTENSION descriptor OR link descriptor that is being 2032 pointed to shall be returned after the frame has been 2033 processed. It is used by WBM for routing purposes. 2034 2035 2036 2037 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2038 to the WMB buffer idle list 2039 2040 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 2041 returned to the WMB idle link descriptor idle list 2042 2043 <enum 2 FW_BM> This buffer shall be returned to the FW 2044 2045 <enum 3 SW0_BM> This buffer shall be returned to the SW, 2046 ring 0 2047 2048 <enum 4 SW1_BM> This buffer shall be returned to the SW, 2049 ring 1 2050 2051 <enum 5 SW2_BM> This buffer shall be returned to the SW, 2052 ring 2 2053 2054 <enum 6 SW3_BM> This buffer shall be returned to the SW, 2055 ring 3 2056 2057 <enum 7 SW4_BM> This buffer shall be returned to the SW, 2058 ring 3 2059 2060 2061 2062 <legal all> 2063 */ 2064 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000005c 2065 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2066 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 2067 2068 /* Description RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 2069 2070 Cookie field exclusively used by SW. 2071 2072 2073 2074 In case of 'NULL' pointer, this field is set to 0 2075 2076 2077 2078 HW ignores the contents, accept that it passes the 2079 programmed value on to other descriptors together with the 2080 physical address 2081 2082 2083 2084 Field can be used by SW to for example associate the 2085 buffers physical address with the virtual address 2086 2087 The bit definitions as used by SW are within SW HLD 2088 specification 2089 2090 2091 2092 NOTE: 2093 2094 The three most significant bits can have a special 2095 meaning in case this struct is embedded in a TX_MPDU_DETAILS 2096 STRUCT, and field transmit_bw_restriction is set 2097 2098 2099 2100 In case of NON punctured transmission: 2101 2102 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 2103 2104 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 2105 2106 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 2107 2108 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 2109 2110 2111 2112 In case of punctured transmission: 2113 2114 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 2115 2116 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 2117 2118 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 2119 2120 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 2121 2122 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 2123 2124 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 2125 2126 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 2127 2128 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 2129 2130 2131 2132 Note: a punctured transmission is indicated by the 2133 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 2134 TLV 2135 2136 2137 2138 <legal all> 2139 */ 2140 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000005c 2141 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 2142 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 2143 2144 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_11 */ 2145 2146 2147 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 2148 2149 2150 /* Description RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 2151 2152 Address (lower 32 bits) of the MSDU buffer OR 2153 MSDU_EXTENSION descriptor OR Link Descriptor 2154 2155 2156 2157 In case of 'NULL' pointer, this field is set to 0 2158 2159 <legal all> 2160 */ 2161 #define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000060 2162 #define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2163 #define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2164 2165 /* Description RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 2166 2167 Address (upper 8 bits) of the MSDU buffer OR 2168 MSDU_EXTENSION descriptor OR Link Descriptor 2169 2170 2171 2172 In case of 'NULL' pointer, this field is set to 0 2173 2174 <legal all> 2175 */ 2176 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000064 2177 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2178 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2179 2180 /* Description RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 2181 2182 Consumer: WBM 2183 2184 Producer: SW/FW 2185 2186 2187 2188 In case of 'NULL' pointer, this field is set to 0 2189 2190 2191 2192 Indicates to which buffer manager the buffer OR 2193 MSDU_EXTENSION descriptor OR link descriptor that is being 2194 pointed to shall be returned after the frame has been 2195 processed. It is used by WBM for routing purposes. 2196 2197 2198 2199 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2200 to the WMB buffer idle list 2201 2202 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 2203 returned to the WMB idle link descriptor idle list 2204 2205 <enum 2 FW_BM> This buffer shall be returned to the FW 2206 2207 <enum 3 SW0_BM> This buffer shall be returned to the SW, 2208 ring 0 2209 2210 <enum 4 SW1_BM> This buffer shall be returned to the SW, 2211 ring 1 2212 2213 <enum 5 SW2_BM> This buffer shall be returned to the SW, 2214 ring 2 2215 2216 <enum 6 SW3_BM> This buffer shall be returned to the SW, 2217 ring 3 2218 2219 <enum 7 SW4_BM> This buffer shall be returned to the SW, 2220 ring 3 2221 2222 2223 2224 <legal all> 2225 */ 2226 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 2227 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2228 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 2229 2230 /* Description RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 2231 2232 Cookie field exclusively used by SW. 2233 2234 2235 2236 In case of 'NULL' pointer, this field is set to 0 2237 2238 2239 2240 HW ignores the contents, accept that it passes the 2241 programmed value on to other descriptors together with the 2242 physical address 2243 2244 2245 2246 Field can be used by SW to for example associate the 2247 buffers physical address with the virtual address 2248 2249 The bit definitions as used by SW are within SW HLD 2250 specification 2251 2252 2253 2254 NOTE: 2255 2256 The three most significant bits can have a special 2257 meaning in case this struct is embedded in a TX_MPDU_DETAILS 2258 STRUCT, and field transmit_bw_restriction is set 2259 2260 2261 2262 In case of NON punctured transmission: 2263 2264 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 2265 2266 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 2267 2268 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 2269 2270 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 2271 2272 2273 2274 In case of punctured transmission: 2275 2276 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 2277 2278 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 2279 2280 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 2281 2282 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 2283 2284 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 2285 2286 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 2287 2288 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 2289 2290 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 2291 2292 2293 2294 Note: a punctured transmission is indicated by the 2295 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 2296 TLV 2297 2298 2299 2300 <legal all> 2301 */ 2302 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000064 2303 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 2304 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 2305 2306 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_12 */ 2307 2308 2309 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 2310 2311 2312 /* Description RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 2313 2314 Address (lower 32 bits) of the MSDU buffer OR 2315 MSDU_EXTENSION descriptor OR Link Descriptor 2316 2317 2318 2319 In case of 'NULL' pointer, this field is set to 0 2320 2321 <legal all> 2322 */ 2323 #define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000068 2324 #define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2325 #define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2326 2327 /* Description RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 2328 2329 Address (upper 8 bits) of the MSDU buffer OR 2330 MSDU_EXTENSION descriptor OR Link Descriptor 2331 2332 2333 2334 In case of 'NULL' pointer, this field is set to 0 2335 2336 <legal all> 2337 */ 2338 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000006c 2339 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2340 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2341 2342 /* Description RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 2343 2344 Consumer: WBM 2345 2346 Producer: SW/FW 2347 2348 2349 2350 In case of 'NULL' pointer, this field is set to 0 2351 2352 2353 2354 Indicates to which buffer manager the buffer OR 2355 MSDU_EXTENSION descriptor OR link descriptor that is being 2356 pointed to shall be returned after the frame has been 2357 processed. It is used by WBM for routing purposes. 2358 2359 2360 2361 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2362 to the WMB buffer idle list 2363 2364 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 2365 returned to the WMB idle link descriptor idle list 2366 2367 <enum 2 FW_BM> This buffer shall be returned to the FW 2368 2369 <enum 3 SW0_BM> This buffer shall be returned to the SW, 2370 ring 0 2371 2372 <enum 4 SW1_BM> This buffer shall be returned to the SW, 2373 ring 1 2374 2375 <enum 5 SW2_BM> This buffer shall be returned to the SW, 2376 ring 2 2377 2378 <enum 6 SW3_BM> This buffer shall be returned to the SW, 2379 ring 3 2380 2381 <enum 7 SW4_BM> This buffer shall be returned to the SW, 2382 ring 3 2383 2384 2385 2386 <legal all> 2387 */ 2388 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000006c 2389 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2390 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 2391 2392 /* Description RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 2393 2394 Cookie field exclusively used by SW. 2395 2396 2397 2398 In case of 'NULL' pointer, this field is set to 0 2399 2400 2401 2402 HW ignores the contents, accept that it passes the 2403 programmed value on to other descriptors together with the 2404 physical address 2405 2406 2407 2408 Field can be used by SW to for example associate the 2409 buffers physical address with the virtual address 2410 2411 The bit definitions as used by SW are within SW HLD 2412 specification 2413 2414 2415 2416 NOTE: 2417 2418 The three most significant bits can have a special 2419 meaning in case this struct is embedded in a TX_MPDU_DETAILS 2420 STRUCT, and field transmit_bw_restriction is set 2421 2422 2423 2424 In case of NON punctured transmission: 2425 2426 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 2427 2428 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 2429 2430 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 2431 2432 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 2433 2434 2435 2436 In case of punctured transmission: 2437 2438 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 2439 2440 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 2441 2442 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 2443 2444 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 2445 2446 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 2447 2448 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 2449 2450 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 2451 2452 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 2453 2454 2455 2456 Note: a punctured transmission is indicated by the 2457 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 2458 TLV 2459 2460 2461 2462 <legal all> 2463 */ 2464 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000006c 2465 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 2466 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 2467 2468 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_13 */ 2469 2470 2471 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 2472 2473 2474 /* Description RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 2475 2476 Address (lower 32 bits) of the MSDU buffer OR 2477 MSDU_EXTENSION descriptor OR Link Descriptor 2478 2479 2480 2481 In case of 'NULL' pointer, this field is set to 0 2482 2483 <legal all> 2484 */ 2485 #define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000070 2486 #define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2487 #define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2488 2489 /* Description RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 2490 2491 Address (upper 8 bits) of the MSDU buffer OR 2492 MSDU_EXTENSION descriptor OR Link Descriptor 2493 2494 2495 2496 In case of 'NULL' pointer, this field is set to 0 2497 2498 <legal all> 2499 */ 2500 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000074 2501 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2502 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2503 2504 /* Description RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 2505 2506 Consumer: WBM 2507 2508 Producer: SW/FW 2509 2510 2511 2512 In case of 'NULL' pointer, this field is set to 0 2513 2514 2515 2516 Indicates to which buffer manager the buffer OR 2517 MSDU_EXTENSION descriptor OR link descriptor that is being 2518 pointed to shall be returned after the frame has been 2519 processed. It is used by WBM for routing purposes. 2520 2521 2522 2523 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2524 to the WMB buffer idle list 2525 2526 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 2527 returned to the WMB idle link descriptor idle list 2528 2529 <enum 2 FW_BM> This buffer shall be returned to the FW 2530 2531 <enum 3 SW0_BM> This buffer shall be returned to the SW, 2532 ring 0 2533 2534 <enum 4 SW1_BM> This buffer shall be returned to the SW, 2535 ring 1 2536 2537 <enum 5 SW2_BM> This buffer shall be returned to the SW, 2538 ring 2 2539 2540 <enum 6 SW3_BM> This buffer shall be returned to the SW, 2541 ring 3 2542 2543 <enum 7 SW4_BM> This buffer shall be returned to the SW, 2544 ring 3 2545 2546 2547 2548 <legal all> 2549 */ 2550 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 2551 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2552 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 2553 2554 /* Description RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 2555 2556 Cookie field exclusively used by SW. 2557 2558 2559 2560 In case of 'NULL' pointer, this field is set to 0 2561 2562 2563 2564 HW ignores the contents, accept that it passes the 2565 programmed value on to other descriptors together with the 2566 physical address 2567 2568 2569 2570 Field can be used by SW to for example associate the 2571 buffers physical address with the virtual address 2572 2573 The bit definitions as used by SW are within SW HLD 2574 specification 2575 2576 2577 2578 NOTE: 2579 2580 The three most significant bits can have a special 2581 meaning in case this struct is embedded in a TX_MPDU_DETAILS 2582 STRUCT, and field transmit_bw_restriction is set 2583 2584 2585 2586 In case of NON punctured transmission: 2587 2588 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 2589 2590 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 2591 2592 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 2593 2594 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 2595 2596 2597 2598 In case of punctured transmission: 2599 2600 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 2601 2602 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 2603 2604 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 2605 2606 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 2607 2608 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 2609 2610 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 2611 2612 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 2613 2614 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 2615 2616 2617 2618 Note: a punctured transmission is indicated by the 2619 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 2620 TLV 2621 2622 2623 2624 <legal all> 2625 */ 2626 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000074 2627 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 2628 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 2629 2630 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_14 */ 2631 2632 2633 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 2634 2635 2636 /* Description RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 2637 2638 Address (lower 32 bits) of the MSDU buffer OR 2639 MSDU_EXTENSION descriptor OR Link Descriptor 2640 2641 2642 2643 In case of 'NULL' pointer, this field is set to 0 2644 2645 <legal all> 2646 */ 2647 #define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000078 2648 #define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2649 #define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2650 2651 /* Description RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 2652 2653 Address (upper 8 bits) of the MSDU buffer OR 2654 MSDU_EXTENSION descriptor OR Link Descriptor 2655 2656 2657 2658 In case of 'NULL' pointer, this field is set to 0 2659 2660 <legal all> 2661 */ 2662 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000007c 2663 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2664 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2665 2666 /* Description RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 2667 2668 Consumer: WBM 2669 2670 Producer: SW/FW 2671 2672 2673 2674 In case of 'NULL' pointer, this field is set to 0 2675 2676 2677 2678 Indicates to which buffer manager the buffer OR 2679 MSDU_EXTENSION descriptor OR link descriptor that is being 2680 pointed to shall be returned after the frame has been 2681 processed. It is used by WBM for routing purposes. 2682 2683 2684 2685 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2686 to the WMB buffer idle list 2687 2688 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 2689 returned to the WMB idle link descriptor idle list 2690 2691 <enum 2 FW_BM> This buffer shall be returned to the FW 2692 2693 <enum 3 SW0_BM> This buffer shall be returned to the SW, 2694 ring 0 2695 2696 <enum 4 SW1_BM> This buffer shall be returned to the SW, 2697 ring 1 2698 2699 <enum 5 SW2_BM> This buffer shall be returned to the SW, 2700 ring 2 2701 2702 <enum 6 SW3_BM> This buffer shall be returned to the SW, 2703 ring 3 2704 2705 <enum 7 SW4_BM> This buffer shall be returned to the SW, 2706 ring 3 2707 2708 2709 2710 <legal all> 2711 */ 2712 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000007c 2713 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2714 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 2715 2716 /* Description RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 2717 2718 Cookie field exclusively used by SW. 2719 2720 2721 2722 In case of 'NULL' pointer, this field is set to 0 2723 2724 2725 2726 HW ignores the contents, accept that it passes the 2727 programmed value on to other descriptors together with the 2728 physical address 2729 2730 2731 2732 Field can be used by SW to for example associate the 2733 buffers physical address with the virtual address 2734 2735 The bit definitions as used by SW are within SW HLD 2736 specification 2737 2738 2739 2740 NOTE: 2741 2742 The three most significant bits can have a special 2743 meaning in case this struct is embedded in a TX_MPDU_DETAILS 2744 STRUCT, and field transmit_bw_restriction is set 2745 2746 2747 2748 In case of NON punctured transmission: 2749 2750 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 2751 2752 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 2753 2754 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 2755 2756 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 2757 2758 2759 2760 In case of punctured transmission: 2761 2762 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 2763 2764 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 2765 2766 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 2767 2768 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 2769 2770 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 2771 2772 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 2773 2774 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 2775 2776 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 2777 2778 2779 2780 Note: a punctured transmission is indicated by the 2781 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 2782 TLV 2783 2784 2785 2786 <legal all> 2787 */ 2788 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000007c 2789 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 2790 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 2791 2792 2793 #endif // _RX_REO_QUEUE_EXT_H_ 2794