1 /* 2 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 // $ATH_LICENSE_HW_HDR_C$ 18 // 19 // DO NOT EDIT! This file is automatically generated 20 // These definitions are tied to a particular hardware layout 21 22 23 #ifndef _RXPCU_PPDU_END_INFO_H_ 24 #define _RXPCU_PPDU_END_INFO_H_ 25 #if !defined(__ASSEMBLER__) 26 #endif 27 28 #include "phyrx_abort_request_info.h" 29 #include "macrx_abort_request_info.h" 30 31 // ################ START SUMMARY ################# 32 // 33 // Dword Fields 34 // 0 wb_timestamp_lower_32[31:0] 35 // 1 wb_timestamp_upper_32[31:0] 36 // 2 rx_antenna[23:0], tx_ht_vht_ack[24], unsupported_mu_nc[25], otp_txbf_disable[26], previous_tlv_corrupted[27], phyrx_abort_request_info_valid[28], macrx_abort_request_info_valid[29], reserved[31:30] 37 // 3 coex_bt_tx_from_start_of_rx[0], coex_bt_tx_after_start_of_rx[1], coex_wan_tx_from_start_of_rx[2], coex_wan_tx_after_start_of_rx[3], coex_wlan_tx_from_start_of_rx[4], coex_wlan_tx_after_start_of_rx[5], mpdu_delimiter_errors_seen[6], ftm_tm[8:7], dialog_token[16:9], follow_up_dialog_token[24:17], bb_captured_channel[25], reserved_3[31:26] 38 // 4 before_mpdu_count_passing_fcs[9:0], before_mpdu_count_failing_fcs[19:10], after_mpdu_count_passing_fcs[29:20], reserved_4[31:30] 39 // 5 after_mpdu_count_failing_fcs[9:0], reserved_5[31:10] 40 // 6 phy_timestamp_tx_lower_32[31:0] 41 // 7 phy_timestamp_tx_upper_32[31:0] 42 // 8 bb_length[15:0], bb_data[16], reserved_8[19:17], first_bt_broadcast_status_details[31:20] 43 // 9 rx_ppdu_duration[23:0], reserved_9[31:24] 44 // 10 ast_index[15:0], ast_index_valid[16], reserved_10[19:17], second_bt_broadcast_status_details[31:20] 45 // 11 struct phyrx_abort_request_info phyrx_abort_request_info_details; 46 // 12 struct macrx_abort_request_info macrx_abort_request_info_details; 47 // 13 rx_ppdu_end_marker[31:0] 48 // 49 // ################ END SUMMARY ################# 50 51 #define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 14 52 53 struct rxpcu_ppdu_end_info { 54 uint32_t wb_timestamp_lower_32 : 32; //[31:0] 55 uint32_t wb_timestamp_upper_32 : 32; //[31:0] 56 uint32_t rx_antenna : 24, //[23:0] 57 tx_ht_vht_ack : 1, //[24] 58 unsupported_mu_nc : 1, //[25] 59 otp_txbf_disable : 1, //[26] 60 previous_tlv_corrupted : 1, //[27] 61 phyrx_abort_request_info_valid : 1, //[28] 62 macrx_abort_request_info_valid : 1, //[29] 63 reserved : 2; //[31:30] 64 uint32_t coex_bt_tx_from_start_of_rx : 1, //[0] 65 coex_bt_tx_after_start_of_rx : 1, //[1] 66 coex_wan_tx_from_start_of_rx : 1, //[2] 67 coex_wan_tx_after_start_of_rx : 1, //[3] 68 coex_wlan_tx_from_start_of_rx : 1, //[4] 69 coex_wlan_tx_after_start_of_rx : 1, //[5] 70 mpdu_delimiter_errors_seen : 1, //[6] 71 ftm_tm : 2, //[8:7] 72 dialog_token : 8, //[16:9] 73 follow_up_dialog_token : 8, //[24:17] 74 bb_captured_channel : 1, //[25] 75 reserved_3 : 6; //[31:26] 76 uint32_t before_mpdu_count_passing_fcs : 10, //[9:0] 77 before_mpdu_count_failing_fcs : 10, //[19:10] 78 after_mpdu_count_passing_fcs : 10, //[29:20] 79 reserved_4 : 2; //[31:30] 80 uint32_t after_mpdu_count_failing_fcs : 10, //[9:0] 81 reserved_5 : 22; //[31:10] 82 uint32_t phy_timestamp_tx_lower_32 : 32; //[31:0] 83 uint32_t phy_timestamp_tx_upper_32 : 32; //[31:0] 84 uint32_t bb_length : 16, //[15:0] 85 bb_data : 1, //[16] 86 reserved_8 : 3, //[19:17] 87 first_bt_broadcast_status_details: 12; //[31:20] 88 uint32_t rx_ppdu_duration : 24, //[23:0] 89 reserved_9 : 8; //[31:24] 90 uint32_t ast_index : 16, //[15:0] 91 ast_index_valid : 1, //[16] 92 reserved_10 : 3, //[19:17] 93 second_bt_broadcast_status_details: 12; //[31:20] 94 struct phyrx_abort_request_info phyrx_abort_request_info_details; 95 struct macrx_abort_request_info macrx_abort_request_info_details; 96 uint16_t pre_bt_broadcast_status_details : 12, //[27:16] 97 reserved_12a : 4; //[31:28] 98 uint32_t rx_ppdu_end_marker : 32; //[31:0] 99 }; 100 101 /* 102 103 wb_timestamp_lower_32 104 105 WLAN/BT timestamp is a 1 usec resolution timestamp which 106 does not get updated based on receive beacon like TSF. The 107 same rules for capturing tsf_timestamp are used to capture 108 the wb_timestamp. This field represents the lower 32 bits of 109 the 64-bit timestamp 110 111 wb_timestamp_upper_32 112 113 WLAN/BT timestamp is a 1 usec resolution timestamp which 114 does not get updated based on receive beacon like TSF. The 115 same rules for capturing tsf_timestamp are used to capture 116 the wb_timestamp. This field represents the upper 32 bits of 117 the 64-bit timestamp 118 119 rx_antenna 120 121 Receive antenna value ??? 122 123 tx_ht_vht_ack 124 125 Indicates that a HT or VHT Ack/BA frame was transmitted 126 in response to this receive packet. 127 128 unsupported_mu_nc 129 130 Set if MU Nc > 2 in received NDPA. 131 132 If this bit is set, even though AID and BSSID are 133 matched, MAC doesn't send tx_expect_ndp to PHY, because MU 134 Nc > 2 is not supported in Helium. 135 136 otp_txbf_disable 137 138 Set if either OTP_SUBFEE_DISABLE or OTP_TXBF_DISABLE is 139 set and if RXPU receives directed NDPA frame. Then, RXPCU 140 should not send TX_EXPECT_NDP TLV to SW but set this bit to 141 inform SW. 142 143 previous_tlv_corrupted 144 145 When set, the TLV preceding this RXPCU_END_INFO TLV 146 within the RX_PPDU_END TLV, is corrupted. Not the entire TLV 147 was received.... Likely due to an abort scenario... If abort 148 is to blame, see the abort data datastructure for details. 149 150 <legal all> 151 152 phyrx_abort_request_info_valid 153 154 When set, the PHY sent an PHYRX_ABORT_REQUEST TLV to 155 RXPCU. The abort fields embedded in this TLV contain valid 156 info. 157 158 <legal all> 159 160 macrx_abort_request_info_valid 161 162 When set, the MAC sent an MACRX_ABORT_REQUEST TLV to 163 PHYRX. The abort fields embedded in this TLV contain valid 164 info. 165 166 <legal all> 167 168 reserved 169 170 <legal 0> 171 172 coex_bt_tx_from_start_of_rx 173 174 Set when BT TX was ongoing when WLAN RX started 175 176 coex_bt_tx_after_start_of_rx 177 178 179 coex_wan_tx_from_start_of_rx 180 181 Set when WAN TX was ongoing when WLAN RX started 182 183 coex_wan_tx_after_start_of_rx 184 185 Set when WAN TX started while WLAN RX was already 186 ongoing 187 188 coex_wlan_tx_from_start_of_rx 189 190 Set when other WLAN TX was ongoing when WLAN RX started 191 192 coex_wlan_tx_after_start_of_rx 193 194 Set when other WLAN TX started while WLAN RX was already 195 ongoing 196 197 mpdu_delimiter_errors_seen 198 199 When set, MPDU delimiter errors have been detected 200 during this PPDU reception 201 202 ftm_tm 203 204 Indicate the timestamp is for the FTM or TM frame 205 206 207 208 0: non TM or FTM frame 209 210 1: FTM frame 211 212 2: TM frame 213 214 3: reserved 215 216 <legal all> 217 218 dialog_token 219 220 The dialog token in the FTM or TM frame. Only valid when 221 the FTM is set. Clear to 254 for a non-FTM frame 222 223 <legal all> 224 225 follow_up_dialog_token 226 227 The follow up dialog token in the FTM or TM frame. Only 228 valid when the FTM is set. Clear to 0 for a non-FTM frame, 229 The follow up dialog token in the FTM frame. Only valid when 230 the FTM is set. Clear to 255 for a non-FTM frame<legal all> 231 232 bb_captured_channel 233 234 Set by RXPCU when the following conditions are met: 235 236 237 238 Directed (=> unicast) TM or FTM frame has been received 239 with passing FCS 240 241 PHYRX_PKT_END. Location_info_valid is set 242 243 244 245 <legal all> 246 247 reserved_3 248 249 <legal 0> 250 251 before_mpdu_count_passing_fcs 252 253 Number of MPDUs received in this PPDU that passed the 254 FCS check before the Coex TX started 255 256 257 258 The counter saturates at 0x3FF. 259 260 <legal all> 261 262 before_mpdu_count_failing_fcs 263 264 Number of MPDUs received in this PPDU that failed the 265 FCS check before the Coex TX started 266 267 268 269 The counter saturates at 0x3FF. 270 271 <legal all> 272 273 after_mpdu_count_passing_fcs 274 275 Number of MPDUs received in this PPDU that passed the 276 FCS check after the moment the Coex TX started 277 278 279 280 (Note: The partially received MPDU when the COEX tx 281 start event came in falls in the after category) 282 283 284 285 The counter saturates at 0x3FF. 286 287 <legal all> 288 289 reserved_4 290 291 <legal 0> 292 293 after_mpdu_count_failing_fcs 294 295 Number of MPDUs received in this PPDU that failed the 296 FCS check after the moment the Coex TX started 297 298 299 300 (Note: The partially received MPDU when the COEX tx 301 start event came in falls in the after category) 302 303 304 305 The counter saturates at 0x3FF. 306 307 <legal all> 308 309 reserved_5 310 311 <legal 0> 312 313 phy_timestamp_tx_lower_32 314 315 The PHY timestamp in the AMPI of the most recent rising 316 edge (TODO: of what ???) after the TX_PHY_DESC. This field 317 indicates the lower 32 bits of the timestamp 318 319 phy_timestamp_tx_upper_32 320 321 The PHY timestamp in the AMPI of the most recent rising 322 edge (TODO: of what ???) after the TX_PHY_DESC. This field 323 indicates the upper 32 bits of the timestamp 324 325 bb_length 326 327 Indicates the number of bytes of baseband information 328 for PPDUs where the BB descriptor preamble type is 0x80 to 329 0xFF which indicates that this is not a normal PPDU but 330 rather contains baseband debug information. 331 332 TODO: Is this still needed ??? 333 334 bb_data 335 336 Indicates that BB data associated with this PPDU will 337 exist in the receive buffer. The exact contents of this BB 338 data can be found by decoding the BB TLV in the buffer 339 associated with the BB data. See vector_fragment in the 340 Helium_mac_phy_interface.docx 341 342 reserved_8 343 344 Reserved: HW should fill with 0, FW should ignore. 345 346 first_bt_broadcast_status_details 347 348 Same contents as field bt_broadcast_status_details for 349 the first received COEX_STATUS_BROADCAST tlv during this 350 PPDU reception. 351 352 353 354 If no COEX_STATUS_BROADCAST tlv is received during this 355 PPDU reception, this field will be set to 0 356 357 358 359 360 361 For detailed info see doc: TBD 362 363 <legal all> 364 365 rx_ppdu_duration 366 367 The length of this PPDU reception in us 368 369 reserved_9 370 371 <legal 0> 372 373 ast_index 374 375 The AST index of the receive Ack/BA. This information 376 is provided from the TXPCU to the RXPCU for receive Ack/BA 377 for implicit beamforming. 378 379 <legal all> 380 381 ast_index_valid 382 383 Indicates that ast_index is valid. Should only be set 384 for receive Ack/BA where single stream implicit sounding is 385 captured. 386 387 reserved_10 388 389 <legal 0> 390 391 second_bt_broadcast_status_details 392 393 Same contents as field bt_broadcast_status_details for 394 the second received COEX_STATUS_BROADCAST tlv during this 395 PPDU reception. 396 397 398 399 If no second COEX_STATUS_BROADCAST tlv is received 400 during this PPDU reception, this field will be set to 0 401 402 403 404 405 406 For detailed info see doc: TBD 407 408 <legal all> 409 410 struct phyrx_abort_request_info phyrx_abort_request_info_details 411 412 Field only valid when Phyrx_abort_request_info_valid is 413 set 414 415 The reason why PHY generated an abort request 416 417 struct macrx_abort_request_info macrx_abort_request_info_details 418 419 Field only valid when macrx_abort_request_info_valid is 420 set 421 422 The reason why MACRX generated an abort request 423 424 rx_ppdu_end_marker 425 426 Field used by SW to double check that their structure 427 alignment is in sync with what HW has done. 428 429 <legal 0xAABBCCDD> 430 */ 431 432 433 /* Description RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32 434 435 WLAN/BT timestamp is a 1 usec resolution timestamp which 436 does not get updated based on receive beacon like TSF. The 437 same rules for capturing tsf_timestamp are used to capture 438 the wb_timestamp. This field represents the lower 32 bits of 439 the 64-bit timestamp 440 */ 441 #define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_OFFSET 0x00000000 442 #define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_LSB 0 443 #define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_MASK 0xffffffff 444 445 /* Description RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32 446 447 WLAN/BT timestamp is a 1 usec resolution timestamp which 448 does not get updated based on receive beacon like TSF. The 449 same rules for capturing tsf_timestamp are used to capture 450 the wb_timestamp. This field represents the upper 32 bits of 451 the 64-bit timestamp 452 */ 453 #define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_OFFSET 0x00000004 454 #define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_LSB 0 455 #define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_MASK 0xffffffff 456 457 /* Description RXPCU_PPDU_END_INFO_2_RX_ANTENNA 458 459 Receive antenna value ??? 460 */ 461 #define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_OFFSET 0x00000008 462 #define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_LSB 0 463 #define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_MASK 0x00ffffff 464 465 /* Description RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK 466 467 Indicates that a HT or VHT Ack/BA frame was transmitted 468 in response to this receive packet. 469 */ 470 #define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_OFFSET 0x00000008 471 #define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_LSB 24 472 #define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_MASK 0x01000000 473 474 /* Description RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC 475 476 Set if MU Nc > 2 in received NDPA. 477 478 If this bit is set, even though AID and BSSID are 479 matched, MAC doesn't send tx_expect_ndp to PHY, because MU 480 Nc > 2 is not supported in Helium. 481 */ 482 #define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_OFFSET 0x00000008 483 #define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_LSB 25 484 #define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_MASK 0x02000000 485 486 /* Description RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE 487 488 Set if either OTP_SUBFEE_DISABLE or OTP_TXBF_DISABLE is 489 set and if RXPU receives directed NDPA frame. Then, RXPCU 490 should not send TX_EXPECT_NDP TLV to SW but set this bit to 491 inform SW. 492 */ 493 #define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_OFFSET 0x00000008 494 #define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_LSB 26 495 #define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_MASK 0x04000000 496 497 /* Description RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED 498 499 When set, the TLV preceding this RXPCU_END_INFO TLV 500 within the RX_PPDU_END TLV, is corrupted. Not the entire TLV 501 was received.... Likely due to an abort scenario... If abort 502 is to blame, see the abort data datastructure for details. 503 504 <legal all> 505 */ 506 #define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_OFFSET 0x00000008 507 #define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_LSB 27 508 #define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_MASK 0x08000000 509 510 /* Description RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID 511 512 When set, the PHY sent an PHYRX_ABORT_REQUEST TLV to 513 RXPCU. The abort fields embedded in this TLV contain valid 514 info. 515 516 <legal all> 517 */ 518 #define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000008 519 #define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_LSB 28 520 #define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_MASK 0x10000000 521 522 /* Description RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID 523 524 When set, the MAC sent an MACRX_ABORT_REQUEST TLV to 525 PHYRX. The abort fields embedded in this TLV contain valid 526 info. 527 528 <legal all> 529 */ 530 #define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000008 531 #define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_LSB 29 532 #define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_MASK 0x20000000 533 534 /* Description RXPCU_PPDU_END_INFO_2_RESERVED 535 536 <legal 0> 537 */ 538 #define RXPCU_PPDU_END_INFO_2_RESERVED_OFFSET 0x00000008 539 #define RXPCU_PPDU_END_INFO_2_RESERVED_LSB 30 540 #define RXPCU_PPDU_END_INFO_2_RESERVED_MASK 0xc0000000 541 542 /* Description RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX 543 544 Set when BT TX was ongoing when WLAN RX started 545 */ 546 #define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_OFFSET 0x0000000c 547 #define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_LSB 0 548 #define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_MASK 0x00000001 549 550 /* Description RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX 551 552 */ 553 #define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_OFFSET 0x0000000c 554 #define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_LSB 1 555 #define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_MASK 0x00000002 556 557 /* Description RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX 558 559 Set when WAN TX was ongoing when WLAN RX started 560 */ 561 #define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_OFFSET 0x0000000c 562 #define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_LSB 2 563 #define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_MASK 0x00000004 564 565 /* Description RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX 566 567 Set when WAN TX started while WLAN RX was already 568 ongoing 569 */ 570 #define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000c 571 #define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_LSB 3 572 #define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_MASK 0x00000008 573 574 /* Description RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX 575 576 Set when other WLAN TX was ongoing when WLAN RX started 577 */ 578 #define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET 0x0000000c 579 #define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_LSB 4 580 #define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_MASK 0x00000010 581 582 /* Description RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX 583 584 Set when other WLAN TX started while WLAN RX was already 585 ongoing 586 */ 587 #define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000c 588 #define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_LSB 5 589 #define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_MASK 0x00000020 590 591 /* Description RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN 592 593 When set, MPDU delimiter errors have been detected 594 during this PPDU reception 595 */ 596 #define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_OFFSET 0x0000000c 597 #define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_LSB 6 598 #define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_MASK 0x00000040 599 600 /* Description RXPCU_PPDU_END_INFO_3_FTM_TM 601 602 Indicate the timestamp is for the FTM or TM frame 603 604 605 606 0: non TM or FTM frame 607 608 1: FTM frame 609 610 2: TM frame 611 612 3: reserved 613 614 <legal all> 615 */ 616 #define RXPCU_PPDU_END_INFO_3_FTM_TM_OFFSET 0x0000000c 617 #define RXPCU_PPDU_END_INFO_3_FTM_TM_LSB 7 618 #define RXPCU_PPDU_END_INFO_3_FTM_TM_MASK 0x00000180 619 620 /* Description RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN 621 622 The dialog token in the FTM or TM frame. Only valid when 623 the FTM is set. Clear to 254 for a non-FTM frame 624 625 <legal all> 626 */ 627 #define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_OFFSET 0x0000000c 628 #define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_LSB 9 629 #define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_MASK 0x0001fe00 630 631 /* Description RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN 632 633 The follow up dialog token in the FTM or TM frame. Only 634 valid when the FTM is set. Clear to 0 for a non-FTM frame, 635 The follow up dialog token in the FTM frame. Only valid when 636 the FTM is set. Clear to 255 for a non-FTM frame<legal all> 637 */ 638 #define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_OFFSET 0x0000000c 639 #define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_LSB 17 640 #define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_MASK 0x01fe0000 641 642 /* Description RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL 643 644 Set by RXPCU when the following conditions are met: 645 646 647 648 Directed (=> unicast) TM or FTM frame has been received 649 with passing FCS 650 651 PHYRX_PKT_END. Location_info_valid is set 652 653 654 655 <legal all> 656 */ 657 #define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_OFFSET 0x0000000c 658 #define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_LSB 25 659 #define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_MASK 0x02000000 660 661 /* Description RXPCU_PPDU_END_INFO_3_RESERVED_3 662 663 <legal 0> 664 */ 665 #define RXPCU_PPDU_END_INFO_3_RESERVED_3_OFFSET 0x0000000c 666 #define RXPCU_PPDU_END_INFO_3_RESERVED_3_LSB 26 667 #define RXPCU_PPDU_END_INFO_3_RESERVED_3_MASK 0xfc000000 668 669 /* Description RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS 670 671 Number of MPDUs received in this PPDU that passed the 672 FCS check before the Coex TX started 673 674 675 676 The counter saturates at 0x3FF. 677 678 <legal all> 679 */ 680 #define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET 0x00000010 681 #define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_LSB 0 682 #define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_MASK 0x000003ff 683 684 /* Description RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS 685 686 Number of MPDUs received in this PPDU that failed the 687 FCS check before the Coex TX started 688 689 690 691 The counter saturates at 0x3FF. 692 693 <legal all> 694 */ 695 #define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET 0x00000010 696 #define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_LSB 10 697 #define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_MASK 0x000ffc00 698 699 /* Description RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS 700 701 Number of MPDUs received in this PPDU that passed the 702 FCS check after the moment the Coex TX started 703 704 705 706 (Note: The partially received MPDU when the COEX tx 707 start event came in falls in the after category) 708 709 710 711 The counter saturates at 0x3FF. 712 713 <legal all> 714 */ 715 #define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET 0x00000010 716 #define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_LSB 20 717 #define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_MASK 0x3ff00000 718 719 /* Description RXPCU_PPDU_END_INFO_4_RESERVED_4 720 721 <legal 0> 722 */ 723 #define RXPCU_PPDU_END_INFO_4_RESERVED_4_OFFSET 0x00000010 724 #define RXPCU_PPDU_END_INFO_4_RESERVED_4_LSB 30 725 #define RXPCU_PPDU_END_INFO_4_RESERVED_4_MASK 0xc0000000 726 727 /* Description RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS 728 729 Number of MPDUs received in this PPDU that failed the 730 FCS check after the moment the Coex TX started 731 732 733 734 (Note: The partially received MPDU when the COEX tx 735 start event came in falls in the after category) 736 737 738 739 The counter saturates at 0x3FF. 740 741 <legal all> 742 */ 743 #define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET 0x00000014 744 #define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_LSB 0 745 #define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_MASK 0x000003ff 746 747 /* Description RXPCU_PPDU_END_INFO_5_RESERVED_5 748 749 <legal 0> 750 */ 751 #define RXPCU_PPDU_END_INFO_5_RESERVED_5_OFFSET 0x00000014 752 #define RXPCU_PPDU_END_INFO_5_RESERVED_5_LSB 10 753 #define RXPCU_PPDU_END_INFO_5_RESERVED_5_MASK 0xfffffc00 754 755 /* Description RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32 756 757 The PHY timestamp in the AMPI of the most recent rising 758 edge (TODO: of what ???) after the TX_PHY_DESC. This field 759 indicates the lower 32 bits of the timestamp 760 */ 761 #define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_OFFSET 0x00000018 762 #define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_LSB 0 763 #define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_MASK 0xffffffff 764 765 /* Description RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32 766 767 The PHY timestamp in the AMPI of the most recent rising 768 edge (TODO: of what ???) after the TX_PHY_DESC. This field 769 indicates the upper 32 bits of the timestamp 770 */ 771 #define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_OFFSET 0x0000001c 772 #define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_LSB 0 773 #define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_MASK 0xffffffff 774 775 /* Description RXPCU_PPDU_END_INFO_8_BB_LENGTH 776 777 Indicates the number of bytes of baseband information 778 for PPDUs where the BB descriptor preamble type is 0x80 to 779 0xFF which indicates that this is not a normal PPDU but 780 rather contains baseband debug information. 781 782 TODO: Is this still needed ??? 783 */ 784 #define RXPCU_PPDU_END_INFO_8_BB_LENGTH_OFFSET 0x00000020 785 #define RXPCU_PPDU_END_INFO_8_BB_LENGTH_LSB 0 786 #define RXPCU_PPDU_END_INFO_8_BB_LENGTH_MASK 0x0000ffff 787 788 /* Description RXPCU_PPDU_END_INFO_8_BB_DATA 789 790 Indicates that BB data associated with this PPDU will 791 exist in the receive buffer. The exact contents of this BB 792 data can be found by decoding the BB TLV in the buffer 793 associated with the BB data. See vector_fragment in the 794 Helium_mac_phy_interface.docx 795 */ 796 #define RXPCU_PPDU_END_INFO_8_BB_DATA_OFFSET 0x00000020 797 #define RXPCU_PPDU_END_INFO_8_BB_DATA_LSB 16 798 #define RXPCU_PPDU_END_INFO_8_BB_DATA_MASK 0x00010000 799 800 /* Description RXPCU_PPDU_END_INFO_8_RESERVED_8 801 802 Reserved: HW should fill with 0, FW should ignore. 803 */ 804 #define RXPCU_PPDU_END_INFO_8_RESERVED_8_OFFSET 0x00000020 805 #define RXPCU_PPDU_END_INFO_8_RESERVED_8_LSB 17 806 #define RXPCU_PPDU_END_INFO_8_RESERVED_8_MASK 0x000e0000 807 808 /* Description RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS 809 810 Same contents as field bt_broadcast_status_details for 811 the first received COEX_STATUS_BROADCAST tlv during this 812 PPDU reception. 813 814 815 816 If no COEX_STATUS_BROADCAST tlv is received during this 817 PPDU reception, this field will be set to 0 818 819 820 821 822 823 For detailed info see doc: TBD 824 825 <legal all> 826 */ 827 #define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000020 828 #define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 20 829 #define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000 830 831 /* Description RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION 832 833 The length of this PPDU reception in us 834 */ 835 #define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 0x00000024 836 #define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 0 837 #define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 0x00ffffff 838 839 /* Description RXPCU_PPDU_END_INFO_9_RESERVED_9 840 841 <legal 0> 842 */ 843 #define RXPCU_PPDU_END_INFO_9_RESERVED_9_OFFSET 0x00000024 844 #define RXPCU_PPDU_END_INFO_9_RESERVED_9_LSB 24 845 #define RXPCU_PPDU_END_INFO_9_RESERVED_9_MASK 0xff000000 846 847 /* Description RXPCU_PPDU_END_INFO_10_AST_INDEX 848 849 The AST index of the receive Ack/BA. This information 850 is provided from the TXPCU to the RXPCU for receive Ack/BA 851 for implicit beamforming. 852 853 <legal all> 854 */ 855 #define RXPCU_PPDU_END_INFO_10_AST_INDEX_OFFSET 0x00000028 856 #define RXPCU_PPDU_END_INFO_10_AST_INDEX_LSB 0 857 #define RXPCU_PPDU_END_INFO_10_AST_INDEX_MASK 0x0000ffff 858 859 /* Description RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID 860 861 Indicates that ast_index is valid. Should only be set 862 for receive Ack/BA where single stream implicit sounding is 863 captured. 864 */ 865 #define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_OFFSET 0x00000028 866 #define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_LSB 16 867 #define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_MASK 0x00010000 868 869 /* Description RXPCU_PPDU_END_INFO_10_RESERVED_10 870 871 <legal 0> 872 */ 873 #define RXPCU_PPDU_END_INFO_10_RESERVED_10_OFFSET 0x00000028 874 #define RXPCU_PPDU_END_INFO_10_RESERVED_10_LSB 17 875 #define RXPCU_PPDU_END_INFO_10_RESERVED_10_MASK 0x000e0000 876 877 /* Description RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS 878 879 Same contents as field bt_broadcast_status_details for 880 the second received COEX_STATUS_BROADCAST tlv during this 881 PPDU reception. 882 883 884 885 If no second COEX_STATUS_BROADCAST tlv is received 886 during this PPDU reception, this field will be set to 0 887 888 889 890 891 892 For detailed info see doc: TBD 893 894 <legal all> 895 */ 896 #define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000028 897 #define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20 898 #define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000 899 900 /* EXTERNAL REFERENCE : struct phyrx_abort_request_info phyrx_abort_request_info_details */ 901 902 903 /* Description RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON 904 905 <enum 0 phyrx_err_phy_off> Reception aborted due to 906 receiving a PHY_OFF TLV 907 908 <enum 1 phyrx_err_synth_off> 909 910 <enum 2 phyrx_err_ofdma_timing> 911 912 <enum 3 phyrx_err_ofdma_signal_parity> 913 914 <enum 4 phyrx_err_ofdma_rate_illegal> 915 916 <enum 5 phyrx_err_ofdma_length_illegal> 917 918 <enum 6 phyrx_err_ofdma_restart> 919 920 <enum 7 phyrx_err_ofdma_service> 921 922 <enum 8 phyrx_err_ppdu_ofdma_power_drop> 923 924 925 926 <enum 9 phyrx_err_cck_blokker> 927 928 <enum 10 phyrx_err_cck_timing> 929 930 <enum 11 phyrx_err_cck_header_crc> 931 932 <enum 12 phyrx_err_cck_rate_illegal> 933 934 <enum 13 phyrx_err_cck_length_illegal> 935 936 <enum 14 phyrx_err_cck_restart> 937 938 <enum 15 phyrx_err_cck_service> 939 940 <enum 16 phyrx_err_cck_power_drop> 941 942 943 944 <enum 17 phyrx_err_ht_crc_err> 945 946 <enum 18 phyrx_err_ht_length_illegal> 947 948 <enum 19 phyrx_err_ht_rate_illegal> 949 950 <enum 20 phyrx_err_ht_zlf> 951 952 <enum 21 phyrx_err_false_radar_ext> 953 954 955 956 <enum 22 phyrx_err_green_field> 957 958 959 960 <enum 23 phyrx_err_bw_gt_dyn_bw> 961 962 <enum 24 phyrx_err_leg_ht_mismatch> 963 964 <enum 25 phyrx_err_vht_crc_error> 965 966 <enum 26 phyrx_err_vht_siga_unsupported> 967 968 <enum 27 phyrx_err_vht_lsig_len_invalid> 969 970 <enum 28 phyrx_err_vht_ndp_or_zlf> 971 972 <enum 29 phyrx_err_vht_nsym_lt_zero> 973 974 <enum 30 phyrx_err_vht_rx_extra_symbol_mismatch> 975 976 <enum 31 phyrx_err_vht_rx_skip_group_id0> 977 978 <enum 32 phyrx_err_vht_rx_skip_group_id1to62> 979 980 <enum 33 phyrx_err_vht_rx_skip_group_id63> 981 982 <enum 34 phyrx_err_ofdm_ldpc_decoder_disabled> 983 984 <enum 35 phyrx_err_defer_nap> 985 986 <enum 36 phyrx_err_fdomain_timeout> 987 988 <enum 37 phyrx_err_lsig_rel_check> 989 990 <enum 38 phyrx_err_bt_collision> 991 992 <enum 39 phyrx_err_unsupported_mu_feedback> 993 994 <enum 40 phyrx_err_ppdu_tx_interrupt_rx> 995 996 <enum 41 phyrx_err_unsupported_cbf> 997 998 999 1000 <enum 42 phyrx_err_other> Should not really be used. If 1001 needed, ask for documentation update 1002 1003 1004 1005 <enum 43 phyrx_err_he_siga_unsupported > <enum 44 1006 phyrx_err_he_crc_error > <enum 45 1007 phyrx_err_he_sigb_unsupported > <enum 46 1008 phyrx_err_he_mu_mode_unsupported > <enum 47 1009 phyrx_err_he_ndp_or_zlf > <enum 48 phyrx_err_he_nsym_lt_zero 1010 > <enum 49 phyrx_err_he_ru_params_unsupported > <enum 50 1011 phyrx_err_he_num_users_unsupported ><enum 51 1012 phyrx_err_he_sounding_params_unsupported > 1013 1014 1015 1016 <enum 52 phyrx_err_MU_UL_no_power_detected> 1017 1018 1019 1020 1021 1022 1023 1024 <legal 0 - 52> 1025 */ 1026 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000002c 1027 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 0 1028 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff 1029 1030 /* Description RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE 1031 1032 When set, PHY enters PHY NAP state after sending this 1033 abort 1034 1035 1036 1037 Note that nap and defer state are mutually exclusive. 1038 1039 1040 1041 Field put pro-actively in place....usage still to be 1042 agreed upon. 1043 1044 <legal all> 1045 */ 1046 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000002c 1047 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 8 1048 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x00000100 1049 1050 /* Description RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE 1051 1052 When set, PHY enters PHY defer state after sending this 1053 abort 1054 1055 1056 1057 Note that nap and defer state are mutually exclusive. 1058 1059 1060 1061 Field put pro-actively in place....usage still to be 1062 agreed upon. 1063 1064 <legal all> 1065 */ 1066 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000002c 1067 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 9 1068 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 1069 1070 /* Description RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0 1071 1072 <legal 0> 1073 */ 1074 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000002c 1075 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 10 1076 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000fc00 1077 1078 /* Description RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION 1079 1080 The remaining receive duration of this PPDU in the 1081 medium (in us). When PHY does not know this duration when 1082 this TLV is generated, the field will be set to 0. 1083 1084 The timing reference point is the reception by the MAC 1085 of this TLV. The value shall be accurate to within 2us. 1086 1087 1088 1089 In case Phy_enters_nap_state and/or 1090 Phy_enters_defer_state is set, there is a possibility that 1091 MAC PMM can also decide to go into a low(er) power state. 1092 1093 <legal all> 1094 */ 1095 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000002c 1096 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 16 1097 #define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff0000 1098 1099 /* EXTERNAL REFERENCE : struct macrx_abort_request_info macrx_abort_request_info_details */ 1100 1101 1102 /* Description RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON 1103 1104 <enum 0 macrx_abort_sw_initiated> 1105 1106 <enum 1 macrx_abort_obss_reception> Upon receiving this 1107 abort reason, PHY should stop reception of the current frame 1108 and go back into a search mode 1109 1110 <enum 2 macrx_abort_other> 1111 1112 <enum 3 macrx_abort_sw_initiated_channel_switch > MAC FW 1113 issued an abort for channel switch reasons 1114 1115 <enum 4 macrx_abort_sw_initiated_power_save > MAC FW 1116 issued an abort power save reasons 1117 1118 <enum 5 macrx_abort_too_much_bad_data > RXPCU is 1119 terminating the current ongoing reception, as the data that 1120 MAC is receiving seems to be all garbage... The PER is too 1121 high, or in case of MU UL, Likely the trigger frame never 1122 got properly received by any of the targeted MU UL devices. 1123 After the abort, PHYRX can resume a normal search mode. 1124 1125 1126 1127 <legal 0-5> 1128 */ 1129 #define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x00000030 1130 #define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0 1131 #define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x000000ff 1132 1133 /* Description RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0 1134 1135 <legal 0> 1136 */ 1137 #define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x00000030 1138 #define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8 1139 #define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000ff00 1140 1141 /* Description RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER 1142 1143 Field used by SW to double check that their structure 1144 alignment is in sync with what HW has done. 1145 1146 <legal 0xAABBCCDD> 1147 */ 1148 #define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_OFFSET 0x00000034 1149 #define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_LSB 0 1150 #define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_MASK 0xffffffff 1151 1152 1153 #endif // _RXPCU_PPDU_END_INFO_H_ 1154