xref: /wlan-driver/fw-api/hw/qca8074/v2/tx_msdu_extension.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2020 The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 // $ATH_LICENSE_HW_HDR_C$
18 //
19 // DO NOT EDIT!  This file is automatically generated
20 //               These definitions are tied to a particular hardware layout
21 
22 
23 #ifndef _TX_MSDU_EXTENSION_H_
24 #define _TX_MSDU_EXTENSION_H_
25 #if !defined(__ASSEMBLER__)
26 #endif
27 
28 
29 // ################ START SUMMARY #################
30 //
31 //	Dword	Fields
32 //	0	tso_enable[0], reserved_0a[6:1], tcp_flag[15:7], tcp_flag_mask[24:16], reserved_0b[31:25]
33 //	1	l2_length[15:0], ip_length[31:16]
34 //	2	tcp_seq_number[31:0]
35 //	3	ip_identification[15:0], udp_length[31:16]
36 //	4	checksum_offset[13:0], partial_checksum_en[14], reserved_4a[15], payload_start_offset[29:16], reserved_4b[31:30]
37 //	5	payload_end_offset[13:0], reserved_5a[15:14], wds[16], reserved_5b[31:17]
38 //	6	buf0_ptr_31_0[31:0]
39 //	7	buf0_ptr_39_32[7:0], reserved_7a[15:8], buf0_len[31:16]
40 //	8	buf1_ptr_31_0[31:0]
41 //	9	buf1_ptr_39_32[7:0], reserved_9a[15:8], buf1_len[31:16]
42 //	10	buf2_ptr_31_0[31:0]
43 //	11	buf2_ptr_39_32[7:0], reserved_11a[15:8], buf2_len[31:16]
44 //	12	buf3_ptr_31_0[31:0]
45 //	13	buf3_ptr_39_32[7:0], reserved_13a[15:8], buf3_len[31:16]
46 //	14	buf4_ptr_31_0[31:0]
47 //	15	buf4_ptr_39_32[7:0], reserved_15a[15:8], buf4_len[31:16]
48 //	16	buf5_ptr_31_0[31:0]
49 //	17	buf5_ptr_39_32[7:0], reserved_17a[15:8], buf5_len[31:16]
50 //
51 // ################ END SUMMARY #################
52 
53 #define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18
54 
55 struct tx_msdu_extension {
56              uint32_t tso_enable                      :  1, //[0]
57                       reserved_0a                     :  6, //[6:1]
58                       tcp_flag                        :  9, //[15:7]
59                       tcp_flag_mask                   :  9, //[24:16]
60                       reserved_0b                     :  7; //[31:25]
61              uint32_t l2_length                       : 16, //[15:0]
62                       ip_length                       : 16; //[31:16]
63              uint32_t tcp_seq_number                  : 32; //[31:0]
64              uint32_t ip_identification               : 16, //[15:0]
65                       udp_length                      : 16; //[31:16]
66              uint32_t checksum_offset                 : 14, //[13:0]
67                       partial_checksum_en             :  1, //[14]
68                       reserved_4a                     :  1, //[15]
69                       payload_start_offset            : 14, //[29:16]
70                       reserved_4b                     :  2; //[31:30]
71              uint32_t payload_end_offset              : 14, //[13:0]
72                       reserved_5a                     :  2, //[15:14]
73                       wds                             :  1, //[16]
74                       reserved_5b                     : 15; //[31:17]
75              uint32_t buf0_ptr_31_0                   : 32; //[31:0]
76              uint32_t buf0_ptr_39_32                  :  8, //[7:0]
77                       reserved_7a                     :  8, //[15:8]
78                       buf0_len                        : 16; //[31:16]
79              uint32_t buf1_ptr_31_0                   : 32; //[31:0]
80              uint32_t buf1_ptr_39_32                  :  8, //[7:0]
81                       reserved_9a                     :  8, //[15:8]
82                       buf1_len                        : 16; //[31:16]
83              uint32_t buf2_ptr_31_0                   : 32; //[31:0]
84              uint32_t buf2_ptr_39_32                  :  8, //[7:0]
85                       reserved_11a                    :  8, //[15:8]
86                       buf2_len                        : 16; //[31:16]
87              uint32_t buf3_ptr_31_0                   : 32; //[31:0]
88              uint32_t buf3_ptr_39_32                  :  8, //[7:0]
89                       reserved_13a                    :  8, //[15:8]
90                       buf3_len                        : 16; //[31:16]
91              uint32_t buf4_ptr_31_0                   : 32; //[31:0]
92              uint32_t buf4_ptr_39_32                  :  8, //[7:0]
93                       reserved_15a                    :  8, //[15:8]
94                       buf4_len                        : 16; //[31:16]
95              uint32_t buf5_ptr_31_0                   : 32; //[31:0]
96              uint32_t buf5_ptr_39_32                  :  8, //[7:0]
97                       reserved_17a                    :  8, //[15:8]
98                       buf5_len                        : 16; //[31:16]
99 };
100 
101 /*
102 
103 tso_enable
104 
105 			Enable transmit segmentation offload <legal all>
106 
107 reserved_0a
108 
109 			FW will set to 0, MAC will ignore.  <legal 0>
110 
111 tcp_flag
112 
113 			TCP flags
114 
115 			{NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}<legal all>
116 
117 tcp_flag_mask
118 
119 			TCP flag mask. Tcp_flag is inserted into the header
120 			based on the mask, if tso is enabled
121 
122 reserved_0b
123 
124 			FW will set to 0, MAC will ignore.  <legal 0>
125 
126 l2_length
127 
128 			L2 length for the msdu, if tso is enabled <legal all>
129 
130 ip_length
131 
132 			Ip length for the msdu, if tso is enabled <legal all>
133 
134 tcp_seq_number
135 
136 			Tcp_seq_number for the msdu, if tso is enabled <legal
137 			all>
138 
139 ip_identification
140 
141 			Ip_identification for the msdu, if tso is enabled <legal
142 			all>
143 
144 udp_length
145 
146 			TXDMA is copies this field into MSDU START TLV
147 
148 checksum_offset
149 
150 			The calculated checksum from start offset to end offset
151 			will be added to the checksum at the offset given by this
152 			field<legal all>
153 
154 partial_checksum_en
155 
156 			Partial Checksum Enable Bit.
157 
158 			<legal 0-1>
159 
160 reserved_4a
161 
162 			<Legal 0>
163 
164 payload_start_offset
165 
166 			L4 checksum calculations will start fromt this offset
167 
168 			<Legal all>
169 
170 reserved_4b
171 
172 			<Legal 0>
173 
174 payload_end_offset
175 
176 			L4 checksum calculations will end at this offset.
177 
178 			<Legal all>
179 
180 reserved_5a
181 
182 			<Legal 0>
183 
184 wds
185 
186 			If set the current packet is 4-address frame.  Required
187 			because an aggregate can include some frames with 3 address
188 			format and other frames with 4 address format.  Used by the
189 			OLE during encapsulation.
190 
191 			Note: there is also global wds tx control in the
192 			TX_PEER_ENTRY
193 
194 			<legal all>
195 
196 reserved_5b
197 
198 			<Legal 0>
199 
200 buf0_ptr_31_0
201 
202 			Lower 32 bits of the first buffer pointer
203 
204 
205 
206 			NOTE: SW/FW manages the 'cookie' info related to this
207 			buffer together with the 'cookie' info for this
208 			MSDU_EXTENSION descriptor
209 
210 			<legal all>
211 
212 buf0_ptr_39_32
213 
214 			Upper 8 bits of the first buffer pointer <legal all>
215 
216 reserved_7a
217 
218 			<Legal 0>
219 
220 buf0_len
221 
222 			Length of the first buffer <legal all>
223 
224 buf1_ptr_31_0
225 
226 			Lower 32 bits of the second buffer pointer
227 
228 
229 
230 			NOTE: SW/FW manages the 'cookie' info related to this
231 			buffer together with the 'cookie' info for this
232 			MSDU_EXTENSION descriptor
233 
234 			<legal all>
235 
236 buf1_ptr_39_32
237 
238 			Upper 8 bits of the second buffer pointer <legal all>
239 
240 reserved_9a
241 
242 			<Legal 0>
243 
244 buf1_len
245 
246 			Length of the second buffer <legal all>
247 
248 buf2_ptr_31_0
249 
250 			Lower 32 bits of the third buffer pointer
251 
252 			NOTE: SW/FW manages the 'cookie' info related to this
253 			buffer together with the 'cookie' info for this
254 			MSDU_EXTENSION descriptor
255 
256 			<legal all>
257 
258 buf2_ptr_39_32
259 
260 			Upper 8 bits of the third buffer pointer <legal all>
261 
262 reserved_11a
263 
264 			<Legal 0>
265 
266 buf2_len
267 
268 			Length of the third buffer <legal all>
269 
270 buf3_ptr_31_0
271 
272 			Lower 32 bits of the fourth buffer pointer
273 
274 
275 
276 			NOTE: SW/FW manages the 'cookie' info related to this
277 			buffer together with the 'cookie' info for this
278 			MSDU_EXTENSION descriptor
279 
280 			 <legal all>
281 
282 buf3_ptr_39_32
283 
284 			Upper 8 bits of the fourth buffer pointer <legal all>
285 
286 reserved_13a
287 
288 			<Legal 0>
289 
290 buf3_len
291 
292 			Length of the fourth buffer <legal all>
293 
294 buf4_ptr_31_0
295 
296 			Lower 32 bits of the fifth buffer pointer
297 
298 
299 
300 			NOTE: SW/FW manages the 'cookie' info related to this
301 			buffer together with the 'cookie' info for this
302 			MSDU_EXTENSION descriptor
303 
304 			<legal all>
305 
306 buf4_ptr_39_32
307 
308 			Upper 8 bits of the fifth buffer pointer <legal all>
309 
310 reserved_15a
311 
312 			<Legal 0>
313 
314 buf4_len
315 
316 			Length of the fifth buffer <legal all>
317 
318 buf5_ptr_31_0
319 
320 			Lower 32 bits of the sixth buffer pointer
321 
322 
323 
324 			NOTE: SW/FW manages the 'cookie' info related to this
325 			buffer together with the 'cookie' info for this
326 			MSDU_EXTENSION descriptor
327 
328 			 <legal all>
329 
330 buf5_ptr_39_32
331 
332 			Upper 8 bits of the sixth buffer pointer <legal all>
333 
334 reserved_17a
335 
336 			<Legal 0>
337 
338 buf5_len
339 
340 			Length of the sixth buffer <legal all>
341 */
342 
343 
344 /* Description		TX_MSDU_EXTENSION_0_TSO_ENABLE
345 
346 			Enable transmit segmentation offload <legal all>
347 */
348 #define TX_MSDU_EXTENSION_0_TSO_ENABLE_OFFSET                        0x00000000
349 #define TX_MSDU_EXTENSION_0_TSO_ENABLE_LSB                           0
350 #define TX_MSDU_EXTENSION_0_TSO_ENABLE_MASK                          0x00000001
351 
352 /* Description		TX_MSDU_EXTENSION_0_RESERVED_0A
353 
354 			FW will set to 0, MAC will ignore.  <legal 0>
355 */
356 #define TX_MSDU_EXTENSION_0_RESERVED_0A_OFFSET                       0x00000000
357 #define TX_MSDU_EXTENSION_0_RESERVED_0A_LSB                          1
358 #define TX_MSDU_EXTENSION_0_RESERVED_0A_MASK                         0x0000007e
359 
360 /* Description		TX_MSDU_EXTENSION_0_TCP_FLAG
361 
362 			TCP flags
363 
364 			{NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}<legal all>
365 */
366 #define TX_MSDU_EXTENSION_0_TCP_FLAG_OFFSET                          0x00000000
367 #define TX_MSDU_EXTENSION_0_TCP_FLAG_LSB                             7
368 #define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK                            0x0000ff80
369 
370 /* Description		TX_MSDU_EXTENSION_0_TCP_FLAG_MASK
371 
372 			TCP flag mask. Tcp_flag is inserted into the header
373 			based on the mask, if tso is enabled
374 */
375 #define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_OFFSET                     0x00000000
376 #define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_LSB                        16
377 #define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_MASK                       0x01ff0000
378 
379 /* Description		TX_MSDU_EXTENSION_0_RESERVED_0B
380 
381 			FW will set to 0, MAC will ignore.  <legal 0>
382 */
383 #define TX_MSDU_EXTENSION_0_RESERVED_0B_OFFSET                       0x00000000
384 #define TX_MSDU_EXTENSION_0_RESERVED_0B_LSB                          25
385 #define TX_MSDU_EXTENSION_0_RESERVED_0B_MASK                         0xfe000000
386 
387 /* Description		TX_MSDU_EXTENSION_1_L2_LENGTH
388 
389 			L2 length for the msdu, if tso is enabled <legal all>
390 */
391 #define TX_MSDU_EXTENSION_1_L2_LENGTH_OFFSET                         0x00000004
392 #define TX_MSDU_EXTENSION_1_L2_LENGTH_LSB                            0
393 #define TX_MSDU_EXTENSION_1_L2_LENGTH_MASK                           0x0000ffff
394 
395 /* Description		TX_MSDU_EXTENSION_1_IP_LENGTH
396 
397 			Ip length for the msdu, if tso is enabled <legal all>
398 */
399 #define TX_MSDU_EXTENSION_1_IP_LENGTH_OFFSET                         0x00000004
400 #define TX_MSDU_EXTENSION_1_IP_LENGTH_LSB                            16
401 #define TX_MSDU_EXTENSION_1_IP_LENGTH_MASK                           0xffff0000
402 
403 /* Description		TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER
404 
405 			Tcp_seq_number for the msdu, if tso is enabled <legal
406 			all>
407 */
408 #define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_OFFSET                    0x00000008
409 #define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_LSB                       0
410 #define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_MASK                      0xffffffff
411 
412 /* Description		TX_MSDU_EXTENSION_3_IP_IDENTIFICATION
413 
414 			Ip_identification for the msdu, if tso is enabled <legal
415 			all>
416 */
417 #define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_OFFSET                 0x0000000c
418 #define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_LSB                    0
419 #define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_MASK                   0x0000ffff
420 
421 /* Description		TX_MSDU_EXTENSION_3_UDP_LENGTH
422 
423 			TXDMA is copies this field into MSDU START TLV
424 */
425 #define TX_MSDU_EXTENSION_3_UDP_LENGTH_OFFSET                        0x0000000c
426 #define TX_MSDU_EXTENSION_3_UDP_LENGTH_LSB                           16
427 #define TX_MSDU_EXTENSION_3_UDP_LENGTH_MASK                          0xffff0000
428 
429 /* Description		TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET
430 
431 			The calculated checksum from start offset to end offset
432 			will be added to the checksum at the offset given by this
433 			field<legal all>
434 */
435 #define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_OFFSET                   0x00000010
436 #define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_LSB                      0
437 #define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_MASK                     0x00003fff
438 
439 /* Description		TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN
440 
441 			Partial Checksum Enable Bit.
442 
443 			<legal 0-1>
444 */
445 #define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_OFFSET               0x00000010
446 #define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_LSB                  14
447 #define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_MASK                 0x00004000
448 
449 /* Description		TX_MSDU_EXTENSION_4_RESERVED_4A
450 
451 			<Legal 0>
452 */
453 #define TX_MSDU_EXTENSION_4_RESERVED_4A_OFFSET                       0x00000010
454 #define TX_MSDU_EXTENSION_4_RESERVED_4A_LSB                          15
455 #define TX_MSDU_EXTENSION_4_RESERVED_4A_MASK                         0x00008000
456 
457 /* Description		TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET
458 
459 			L4 checksum calculations will start fromt this offset
460 
461 			<Legal all>
462 */
463 #define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_OFFSET              0x00000010
464 #define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_LSB                 16
465 #define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_MASK                0x3fff0000
466 
467 /* Description		TX_MSDU_EXTENSION_4_RESERVED_4B
468 
469 			<Legal 0>
470 */
471 #define TX_MSDU_EXTENSION_4_RESERVED_4B_OFFSET                       0x00000010
472 #define TX_MSDU_EXTENSION_4_RESERVED_4B_LSB                          30
473 #define TX_MSDU_EXTENSION_4_RESERVED_4B_MASK                         0xc0000000
474 
475 /* Description		TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET
476 
477 			L4 checksum calculations will end at this offset.
478 
479 			<Legal all>
480 */
481 #define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_OFFSET                0x00000014
482 #define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_LSB                   0
483 #define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_MASK                  0x00003fff
484 
485 /* Description		TX_MSDU_EXTENSION_5_RESERVED_5A
486 
487 			<Legal 0>
488 */
489 #define TX_MSDU_EXTENSION_5_RESERVED_5A_OFFSET                       0x00000014
490 #define TX_MSDU_EXTENSION_5_RESERVED_5A_LSB                          14
491 #define TX_MSDU_EXTENSION_5_RESERVED_5A_MASK                         0x0000c000
492 
493 /* Description		TX_MSDU_EXTENSION_5_WDS
494 
495 			If set the current packet is 4-address frame.  Required
496 			because an aggregate can include some frames with 3 address
497 			format and other frames with 4 address format.  Used by the
498 			OLE during encapsulation.
499 
500 			Note: there is also global wds tx control in the
501 			TX_PEER_ENTRY
502 
503 			<legal all>
504 */
505 #define TX_MSDU_EXTENSION_5_WDS_OFFSET                               0x00000014
506 #define TX_MSDU_EXTENSION_5_WDS_LSB                                  16
507 #define TX_MSDU_EXTENSION_5_WDS_MASK                                 0x00010000
508 
509 /* Description		TX_MSDU_EXTENSION_5_RESERVED_5B
510 
511 			<Legal 0>
512 */
513 #define TX_MSDU_EXTENSION_5_RESERVED_5B_OFFSET                       0x00000014
514 #define TX_MSDU_EXTENSION_5_RESERVED_5B_LSB                          17
515 #define TX_MSDU_EXTENSION_5_RESERVED_5B_MASK                         0xfffe0000
516 
517 /* Description		TX_MSDU_EXTENSION_6_BUF0_PTR_31_0
518 
519 			Lower 32 bits of the first buffer pointer
520 
521 
522 
523 			NOTE: SW/FW manages the 'cookie' info related to this
524 			buffer together with the 'cookie' info for this
525 			MSDU_EXTENSION descriptor
526 
527 			<legal all>
528 */
529 #define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET                     0x00000018
530 #define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_LSB                        0
531 #define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK                       0xffffffff
532 
533 /* Description		TX_MSDU_EXTENSION_7_BUF0_PTR_39_32
534 
535 			Upper 8 bits of the first buffer pointer <legal all>
536 */
537 #define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_OFFSET                    0x0000001c
538 #define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_LSB                       0
539 #define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK                      0x000000ff
540 
541 /* Description		TX_MSDU_EXTENSION_7_RESERVED_7A
542 
543 			<Legal 0>
544 */
545 #define TX_MSDU_EXTENSION_7_RESERVED_7A_OFFSET                       0x0000001c
546 #define TX_MSDU_EXTENSION_7_RESERVED_7A_LSB                          8
547 #define TX_MSDU_EXTENSION_7_RESERVED_7A_MASK                         0x0000ff00
548 
549 /* Description		TX_MSDU_EXTENSION_7_BUF0_LEN
550 
551 			Length of the first buffer <legal all>
552 */
553 #define TX_MSDU_EXTENSION_7_BUF0_LEN_OFFSET                          0x0000001c
554 #define TX_MSDU_EXTENSION_7_BUF0_LEN_LSB                             16
555 #define TX_MSDU_EXTENSION_7_BUF0_LEN_MASK                            0xffff0000
556 
557 /* Description		TX_MSDU_EXTENSION_8_BUF1_PTR_31_0
558 
559 			Lower 32 bits of the second buffer pointer
560 
561 
562 
563 			NOTE: SW/FW manages the 'cookie' info related to this
564 			buffer together with the 'cookie' info for this
565 			MSDU_EXTENSION descriptor
566 
567 			<legal all>
568 */
569 #define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_OFFSET                     0x00000020
570 #define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_LSB                        0
571 #define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_MASK                       0xffffffff
572 
573 /* Description		TX_MSDU_EXTENSION_9_BUF1_PTR_39_32
574 
575 			Upper 8 bits of the second buffer pointer <legal all>
576 */
577 #define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_OFFSET                    0x00000024
578 #define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_LSB                       0
579 #define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_MASK                      0x000000ff
580 
581 /* Description		TX_MSDU_EXTENSION_9_RESERVED_9A
582 
583 			<Legal 0>
584 */
585 #define TX_MSDU_EXTENSION_9_RESERVED_9A_OFFSET                       0x00000024
586 #define TX_MSDU_EXTENSION_9_RESERVED_9A_LSB                          8
587 #define TX_MSDU_EXTENSION_9_RESERVED_9A_MASK                         0x0000ff00
588 
589 /* Description		TX_MSDU_EXTENSION_9_BUF1_LEN
590 
591 			Length of the second buffer <legal all>
592 */
593 #define TX_MSDU_EXTENSION_9_BUF1_LEN_OFFSET                          0x00000024
594 #define TX_MSDU_EXTENSION_9_BUF1_LEN_LSB                             16
595 #define TX_MSDU_EXTENSION_9_BUF1_LEN_MASK                            0xffff0000
596 
597 /* Description		TX_MSDU_EXTENSION_10_BUF2_PTR_31_0
598 
599 			Lower 32 bits of the third buffer pointer
600 
601 			NOTE: SW/FW manages the 'cookie' info related to this
602 			buffer together with the 'cookie' info for this
603 			MSDU_EXTENSION descriptor
604 
605 			<legal all>
606 */
607 #define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_OFFSET                    0x00000028
608 #define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_LSB                       0
609 #define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_MASK                      0xffffffff
610 
611 /* Description		TX_MSDU_EXTENSION_11_BUF2_PTR_39_32
612 
613 			Upper 8 bits of the third buffer pointer <legal all>
614 */
615 #define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_OFFSET                   0x0000002c
616 #define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_LSB                      0
617 #define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_MASK                     0x000000ff
618 
619 /* Description		TX_MSDU_EXTENSION_11_RESERVED_11A
620 
621 			<Legal 0>
622 */
623 #define TX_MSDU_EXTENSION_11_RESERVED_11A_OFFSET                     0x0000002c
624 #define TX_MSDU_EXTENSION_11_RESERVED_11A_LSB                        8
625 #define TX_MSDU_EXTENSION_11_RESERVED_11A_MASK                       0x0000ff00
626 
627 /* Description		TX_MSDU_EXTENSION_11_BUF2_LEN
628 
629 			Length of the third buffer <legal all>
630 */
631 #define TX_MSDU_EXTENSION_11_BUF2_LEN_OFFSET                         0x0000002c
632 #define TX_MSDU_EXTENSION_11_BUF2_LEN_LSB                            16
633 #define TX_MSDU_EXTENSION_11_BUF2_LEN_MASK                           0xffff0000
634 
635 /* Description		TX_MSDU_EXTENSION_12_BUF3_PTR_31_0
636 
637 			Lower 32 bits of the fourth buffer pointer
638 
639 
640 
641 			NOTE: SW/FW manages the 'cookie' info related to this
642 			buffer together with the 'cookie' info for this
643 			MSDU_EXTENSION descriptor
644 
645 			 <legal all>
646 */
647 #define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_OFFSET                    0x00000030
648 #define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_LSB                       0
649 #define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_MASK                      0xffffffff
650 
651 /* Description		TX_MSDU_EXTENSION_13_BUF3_PTR_39_32
652 
653 			Upper 8 bits of the fourth buffer pointer <legal all>
654 */
655 #define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_OFFSET                   0x00000034
656 #define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_LSB                      0
657 #define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_MASK                     0x000000ff
658 
659 /* Description		TX_MSDU_EXTENSION_13_RESERVED_13A
660 
661 			<Legal 0>
662 */
663 #define TX_MSDU_EXTENSION_13_RESERVED_13A_OFFSET                     0x00000034
664 #define TX_MSDU_EXTENSION_13_RESERVED_13A_LSB                        8
665 #define TX_MSDU_EXTENSION_13_RESERVED_13A_MASK                       0x0000ff00
666 
667 /* Description		TX_MSDU_EXTENSION_13_BUF3_LEN
668 
669 			Length of the fourth buffer <legal all>
670 */
671 #define TX_MSDU_EXTENSION_13_BUF3_LEN_OFFSET                         0x00000034
672 #define TX_MSDU_EXTENSION_13_BUF3_LEN_LSB                            16
673 #define TX_MSDU_EXTENSION_13_BUF3_LEN_MASK                           0xffff0000
674 
675 /* Description		TX_MSDU_EXTENSION_14_BUF4_PTR_31_0
676 
677 			Lower 32 bits of the fifth buffer pointer
678 
679 
680 
681 			NOTE: SW/FW manages the 'cookie' info related to this
682 			buffer together with the 'cookie' info for this
683 			MSDU_EXTENSION descriptor
684 
685 			<legal all>
686 */
687 #define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_OFFSET                    0x00000038
688 #define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_LSB                       0
689 #define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_MASK                      0xffffffff
690 
691 /* Description		TX_MSDU_EXTENSION_15_BUF4_PTR_39_32
692 
693 			Upper 8 bits of the fifth buffer pointer <legal all>
694 */
695 #define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_OFFSET                   0x0000003c
696 #define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_LSB                      0
697 #define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_MASK                     0x000000ff
698 
699 /* Description		TX_MSDU_EXTENSION_15_RESERVED_15A
700 
701 			<Legal 0>
702 */
703 #define TX_MSDU_EXTENSION_15_RESERVED_15A_OFFSET                     0x0000003c
704 #define TX_MSDU_EXTENSION_15_RESERVED_15A_LSB                        8
705 #define TX_MSDU_EXTENSION_15_RESERVED_15A_MASK                       0x0000ff00
706 
707 /* Description		TX_MSDU_EXTENSION_15_BUF4_LEN
708 
709 			Length of the fifth buffer <legal all>
710 */
711 #define TX_MSDU_EXTENSION_15_BUF4_LEN_OFFSET                         0x0000003c
712 #define TX_MSDU_EXTENSION_15_BUF4_LEN_LSB                            16
713 #define TX_MSDU_EXTENSION_15_BUF4_LEN_MASK                           0xffff0000
714 
715 /* Description		TX_MSDU_EXTENSION_16_BUF5_PTR_31_0
716 
717 			Lower 32 bits of the sixth buffer pointer
718 
719 
720 
721 			NOTE: SW/FW manages the 'cookie' info related to this
722 			buffer together with the 'cookie' info for this
723 			MSDU_EXTENSION descriptor
724 
725 			 <legal all>
726 */
727 #define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_OFFSET                    0x00000040
728 #define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_LSB                       0
729 #define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_MASK                      0xffffffff
730 
731 /* Description		TX_MSDU_EXTENSION_17_BUF5_PTR_39_32
732 
733 			Upper 8 bits of the sixth buffer pointer <legal all>
734 */
735 #define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_OFFSET                   0x00000044
736 #define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_LSB                      0
737 #define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_MASK                     0x000000ff
738 
739 /* Description		TX_MSDU_EXTENSION_17_RESERVED_17A
740 
741 			<Legal 0>
742 */
743 #define TX_MSDU_EXTENSION_17_RESERVED_17A_OFFSET                     0x00000044
744 #define TX_MSDU_EXTENSION_17_RESERVED_17A_LSB                        8
745 #define TX_MSDU_EXTENSION_17_RESERVED_17A_MASK                       0x0000ff00
746 
747 /* Description		TX_MSDU_EXTENSION_17_BUF5_LEN
748 
749 			Length of the sixth buffer <legal all>
750 */
751 #define TX_MSDU_EXTENSION_17_BUF5_LEN_OFFSET                         0x00000044
752 #define TX_MSDU_EXTENSION_17_BUF5_LEN_LSB                            16
753 #define TX_MSDU_EXTENSION_17_BUF5_LEN_MASK                           0xffff0000
754 
755 
756 #endif // _TX_MSDU_EXTENSION_H_
757