1 /* 2 * Copyright (c) 2020 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 /////////////////////////////////////////////////////////////////////////////////////////////// 18 // 19 // wfss_ce_reg_seq_hwioreg.h : automatically generated by Autoseq 3.1 5/20/2018 20 // User Name:vakkati 21 // 22 // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. 23 // 24 /////////////////////////////////////////////////////////////////////////////////////////////// 25 26 #ifndef __WFSS_CE_REG_SEQ_REG_H__ 27 #define __WFSS_CE_REG_SEQ_REG_H__ 28 29 #include "seq_hwio.h" 30 #include "wfss_ce_reg_seq_hwiobase.h" 31 #ifdef SCALE_INCLUDES 32 #include "HALhwio.h" 33 #else 34 #include "msmhwio.h" 35 #endif 36 37 38 /////////////////////////////////////////////////////////////////////////////////////////////// 39 // Register Data for Block WFSS_CE_CHANNEL_DST_REG 40 /////////////////////////////////////////////////////////////////////////////////////////////// 41 42 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB //// 43 44 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) (x+0x00000000) 45 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) (x+0x00000000) 46 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff 47 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_SHFT 0 48 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ 49 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) 50 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, mask) \ 51 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), mask) 52 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, val) \ 53 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), val) 54 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x, mask, val) \ 55 do {\ 56 HWIO_INTLOCK(); \ 57 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)); \ 58 HWIO_INTFREE();\ 59 } while (0) 60 61 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 62 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 63 64 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB //// 65 66 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) (x+0x00000004) 67 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) (x+0x00000004) 68 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0x00ffffff 69 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_SHFT 0 70 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ 71 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) 72 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, mask) \ 73 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), mask) 74 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, val) \ 75 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), val) 76 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x, mask, val) \ 77 do {\ 78 HWIO_INTLOCK(); \ 79 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)); \ 80 HWIO_INTFREE();\ 81 } while (0) 82 83 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 84 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 85 86 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 87 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 88 89 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID //// 90 91 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) (x+0x00000008) 92 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) (x+0x00000008) 93 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0x000000ff 94 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_SHFT 0 95 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ 96 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) 97 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, mask) \ 98 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), mask) 99 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, val) \ 100 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), val) 101 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x, mask, val) \ 102 do {\ 103 HWIO_INTLOCK(); \ 104 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)); \ 105 HWIO_INTFREE();\ 106 } while (0) 107 108 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 109 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 110 111 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS //// 112 113 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) (x+0x0000000c) 114 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) (x+0x0000000c) 115 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff 116 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_SHFT 0 117 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ 118 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) 119 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, mask) \ 120 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), mask) 121 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OUT(x, val) \ 122 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), val) 123 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OUTM(x, mask, val) \ 124 do {\ 125 HWIO_INTLOCK(); \ 126 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x)); \ 127 HWIO_INTFREE();\ 128 } while (0) 129 130 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 131 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 132 133 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 134 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 135 136 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC //// 137 138 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) (x+0x00000010) 139 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) (x+0x00000010) 140 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x003fffff 141 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SHFT 0 142 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ 143 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) 144 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, mask) \ 145 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), mask) 146 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, val) \ 147 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), val) 148 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x, mask, val) \ 149 do {\ 150 HWIO_INTLOCK(); \ 151 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)); \ 152 HWIO_INTFREE();\ 153 } while (0) 154 155 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 156 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe 157 158 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 159 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 160 161 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 162 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 163 164 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 165 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 166 167 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 168 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6 169 170 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 171 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 172 173 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 174 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 175 176 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 177 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 178 179 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x00000004 180 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2 181 182 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 183 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 184 185 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 186 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0 187 188 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB //// 189 190 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) (x+0x0000001c) 191 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) (x+0x0000001c) 192 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff 193 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_SHFT 0 194 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ 195 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) 196 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, mask) \ 197 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), mask) 198 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, val) \ 199 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), val) 200 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 201 do {\ 202 HWIO_INTLOCK(); \ 203 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)); \ 204 HWIO_INTFREE();\ 205 } while (0) 206 207 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 208 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 209 210 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB //// 211 212 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000020) 213 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000020) 214 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0x000000ff 215 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_SHFT 0 216 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ 217 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) 218 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, mask) \ 219 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), mask) 220 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, val) \ 221 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), val) 222 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 223 do {\ 224 HWIO_INTLOCK(); \ 225 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)); \ 226 HWIO_INTFREE();\ 227 } while (0) 228 229 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 230 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 231 232 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0 //// 233 234 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000030) 235 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000030) 236 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 237 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 238 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 239 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) 240 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 241 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 242 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 243 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 244 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 245 do {\ 246 HWIO_INTLOCK(); \ 247 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 248 HWIO_INTFREE();\ 249 } while (0) 250 251 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 252 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 253 254 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 255 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 256 257 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 258 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 259 260 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1 //// 261 262 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000034) 263 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000034) 264 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 265 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 266 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 267 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) 268 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 269 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 270 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 271 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 272 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 273 do {\ 274 HWIO_INTLOCK(); \ 275 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 276 HWIO_INTFREE();\ 277 } while (0) 278 279 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 280 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 281 282 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS //// 283 284 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000038) 285 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000038) 286 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 287 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_SHFT 0 288 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ 289 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) 290 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 291 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 292 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 293 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), val) 294 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 295 do {\ 296 HWIO_INTLOCK(); \ 297 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x)); \ 298 HWIO_INTFREE();\ 299 } while (0) 300 301 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 302 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 303 304 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 305 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 306 307 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 308 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 309 310 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER //// 311 312 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000003c) 313 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000003c) 314 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 315 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 316 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 317 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) 318 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 319 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 320 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 321 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 322 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 323 do {\ 324 HWIO_INTLOCK(); \ 325 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 326 HWIO_INTFREE();\ 327 } while (0) 328 329 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 330 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 331 332 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER //// 333 334 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000040) 335 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000040) 336 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 337 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 338 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 339 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) 340 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 341 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 342 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 343 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 344 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 345 do {\ 346 HWIO_INTLOCK(); \ 347 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 348 HWIO_INTFREE();\ 349 } while (0) 350 351 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 352 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 353 354 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS //// 355 356 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000044) 357 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000044) 358 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 359 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 360 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 361 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) 362 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 363 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 364 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 365 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 366 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 367 do {\ 368 HWIO_INTLOCK(); \ 369 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 370 HWIO_INTFREE();\ 371 } while (0) 372 373 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 374 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 375 376 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 377 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 378 379 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB //// 380 381 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000048) 382 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000048) 383 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff 384 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_SHFT 0 385 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ 386 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) 387 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, mask) \ 388 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), mask) 389 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, val) \ 390 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), val) 391 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 392 do {\ 393 HWIO_INTLOCK(); \ 394 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)); \ 395 HWIO_INTFREE();\ 396 } while (0) 397 398 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 399 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 400 401 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB //// 402 403 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) (x+0x0000004c) 404 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) (x+0x0000004c) 405 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x000001ff 406 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_SHFT 0 407 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ 408 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) 409 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, mask) \ 410 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), mask) 411 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, val) \ 412 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), val) 413 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 414 do {\ 415 HWIO_INTLOCK(); \ 416 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)); \ 417 HWIO_INTFREE();\ 418 } while (0) 419 420 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 421 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 422 423 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 424 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 425 426 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA //// 427 428 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) (x+0x00000050) 429 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) (x+0x00000050) 430 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff 431 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_SHFT 0 432 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ 433 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) 434 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, mask) \ 435 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), mask) 436 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, val) \ 437 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), val) 438 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x, mask, val) \ 439 do {\ 440 HWIO_INTLOCK(); \ 441 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)); \ 442 HWIO_INTFREE();\ 443 } while (0) 444 445 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 446 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 447 448 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET //// 449 450 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000054) 451 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000054) 452 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 453 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_SHFT 0 454 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ 455 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) 456 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 457 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 458 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 459 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), val) 460 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 461 do {\ 462 HWIO_INTLOCK(); \ 463 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)); \ 464 HWIO_INTFREE();\ 465 } while (0) 466 467 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 468 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 469 470 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB //// 471 472 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) (x+0x00000058) 473 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) (x+0x00000058) 474 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff 475 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_SHFT 0 476 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ 477 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) 478 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, mask) \ 479 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), mask) 480 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, val) \ 481 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), val) 482 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x, mask, val) \ 483 do {\ 484 HWIO_INTLOCK(); \ 485 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)); \ 486 HWIO_INTFREE();\ 487 } while (0) 488 489 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 490 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 491 492 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB //// 493 494 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) (x+0x0000005c) 495 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) (x+0x0000005c) 496 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0x00ffffff 497 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_SHFT 0 498 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ 499 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) 500 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, mask) \ 501 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), mask) 502 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, val) \ 503 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), val) 504 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x, mask, val) \ 505 do {\ 506 HWIO_INTLOCK(); \ 507 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)); \ 508 HWIO_INTFREE();\ 509 } while (0) 510 511 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 512 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 513 514 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 515 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 516 517 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID //// 518 519 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) (x+0x00000060) 520 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) (x+0x00000060) 521 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0x0000ffff 522 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_SHFT 0 523 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ 524 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) 525 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, mask) \ 526 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), mask) 527 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, val) \ 528 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), val) 529 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x, mask, val) \ 530 do {\ 531 HWIO_INTLOCK(); \ 532 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)); \ 533 HWIO_INTFREE();\ 534 } while (0) 535 536 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0x0000ff00 537 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 538 539 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 540 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 541 542 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS //// 543 544 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) (x+0x00000064) 545 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) (x+0x00000064) 546 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff 547 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_SHFT 0 548 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ 549 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) 550 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, mask) \ 551 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), mask) 552 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OUT(x, val) \ 553 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), val) 554 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OUTM(x, mask, val) \ 555 do {\ 556 HWIO_INTLOCK(); \ 557 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x)); \ 558 HWIO_INTFREE();\ 559 } while (0) 560 561 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 562 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 563 564 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 565 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 566 567 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC //// 568 569 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) (x+0x00000068) 570 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) (x+0x00000068) 571 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x03ffffff 572 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SHFT 0 573 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ 574 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) 575 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, mask) \ 576 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), mask) 577 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, val) \ 578 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), val) 579 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x, mask, val) \ 580 do {\ 581 HWIO_INTLOCK(); \ 582 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)); \ 583 HWIO_INTFREE();\ 584 } while (0) 585 586 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x03c00000 587 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 588 589 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 590 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe 591 592 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 593 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 594 595 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 596 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 597 598 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 599 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 600 601 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 602 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 603 604 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 605 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 606 607 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 608 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 609 610 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 611 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 612 613 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x00000004 614 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 615 616 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 617 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 618 619 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 620 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 621 622 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB //// 623 624 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) (x+0x0000006c) 625 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) (x+0x0000006c) 626 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff 627 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_SHFT 0 628 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ 629 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) 630 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, mask) \ 631 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask) 632 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, val) \ 633 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), val) 634 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ 635 do {\ 636 HWIO_INTLOCK(); \ 637 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)); \ 638 HWIO_INTFREE();\ 639 } while (0) 640 641 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff 642 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 643 644 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB //// 645 646 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000070) 647 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000070) 648 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0x000000ff 649 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_SHFT 0 650 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ 651 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) 652 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, mask) \ 653 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask) 654 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, val) \ 655 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), val) 656 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ 657 do {\ 658 HWIO_INTLOCK(); \ 659 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)); \ 660 HWIO_INTFREE();\ 661 } while (0) 662 663 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff 664 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 665 666 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP //// 667 668 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x0000007c) 669 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x0000007c) 670 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff 671 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SHFT 0 672 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ 673 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) 674 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, mask) \ 675 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 676 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, val) \ 677 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), val) 678 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ 679 do {\ 680 HWIO_INTLOCK(); \ 681 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)); \ 682 HWIO_INTFREE();\ 683 } while (0) 684 685 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 686 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 687 688 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 689 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf 690 691 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 692 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 693 694 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS //// 695 696 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000080) 697 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000080) 698 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff 699 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_SHFT 0 700 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ 701 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) 702 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, mask) \ 703 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 704 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OUT(x, val) \ 705 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), val) 706 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ 707 do {\ 708 HWIO_INTLOCK(); \ 709 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x)); \ 710 HWIO_INTFREE();\ 711 } while (0) 712 713 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 714 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 715 716 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 717 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf 718 719 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 720 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 721 722 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER //// 723 724 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000084) 725 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000084) 726 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff 727 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_SHFT 0 728 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ 729 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) 730 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ 731 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 732 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ 733 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) 734 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ 735 do {\ 736 HWIO_INTLOCK(); \ 737 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)); \ 738 HWIO_INTFREE();\ 739 } while (0) 740 741 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff 742 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 743 744 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB //// 745 746 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000000a0) 747 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000000a0) 748 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff 749 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_SHFT 0 750 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ 751 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) 752 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, mask) \ 753 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask) 754 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, val) \ 755 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), val) 756 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 757 do {\ 758 HWIO_INTLOCK(); \ 759 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)); \ 760 HWIO_INTFREE();\ 761 } while (0) 762 763 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 764 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 765 766 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB //// 767 768 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000000a4) 769 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000000a4) 770 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x000001ff 771 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_SHFT 0 772 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ 773 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) 774 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, mask) \ 775 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask) 776 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, val) \ 777 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), val) 778 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 779 do {\ 780 HWIO_INTLOCK(); \ 781 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)); \ 782 HWIO_INTFREE();\ 783 } while (0) 784 785 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 786 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 787 788 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 789 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 790 791 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA //// 792 793 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) (x+0x000000a8) 794 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) (x+0x000000a8) 795 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff 796 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_SHFT 0 797 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ 798 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) 799 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, mask) \ 800 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), mask) 801 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, val) \ 802 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), val) 803 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x, mask, val) \ 804 do {\ 805 HWIO_INTLOCK(); \ 806 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)); \ 807 HWIO_INTFREE();\ 808 } while (0) 809 810 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 811 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 812 813 //// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET //// 814 815 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000000ac) 816 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000000ac) 817 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 818 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_SHFT 0 819 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ 820 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) 821 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 822 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 823 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 824 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), val) 825 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 826 do {\ 827 HWIO_INTLOCK(); \ 828 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)); \ 829 HWIO_INTFREE();\ 830 } while (0) 831 832 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 833 #define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 834 835 //// Register WFSS_CE_CHANNEL_DST_R0_DEST_CTRL //// 836 837 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) (x+0x000000b0) 838 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) (x+0x000000b0) 839 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x0001ffff 840 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_SHFT 0 841 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ 842 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) 843 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, mask) \ 844 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), mask) 845 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, val) \ 846 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), val) 847 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x, mask, val) \ 848 do {\ 849 HWIO_INTLOCK(); \ 850 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)); \ 851 HWIO_INTFREE();\ 852 } while (0) 853 854 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x00010000 855 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 856 857 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0x0000ffff 858 #define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0 859 860 //// Register WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS //// 861 862 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) (x+0x000000b4) 863 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) (x+0x000000b4) 864 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x0000003f 865 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_SHFT 0 866 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ 867 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) 868 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, mask) \ 869 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), mask) 870 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, val) \ 871 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), val) 872 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x, mask, val) \ 873 do {\ 874 HWIO_INTLOCK(); \ 875 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)); \ 876 HWIO_INTFREE();\ 877 } while (0) 878 879 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x00000020 880 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 881 882 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x00000010 883 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4 884 885 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x00000008 886 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3 887 888 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x00000004 889 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2 890 891 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x00000002 892 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1 893 894 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x00000001 895 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0 896 897 //// Register WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2 //// 898 899 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) (x+0x000000b8) 900 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) (x+0x000000b8) 901 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0x0000000f 902 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_SHFT 0 903 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ 904 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) 905 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, mask) \ 906 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), mask) 907 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, val) \ 908 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), val) 909 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x, mask, val) \ 910 do {\ 911 HWIO_INTLOCK(); \ 912 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)); \ 913 HWIO_INTFREE();\ 914 } while (0) 915 916 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x00000008 917 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 918 919 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x00000004 920 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2 921 922 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x00000002 923 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1 924 925 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x00000001 926 #define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0 927 928 //// Register WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP //// 929 930 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) (x+0x00000400) 931 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) (x+0x00000400) 932 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0x0000ffff 933 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_SHFT 0 934 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ 935 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) 936 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, mask) \ 937 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), mask) 938 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, val) \ 939 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), val) 940 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x, mask, val) \ 941 do {\ 942 HWIO_INTLOCK(); \ 943 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)); \ 944 HWIO_INTFREE();\ 945 } while (0) 946 947 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0x0000ffff 948 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 949 950 //// Register WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP //// 951 952 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) (x+0x00000404) 953 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) (x+0x00000404) 954 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0x0000ffff 955 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_SHFT 0 956 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ 957 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) 958 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, mask) \ 959 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), mask) 960 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, val) \ 961 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), val) 962 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x, mask, val) \ 963 do {\ 964 HWIO_INTLOCK(); \ 965 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)); \ 966 HWIO_INTFREE();\ 967 } while (0) 968 969 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0x0000ffff 970 #define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 971 972 //// Register WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP //// 973 974 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) (x+0x00000408) 975 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) (x+0x00000408) 976 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0x0000ffff 977 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_SHFT 0 978 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ 979 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) 980 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, mask) \ 981 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), mask) 982 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, val) \ 983 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), val) 984 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x, mask, val) \ 985 do {\ 986 HWIO_INTLOCK(); \ 987 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)); \ 988 HWIO_INTFREE();\ 989 } while (0) 990 991 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0x0000ffff 992 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 993 994 //// Register WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP //// 995 996 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) (x+0x0000040c) 997 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) (x+0x0000040c) 998 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0x0000ffff 999 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_SHFT 0 1000 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ 1001 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) 1002 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, mask) \ 1003 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), mask) 1004 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, val) \ 1005 out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), val) 1006 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x, mask, val) \ 1007 do {\ 1008 HWIO_INTLOCK(); \ 1009 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)); \ 1010 HWIO_INTFREE();\ 1011 } while (0) 1012 1013 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0x0000ffff 1014 #define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 1015 1016 1017 /////////////////////////////////////////////////////////////////////////////////////////////// 1018 // Register Data for Block WFSS_CE_CHANNEL_SRC_REG 1019 /////////////////////////////////////////////////////////////////////////////////////////////// 1020 1021 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB //// 1022 1023 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) (x+0x00000000) 1024 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) (x+0x00000000) 1025 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff 1026 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_SHFT 0 1027 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ 1028 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) 1029 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, mask) \ 1030 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), mask) 1031 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, val) \ 1032 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), val) 1033 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x, mask, val) \ 1034 do {\ 1035 HWIO_INTLOCK(); \ 1036 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)); \ 1037 HWIO_INTFREE();\ 1038 } while (0) 1039 1040 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff 1041 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 1042 1043 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB //// 1044 1045 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) (x+0x00000004) 1046 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) (x+0x00000004) 1047 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0x00ffffff 1048 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_SHFT 0 1049 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ 1050 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) 1051 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, mask) \ 1052 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), mask) 1053 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, val) \ 1054 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), val) 1055 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x, mask, val) \ 1056 do {\ 1057 HWIO_INTLOCK(); \ 1058 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)); \ 1059 HWIO_INTFREE();\ 1060 } while (0) 1061 1062 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 1063 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 1064 1065 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff 1066 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 1067 1068 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID //// 1069 1070 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) (x+0x00000008) 1071 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) (x+0x00000008) 1072 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0x000000ff 1073 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_SHFT 0 1074 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ 1075 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) 1076 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, mask) \ 1077 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), mask) 1078 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, val) \ 1079 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), val) 1080 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x, mask, val) \ 1081 do {\ 1082 HWIO_INTLOCK(); \ 1083 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)); \ 1084 HWIO_INTFREE();\ 1085 } while (0) 1086 1087 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0x000000ff 1088 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 1089 1090 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS //// 1091 1092 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) (x+0x0000000c) 1093 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) (x+0x0000000c) 1094 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff 1095 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_SHFT 0 1096 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ 1097 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) 1098 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, mask) \ 1099 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), mask) 1100 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OUT(x, val) \ 1101 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), val) 1102 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OUTM(x, mask, val) \ 1103 do {\ 1104 HWIO_INTLOCK(); \ 1105 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x)); \ 1106 HWIO_INTFREE();\ 1107 } while (0) 1108 1109 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 1110 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 1111 1112 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff 1113 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 1114 1115 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC //// 1116 1117 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) (x+0x00000010) 1118 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) (x+0x00000010) 1119 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x003fffff 1120 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SHFT 0 1121 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ 1122 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) 1123 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, mask) \ 1124 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), mask) 1125 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, val) \ 1126 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), val) 1127 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x, mask, val) \ 1128 do {\ 1129 HWIO_INTLOCK(); \ 1130 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)); \ 1131 HWIO_INTFREE();\ 1132 } while (0) 1133 1134 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 1135 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe 1136 1137 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 1138 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc 1139 1140 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 1141 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 1142 1143 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 1144 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 1145 1146 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 1147 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6 1148 1149 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 1150 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 1151 1152 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 1153 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 1154 1155 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 1156 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 1157 1158 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x00000004 1159 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2 1160 1161 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 1162 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 1163 1164 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 1165 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0 1166 1167 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB //// 1168 1169 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) (x+0x0000001c) 1170 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) (x+0x0000001c) 1171 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff 1172 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_SHFT 0 1173 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ 1174 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) 1175 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, mask) \ 1176 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), mask) 1177 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, val) \ 1178 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), val) 1179 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ 1180 do {\ 1181 HWIO_INTLOCK(); \ 1182 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)); \ 1183 HWIO_INTFREE();\ 1184 } while (0) 1185 1186 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff 1187 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 1188 1189 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB //// 1190 1191 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000020) 1192 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000020) 1193 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0x000000ff 1194 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_SHFT 0 1195 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ 1196 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) 1197 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, mask) \ 1198 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), mask) 1199 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, val) \ 1200 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), val) 1201 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ 1202 do {\ 1203 HWIO_INTLOCK(); \ 1204 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)); \ 1205 HWIO_INTFREE();\ 1206 } while (0) 1207 1208 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff 1209 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 1210 1211 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0 //// 1212 1213 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000030) 1214 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000030) 1215 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff 1216 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 1217 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ 1218 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) 1219 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ 1220 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 1221 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ 1222 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) 1223 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ 1224 do {\ 1225 HWIO_INTLOCK(); \ 1226 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ 1227 HWIO_INTFREE();\ 1228 } while (0) 1229 1230 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 1231 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 1232 1233 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 1234 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf 1235 1236 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff 1237 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 1238 1239 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1 //// 1240 1241 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000034) 1242 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000034) 1243 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff 1244 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 1245 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ 1246 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) 1247 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ 1248 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 1249 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ 1250 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) 1251 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ 1252 do {\ 1253 HWIO_INTLOCK(); \ 1254 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ 1255 HWIO_INTFREE();\ 1256 } while (0) 1257 1258 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff 1259 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 1260 1261 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS //// 1262 1263 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000038) 1264 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000038) 1265 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff 1266 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_SHFT 0 1267 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ 1268 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) 1269 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, mask) \ 1270 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 1271 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OUT(x, val) \ 1272 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), val) 1273 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ 1274 do {\ 1275 HWIO_INTLOCK(); \ 1276 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x)); \ 1277 HWIO_INTFREE();\ 1278 } while (0) 1279 1280 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 1281 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 1282 1283 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 1284 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf 1285 1286 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff 1287 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 1288 1289 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER //// 1290 1291 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000003c) 1292 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000003c) 1293 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff 1294 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 1295 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ 1296 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) 1297 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ 1298 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 1299 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ 1300 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) 1301 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ 1302 do {\ 1303 HWIO_INTLOCK(); \ 1304 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ 1305 HWIO_INTFREE();\ 1306 } while (0) 1307 1308 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff 1309 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 1310 1311 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER //// 1312 1313 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000040) 1314 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000040) 1315 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 1316 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 1317 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ 1318 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) 1319 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ 1320 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 1321 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ 1322 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) 1323 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ 1324 do {\ 1325 HWIO_INTLOCK(); \ 1326 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ 1327 HWIO_INTFREE();\ 1328 } while (0) 1329 1330 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 1331 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 1332 1333 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS //// 1334 1335 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000044) 1336 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000044) 1337 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff 1338 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 1339 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ 1340 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) 1341 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ 1342 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 1343 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ 1344 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) 1345 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ 1346 do {\ 1347 HWIO_INTLOCK(); \ 1348 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ 1349 HWIO_INTFREE();\ 1350 } while (0) 1351 1352 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 1353 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 1354 1355 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff 1356 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 1357 1358 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB //// 1359 1360 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000048) 1361 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000048) 1362 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff 1363 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_SHFT 0 1364 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ 1365 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) 1366 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, mask) \ 1367 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), mask) 1368 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, val) \ 1369 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), val) 1370 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ 1371 do {\ 1372 HWIO_INTLOCK(); \ 1373 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)); \ 1374 HWIO_INTFREE();\ 1375 } while (0) 1376 1377 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff 1378 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 1379 1380 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB //// 1381 1382 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) (x+0x0000004c) 1383 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) (x+0x0000004c) 1384 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x000001ff 1385 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_SHFT 0 1386 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ 1387 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) 1388 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, mask) \ 1389 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), mask) 1390 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, val) \ 1391 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), val) 1392 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ 1393 do {\ 1394 HWIO_INTLOCK(); \ 1395 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)); \ 1396 HWIO_INTFREE();\ 1397 } while (0) 1398 1399 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 1400 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 1401 1402 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff 1403 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 1404 1405 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA //// 1406 1407 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) (x+0x00000050) 1408 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) (x+0x00000050) 1409 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff 1410 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_SHFT 0 1411 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ 1412 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) 1413 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, mask) \ 1414 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), mask) 1415 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, val) \ 1416 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), val) 1417 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x, mask, val) \ 1418 do {\ 1419 HWIO_INTLOCK(); \ 1420 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)); \ 1421 HWIO_INTFREE();\ 1422 } while (0) 1423 1424 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff 1425 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 1426 1427 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET //// 1428 1429 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000054) 1430 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000054) 1431 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff 1432 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_SHFT 0 1433 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ 1434 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) 1435 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, mask) \ 1436 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 1437 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, val) \ 1438 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), val) 1439 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ 1440 do {\ 1441 HWIO_INTLOCK(); \ 1442 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)); \ 1443 HWIO_INTFREE();\ 1444 } while (0) 1445 1446 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff 1447 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 1448 1449 //// Register WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL //// 1450 1451 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) (x+0x00000058) 1452 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) (x+0x00000058) 1453 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x0000001f 1454 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SHFT 0 1455 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ 1456 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) 1457 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, mask) \ 1458 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), mask) 1459 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, val) \ 1460 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), val) 1461 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x, mask, val) \ 1462 do {\ 1463 HWIO_INTLOCK(); \ 1464 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)); \ 1465 HWIO_INTFREE();\ 1466 } while (0) 1467 1468 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x00000010 1469 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 1470 1471 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x00000008 1472 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3 1473 1474 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x00000004 1475 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2 1476 1477 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x00000002 1478 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1 1479 1480 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x00000001 1481 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0 1482 1483 //// Register WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS //// 1484 1485 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) (x+0x0000005c) 1486 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) (x+0x0000005c) 1487 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x0000001f 1488 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SHFT 0 1489 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ 1490 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) 1491 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, mask) \ 1492 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), mask) 1493 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, val) \ 1494 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), val) 1495 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x, mask, val) \ 1496 do {\ 1497 HWIO_INTLOCK(); \ 1498 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)); \ 1499 HWIO_INTFREE();\ 1500 } while (0) 1501 1502 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x00000010 1503 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 1504 1505 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x00000008 1506 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3 1507 1508 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x00000004 1509 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2 1510 1511 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x00000002 1512 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1 1513 1514 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x00000001 1515 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0 1516 1517 //// Register WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG //// 1518 1519 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) (x+0x00000060) 1520 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) (x+0x00000060) 1521 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff 1522 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_SHFT 0 1523 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ 1524 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) 1525 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, mask) \ 1526 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), mask) 1527 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, val) \ 1528 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), val) 1529 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x, mask, val) \ 1530 do {\ 1531 HWIO_INTLOCK(); \ 1532 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)); \ 1533 HWIO_INTFREE();\ 1534 } while (0) 1535 1536 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 1537 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 1538 1539 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0x0000ffff 1540 #define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0 1541 1542 //// Register WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP //// 1543 1544 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) (x+0x00000400) 1545 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) (x+0x00000400) 1546 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0x0000ffff 1547 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_SHFT 0 1548 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ 1549 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) 1550 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, mask) \ 1551 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), mask) 1552 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, val) \ 1553 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), val) 1554 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x, mask, val) \ 1555 do {\ 1556 HWIO_INTLOCK(); \ 1557 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)); \ 1558 HWIO_INTFREE();\ 1559 } while (0) 1560 1561 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0x0000ffff 1562 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 1563 1564 //// Register WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP //// 1565 1566 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) (x+0x00000404) 1567 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) (x+0x00000404) 1568 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0x0000ffff 1569 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_SHFT 0 1570 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ 1571 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) 1572 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, mask) \ 1573 in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), mask) 1574 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, val) \ 1575 out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), val) 1576 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x, mask, val) \ 1577 do {\ 1578 HWIO_INTLOCK(); \ 1579 out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)); \ 1580 HWIO_INTFREE();\ 1581 } while (0) 1582 1583 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0x0000ffff 1584 #define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 1585 1586 1587 /////////////////////////////////////////////////////////////////////////////////////////////// 1588 // Register Data for Block WFSS_CE_COMMON_REG 1589 /////////////////////////////////////////////////////////////////////////////////////////////// 1590 1591 //// Register WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER //// 1592 1593 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x) (x+0x00000000) 1594 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_PHYS(x) (x+0x00000000) 1595 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK 0xffffffff 1596 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_SHFT 0 1597 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_IN(x) \ 1598 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK) 1599 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_INM(x, mask) \ 1600 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), mask) 1601 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_OUT(x, val) \ 1602 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), val) 1603 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_OUTM(x, mask, val) \ 1604 do {\ 1605 HWIO_INTLOCK(); \ 1606 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_IN(x)); \ 1607 HWIO_INTFREE();\ 1608 } while (0) 1609 1610 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_BMSK 0xffffffff 1611 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_SHFT 0x0 1612 1613 //// Register WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER //// 1614 1615 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x) (x+0x00000004) 1616 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_PHYS(x) (x+0x00000004) 1617 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK 0x000000ff 1618 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_SHFT 0 1619 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_IN(x) \ 1620 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK) 1621 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_INM(x, mask) \ 1622 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), mask) 1623 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_OUT(x, val) \ 1624 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), val) 1625 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_OUTM(x, mask, val) \ 1626 do {\ 1627 HWIO_INTLOCK(); \ 1628 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_IN(x)); \ 1629 HWIO_INTFREE();\ 1630 } while (0) 1631 1632 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_BMSK 0x000000ff 1633 #define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_SHFT 0x0 1634 1635 //// Register WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0 //// 1636 1637 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x) (x+0x00000008) 1638 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_PHYS(x) (x+0x00000008) 1639 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK 0x00000fff 1640 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SHFT 0 1641 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_IN(x) \ 1642 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK) 1643 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_INM(x, mask) \ 1644 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), mask) 1645 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_OUT(x, val) \ 1646 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), val) 1647 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_OUTM(x, mask, val) \ 1648 do {\ 1649 HWIO_INTLOCK(); \ 1650 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_IN(x)); \ 1651 HWIO_INTFREE();\ 1652 } while (0) 1653 1654 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00 1655 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 1656 1657 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0 1658 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4 1659 1660 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f 1661 #define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0 1662 1663 //// Register WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK //// 1664 1665 #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x) (x+0x0000000c) 1666 #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_PHYS(x) (x+0x0000000c) 1667 #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK 0x00000001 1668 #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_SHFT 0 1669 #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN(x) \ 1670 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK) 1671 #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_INM(x, mask) \ 1672 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), mask) 1673 #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUT(x, val) \ 1674 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), val) 1675 #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 1676 do {\ 1677 HWIO_INTLOCK(); \ 1678 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN(x)); \ 1679 HWIO_INTFREE();\ 1680 } while (0) 1681 1682 #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 1683 #define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 1684 1685 //// Register WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE //// 1686 1687 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x) (x+0x00000010) 1688 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_PHYS(x) (x+0x00000010) 1689 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK 0x80000fff 1690 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_SHFT 0 1691 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN(x) \ 1692 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK) 1693 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_INM(x, mask) \ 1694 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), mask) 1695 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUT(x, val) \ 1696 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), val) 1697 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ 1698 do {\ 1699 HWIO_INTLOCK(); \ 1700 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN(x)); \ 1701 HWIO_INTFREE();\ 1702 } while (0) 1703 1704 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 1705 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f 1706 1707 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_SPARE_BMSK 0x00000800 1708 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_SPARE_SHFT 0xb 1709 1710 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WDOG_CTR_BMSK 0x00000400 1711 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WDOG_CTR_SHFT 0xa 1712 1713 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_FIFO_BMSK 0x00000200 1714 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_FIFO_SHFT 0x9 1715 1716 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_FIFO_BMSK 0x00000100 1717 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_FIFO_SHFT 0x8 1718 1719 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_BMSK 0x00000080 1720 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_SHFT 0x7 1721 1722 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_AXI_MAS_BMSK 0x00000040 1723 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_AXI_MAS_SHFT 0x6 1724 1725 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_BMSK 0x00000020 1726 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_SHFT 0x5 1727 1728 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_BMSK 0x00000010 1729 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_SHFT 0x4 1730 1731 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_CMD_BMSK 0x00000008 1732 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_CMD_SHFT 0x3 1733 1734 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_CMD_BMSK 0x00000004 1735 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_CMD_SHFT 0x2 1736 1737 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_CMD_BMSK 0x00000002 1738 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_CMD_SHFT 0x1 1739 1740 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CORE_BMSK 0x00000001 1741 #define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CORE_SHFT 0x0 1742 1743 //// Register WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS //// 1744 1745 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x) (x+0x00000014) 1746 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_PHYS(x) (x+0x00000014) 1747 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK 0x01010101 1748 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_SHFT 0 1749 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_IN(x) \ 1750 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK) 1751 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_INM(x, mask) \ 1752 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), mask) 1753 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_OUT(x, val) \ 1754 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), val) 1755 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_OUTM(x, mask, val) \ 1756 do {\ 1757 HWIO_INTLOCK(); \ 1758 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_IN(x)); \ 1759 HWIO_INTFREE();\ 1760 } while (0) 1761 1762 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000 1763 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 1764 1765 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000 1766 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10 1767 1768 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100 1769 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8 1770 1771 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001 1772 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0 1773 1774 //// Register WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS //// 1775 1776 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x) (x+0x00000018) 1777 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_PHYS(x) (x+0x00000018) 1778 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK 0x003f3f3f 1779 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_SHFT 0 1780 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_IN(x) \ 1781 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK) 1782 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_INM(x, mask) \ 1783 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), mask) 1784 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_OUT(x, val) \ 1785 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), val) 1786 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_OUTM(x, mask, val) \ 1787 do {\ 1788 HWIO_INTLOCK(); \ 1789 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_IN(x)); \ 1790 HWIO_INTFREE();\ 1791 } while (0) 1792 1793 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000 1794 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 1795 1796 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00 1797 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8 1798 1799 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f 1800 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0 1801 1802 //// Register WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL //// 1803 1804 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x0000001c) 1805 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x0000001c) 1806 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f 1807 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_SHFT 0 1808 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN(x) \ 1809 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK) 1810 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_INM(x, mask) \ 1811 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), mask) 1812 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUT(x, val) \ 1813 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), val) 1814 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ 1815 do {\ 1816 HWIO_INTLOCK(); \ 1817 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN(x)); \ 1818 HWIO_INTFREE();\ 1819 } while (0) 1820 1821 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 1822 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 1823 1824 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 1825 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10 1826 1827 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00 1828 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8 1829 1830 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f 1831 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0 1832 1833 //// Register WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL //// 1834 1835 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x) (x+0x00000020) 1836 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_PHYS(x) (x+0x00000020) 1837 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f 1838 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_SHFT 0 1839 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN(x) \ 1840 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK) 1841 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_INM(x, mask) \ 1842 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), mask) 1843 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUT(x, val) \ 1844 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), val) 1845 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ 1846 do {\ 1847 HWIO_INTLOCK(); \ 1848 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN(x)); \ 1849 HWIO_INTFREE();\ 1850 } while (0) 1851 1852 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 1853 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 1854 1855 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 1856 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10 1857 1858 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00 1859 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8 1860 1861 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f 1862 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0 1863 1864 //// Register WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL //// 1865 1866 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x) (x+0x00000024) 1867 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_PHYS(x) (x+0x00000024) 1868 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK 0x0fffffff 1869 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_SHFT 0 1870 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN(x) \ 1871 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK) 1872 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_INM(x, mask) \ 1873 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), mask) 1874 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUT(x, val) \ 1875 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), val) 1876 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUTM(x, mask, val) \ 1877 do {\ 1878 HWIO_INTLOCK(); \ 1879 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN(x)); \ 1880 HWIO_INTFREE();\ 1881 } while (0) 1882 1883 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_BMSK 0x08000000 1884 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_SHFT 0x1b 1885 1886 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_BMSK 0x04000000 1887 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_SHFT 0x1a 1888 1889 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_BMSK 0x02000000 1890 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_SHFT 0x19 1891 1892 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_BMSK 0x01000000 1893 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_SHFT 0x18 1894 1895 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_BMSK 0x00800000 1896 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_SHFT 0x17 1897 1898 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000 1899 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 1900 1901 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000 1902 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11 1903 1904 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00 1905 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9 1906 1907 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe 1908 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1 1909 1910 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001 1911 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0 1912 1913 //// Register WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL //// 1914 1915 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x) (x+0x00000028) 1916 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_PHYS(x) (x+0x00000028) 1917 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK 0xffff0001 1918 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_SHFT 0 1919 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN(x) \ 1920 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK) 1921 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_INM(x, mask) \ 1922 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), mask) 1923 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUT(x, val) \ 1924 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), val) 1925 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ 1926 do {\ 1927 HWIO_INTLOCK(); \ 1928 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN(x)); \ 1929 HWIO_INTFREE();\ 1930 } while (0) 1931 1932 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 1933 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 1934 1935 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001 1936 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0 1937 1938 //// Register WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS //// 1939 1940 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x) (x+0x0000002c) 1941 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_PHYS(x) (x+0x0000002c) 1942 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK 0x0000ffff 1943 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_SHFT 0 1944 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_IN(x) \ 1945 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK) 1946 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_INM(x, mask) \ 1947 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), mask) 1948 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_OUT(x, val) \ 1949 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), val) 1950 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_OUTM(x, mask, val) \ 1951 do {\ 1952 HWIO_INTLOCK(); \ 1953 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_IN(x)); \ 1954 HWIO_INTFREE();\ 1955 } while (0) 1956 1957 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff 1958 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 1959 1960 //// Register WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS //// 1961 1962 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x) (x+0x00000030) 1963 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_PHYS(x) (x+0x00000030) 1964 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK 0xffffffff 1965 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_SHFT 0 1966 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_IN(x) \ 1967 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK) 1968 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_INM(x, mask) \ 1969 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), mask) 1970 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_OUT(x, val) \ 1971 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), val) 1972 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ 1973 do {\ 1974 HWIO_INTLOCK(); \ 1975 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_IN(x)); \ 1976 HWIO_INTFREE();\ 1977 } while (0) 1978 1979 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 1980 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 1981 1982 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff 1983 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0 1984 1985 //// Register WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL //// 1986 1987 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR(x) (x+0x00000034) 1988 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_PHYS(x) (x+0x00000034) 1989 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_RMSK 0x000fffff 1990 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_SHFT 0 1991 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_IN(x) \ 1992 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_RMSK) 1993 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_INM(x, mask) \ 1994 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR(x), mask) 1995 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_OUT(x, val) \ 1996 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR(x), val) 1997 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_OUTM(x, mask, val) \ 1998 do {\ 1999 HWIO_INTLOCK(); \ 2000 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_IN(x)); \ 2001 HWIO_INTFREE();\ 2002 } while (0) 2003 2004 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0x000e0000 2005 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11 2006 2007 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x00010000 2008 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10 2009 2010 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0x0000ffff 2011 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0 2012 2013 //// Register WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL //// 2014 2015 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR(x) (x+0x00000038) 2016 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_PHYS(x) (x+0x00000038) 2017 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_RMSK 0x000fffff 2018 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_SHFT 0 2019 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_IN(x) \ 2020 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_RMSK) 2021 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_INM(x, mask) \ 2022 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR(x), mask) 2023 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_OUT(x, val) \ 2024 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR(x), val) 2025 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_OUTM(x, mask, val) \ 2026 do {\ 2027 HWIO_INTLOCK(); \ 2028 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_IN(x)); \ 2029 HWIO_INTFREE();\ 2030 } while (0) 2031 2032 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0x000e0000 2033 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11 2034 2035 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x00010000 2036 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10 2037 2038 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0x0000ffff 2039 #define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0 2040 2041 //// Register WFSS_CE_COMMON_R0_CE_HOST_IE_0 //// 2042 2043 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x) (x+0x0000003c) 2044 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_PHYS(x) (x+0x0000003c) 2045 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK 0x01ffffff 2046 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SHFT 0 2047 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN(x) \ 2048 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK) 2049 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_INM(x, mask) \ 2050 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), mask) 2051 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUT(x, val) \ 2052 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), val) 2053 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUTM(x, mask, val) \ 2054 do {\ 2055 HWIO_INTLOCK(); \ 2056 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN(x)); \ 2057 HWIO_INTFREE();\ 2058 } while (0) 2059 2060 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_BMSK 0x01000000 2061 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_SHFT 0x18 2062 2063 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_BMSK 0x00fff000 2064 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_SHFT 0xc 2065 2066 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_BMSK 0x00000fff 2067 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_SHFT 0x0 2068 2069 //// Register WFSS_CE_COMMON_R0_CE_HOST_IE_1 //// 2070 2071 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x) (x+0x00000040) 2072 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_PHYS(x) (x+0x00000040) 2073 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK 0x00000fff 2074 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_SHFT 0 2075 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN(x) \ 2076 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK) 2077 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_INM(x, mask) \ 2078 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), mask) 2079 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUT(x, val) \ 2080 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), val) 2081 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUTM(x, mask, val) \ 2082 do {\ 2083 HWIO_INTLOCK(); \ 2084 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN(x)); \ 2085 HWIO_INTFREE();\ 2086 } while (0) 2087 2088 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_BMSK 0x00000fff 2089 #define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_SHFT 0x0 2090 2091 //// Register WFSS_CE_COMMON_R0_CE_SECURITY //// 2092 2093 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x) (x+0x00000044) 2094 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_PHYS(x) (x+0x00000044) 2095 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK 0x00ffffff 2096 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_SHFT 0 2097 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_IN(x) \ 2098 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK) 2099 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_INM(x, mask) \ 2100 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), mask) 2101 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_OUT(x, val) \ 2102 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), val) 2103 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_OUTM(x, mask, val) \ 2104 do {\ 2105 HWIO_INTLOCK(); \ 2106 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_IN(x)); \ 2107 HWIO_INTFREE();\ 2108 } while (0) 2109 2110 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_BMSK 0x00fff000 2111 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_SHFT 0xc 2112 2113 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_BMSK 0x00000fff 2114 #define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_SHFT 0x0 2115 2116 //// Register WFSS_CE_COMMON_R0_CE_TARGET_IE_0 //// 2117 2118 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x) (x+0x00000048) 2119 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_PHYS(x) (x+0x00000048) 2120 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK 0x01ffffff 2121 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SHFT 0 2122 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN(x) \ 2123 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK) 2124 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_INM(x, mask) \ 2125 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), mask) 2126 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUT(x, val) \ 2127 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), val) 2128 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUTM(x, mask, val) \ 2129 do {\ 2130 HWIO_INTLOCK(); \ 2131 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN(x)); \ 2132 HWIO_INTFREE();\ 2133 } while (0) 2134 2135 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_BMSK 0x01000000 2136 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_SHFT 0x18 2137 2138 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_BMSK 0x00fff000 2139 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_SHFT 0xc 2140 2141 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_BMSK 0x00000fff 2142 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_SHFT 0x0 2143 2144 //// Register WFSS_CE_COMMON_R0_CE_TARGET_IE_1 //// 2145 2146 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x) (x+0x0000004c) 2147 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_PHYS(x) (x+0x0000004c) 2148 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK 0x00000fff 2149 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_SHFT 0 2150 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN(x) \ 2151 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK) 2152 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_INM(x, mask) \ 2153 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), mask) 2154 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUT(x, val) \ 2155 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), val) 2156 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUTM(x, mask, val) \ 2157 do {\ 2158 HWIO_INTLOCK(); \ 2159 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN(x)); \ 2160 HWIO_INTFREE();\ 2161 } while (0) 2162 2163 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_BMSK 0x00000fff 2164 #define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_SHFT 0x0 2165 2166 //// Register WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0 //// 2167 2168 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x) (x+0x00000050) 2169 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_PHYS(x) (x+0x00000050) 2170 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK 0xffffffff 2171 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SHFT 0 2172 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN(x) \ 2173 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK) 2174 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_INM(x, mask) \ 2175 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), mask) 2176 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUT(x, val) \ 2177 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), val) 2178 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUTM(x, mask, val) \ 2179 do {\ 2180 HWIO_INTLOCK(); \ 2181 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN(x)); \ 2182 HWIO_INTFREE();\ 2183 } while (0) 2184 2185 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_BMSK 0xffffffff 2186 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_SHFT 0x0 2187 2188 //// Register WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1 //// 2189 2190 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x) (x+0x00000054) 2191 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_PHYS(x) (x+0x00000054) 2192 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK 0x0001ffff 2193 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SHFT 0 2194 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN(x) \ 2195 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK) 2196 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_INM(x, mask) \ 2197 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), mask) 2198 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUT(x, val) \ 2199 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), val) 2200 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUTM(x, mask, val) \ 2201 do {\ 2202 HWIO_INTLOCK(); \ 2203 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN(x)); \ 2204 HWIO_INTFREE();\ 2205 } while (0) 2206 2207 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_BMSK 0x0001ffff 2208 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_SHFT 0x0 2209 2210 //// Register WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0 //// 2211 2212 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x) (x+0x00000058) 2213 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_PHYS(x) (x+0x00000058) 2214 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_RMSK 0xffffffff 2215 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_SHFT 0 2216 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_IN(x) \ 2217 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_RMSK) 2218 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_INM(x, mask) \ 2219 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x), mask) 2220 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OUT(x, val) \ 2221 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x), val) 2222 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OUTM(x, mask, val) \ 2223 do {\ 2224 HWIO_INTLOCK(); \ 2225 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_IN(x)); \ 2226 HWIO_INTFREE();\ 2227 } while (0) 2228 2229 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POLY_0_BMSK 0xffffffff 2230 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POLY_0_SHFT 0x0 2231 2232 //// Register WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1 //// 2233 2234 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x) (x+0x0000005c) 2235 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_PHYS(x) (x+0x0000005c) 2236 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_RMSK 0x0001ffff 2237 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_SHFT 0 2238 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_IN(x) \ 2239 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_RMSK) 2240 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_INM(x, mask) \ 2241 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x), mask) 2242 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OUT(x, val) \ 2243 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x), val) 2244 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OUTM(x, mask, val) \ 2245 do {\ 2246 HWIO_INTLOCK(); \ 2247 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_IN(x)); \ 2248 HWIO_INTFREE();\ 2249 } while (0) 2250 2251 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POLY_1_BMSK 0x0001ffff 2252 #define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POLY_1_SHFT 0x0 2253 2254 //// Register WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0 //// 2255 2256 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x) (x+0x00000060) 2257 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_PHYS(x) (x+0x00000060) 2258 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK 0xffffffff 2259 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_SHFT 0 2260 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_IN(x) \ 2261 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK) 2262 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_INM(x, mask) \ 2263 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), mask) 2264 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_OUT(x, val) \ 2265 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), val) 2266 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_OUTM(x, mask, val) \ 2267 do {\ 2268 HWIO_INTLOCK(); \ 2269 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_IN(x)); \ 2270 HWIO_INTFREE();\ 2271 } while (0) 2272 2273 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_BMSK 0xffffffff 2274 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_SHFT 0x0 2275 2276 //// Register WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1 //// 2277 2278 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x) (x+0x00000064) 2279 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_PHYS(x) (x+0x00000064) 2280 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK 0xffffffff 2281 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_SHFT 0 2282 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_IN(x) \ 2283 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK) 2284 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_INM(x, mask) \ 2285 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), mask) 2286 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_OUT(x, val) \ 2287 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), val) 2288 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_OUTM(x, mask, val) \ 2289 do {\ 2290 HWIO_INTLOCK(); \ 2291 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_IN(x)); \ 2292 HWIO_INTFREE();\ 2293 } while (0) 2294 2295 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_BMSK 0xffffffff 2296 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_SHFT 0x0 2297 2298 //// Register WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2 //// 2299 2300 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x) (x+0x00000068) 2301 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_PHYS(x) (x+0x00000068) 2302 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK 0xffffffff 2303 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_SHFT 0 2304 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_IN(x) \ 2305 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK) 2306 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_INM(x, mask) \ 2307 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), mask) 2308 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_OUT(x, val) \ 2309 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), val) 2310 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_OUTM(x, mask, val) \ 2311 do {\ 2312 HWIO_INTLOCK(); \ 2313 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_IN(x)); \ 2314 HWIO_INTFREE();\ 2315 } while (0) 2316 2317 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_BMSK 0xffffffff 2318 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_SHFT 0x0 2319 2320 //// Register WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3 //// 2321 2322 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x) (x+0x0000006c) 2323 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_PHYS(x) (x+0x0000006c) 2324 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK 0xffffffff 2325 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_SHFT 0 2326 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_IN(x) \ 2327 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK) 2328 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_INM(x, mask) \ 2329 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), mask) 2330 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_OUT(x, val) \ 2331 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), val) 2332 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_OUTM(x, mask, val) \ 2333 do {\ 2334 HWIO_INTLOCK(); \ 2335 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_IN(x)); \ 2336 HWIO_INTFREE();\ 2337 } while (0) 2338 2339 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_BMSK 0xffffffff 2340 #define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_SHFT 0x0 2341 2342 //// Register WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS //// 2343 2344 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x) (x+0x00000070) 2345 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_PHYS(x) (x+0x00000070) 2346 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_RMSK 0xfffdffff 2347 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_SHFT 0 2348 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_IN(x) \ 2349 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_RMSK) 2350 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_INM(x, mask) \ 2351 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), mask) 2352 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_OUT(x, val) \ 2353 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), val) 2354 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_OUTM(x, mask, val) \ 2355 do {\ 2356 HWIO_INTLOCK(); \ 2357 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_IN(x)); \ 2358 HWIO_INTFREE();\ 2359 } while (0) 2360 2361 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CLK_EXTEND_BMSK 0x80000000 2362 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CLK_EXTEND_SHFT 0x1f 2363 2364 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_WRAPPER_REG_CLK_BMSK 0x40000000 2365 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_WRAPPER_REG_CLK_SHFT 0x1e 2366 2367 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_REG_CLK_BMSK 0x3ffc0000 2368 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_REG_CLK_SHFT 0x12 2369 2370 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_IC_CLK_BMSK 0x00010000 2371 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_IC_CLK_SHFT 0x10 2372 2373 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_DMA_CLK_BMSK 0x0000f000 2374 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_DMA_CLK_SHFT 0xc 2375 2376 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_CORE_CLK_BMSK 0x00000fff 2377 #define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_CORE_CLK_SHFT 0x0 2378 2379 //// Register WFSS_CE_COMMON_R0_CE_IDLE_CONFIG //// 2380 2381 #define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x) (x+0x00000074) 2382 #define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_PHYS(x) (x+0x00000074) 2383 #define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_RMSK 0x00000fff 2384 #define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_SHFT 0 2385 #define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IN(x) \ 2386 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_RMSK) 2387 #define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_INM(x, mask) \ 2388 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x), mask) 2389 #define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_OUT(x, val) \ 2390 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x), val) 2391 #define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_OUTM(x, mask, val) \ 2392 do {\ 2393 HWIO_INTLOCK(); \ 2394 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IN(x)); \ 2395 HWIO_INTFREE();\ 2396 } while (0) 2397 2398 #define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IDLE_CFG_BMSK 0x00000fff 2399 #define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IDLE_CFG_SHFT 0x0 2400 2401 //// Register WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR //// 2402 2403 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_ADDR(x) (x+0x00000078) 2404 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_PHYS(x) (x+0x00000078) 2405 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_RMSK 0xffffffff 2406 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_SHFT 0 2407 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_IN(x) \ 2408 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_RMSK) 2409 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_INM(x, mask) \ 2410 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_ADDR(x), mask) 2411 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_OUT(x, val) \ 2412 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_ADDR(x), val) 2413 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_OUTM(x, mask, val) \ 2414 do {\ 2415 HWIO_INTLOCK(); \ 2416 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_IN(x)); \ 2417 HWIO_INTFREE();\ 2418 } while (0) 2419 2420 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_VALUE_BMSK 0xffffffff 2421 #define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_VALUE_SHFT 0x0 2422 2423 //// Register WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER //// 2424 2425 #define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR(x) (x+0x0000007c) 2426 #define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_PHYS(x) (x+0x0000007c) 2427 #define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_RMSK 0xffffffff 2428 #define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_SHFT 0 2429 #define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_IN(x) \ 2430 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_RMSK) 2431 #define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_INM(x, mask) \ 2432 in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR(x), mask) 2433 #define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_OUT(x, val) \ 2434 out_dword( HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR(x), val) 2435 #define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_OUTM(x, mask, val) \ 2436 do {\ 2437 HWIO_INTLOCK(); \ 2438 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_IN(x)); \ 2439 HWIO_INTFREE();\ 2440 } while (0) 2441 2442 #define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_VAL_BMSK 0xffffffff 2443 #define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_VAL_SHFT 0x0 2444 2445 //// Register WFSS_CE_COMMON_R1_TESTBUS_CTRL //// 2446 2447 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x) (x+0x00000400) 2448 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_PHYS(x) (x+0x00000400) 2449 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK 0x000100ff 2450 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_SHFT 0 2451 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN(x) \ 2452 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK) 2453 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_INM(x, mask) \ 2454 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), mask) 2455 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUT(x, val) \ 2456 out_dword( HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), val) 2457 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUTM(x, mask, val) \ 2458 do {\ 2459 HWIO_INTLOCK(); \ 2460 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN(x)); \ 2461 HWIO_INTFREE();\ 2462 } while (0) 2463 2464 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK 0x00010000 2465 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT 0x10 2466 2467 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_BMSK 0x000000ff 2468 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_SHFT 0x0 2469 2470 //// Register WFSS_CE_COMMON_R1_EVENTMASK_IX_0 //// 2471 2472 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x) (x+0x00000404) 2473 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_PHYS(x) (x+0x00000404) 2474 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK 0xffffffff 2475 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_SHFT 0 2476 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN(x) \ 2477 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK) 2478 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_INM(x, mask) \ 2479 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), mask) 2480 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUT(x, val) \ 2481 out_dword( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), val) 2482 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUTM(x, mask, val) \ 2483 do {\ 2484 HWIO_INTLOCK(); \ 2485 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN(x)); \ 2486 HWIO_INTFREE();\ 2487 } while (0) 2488 2489 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_BMSK 0xffffffff 2490 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_SHFT 0x0 2491 2492 //// Register WFSS_CE_COMMON_R1_EVENTMASK_IX_1 //// 2493 2494 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x) (x+0x00000408) 2495 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_PHYS(x) (x+0x00000408) 2496 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK 0xffffffff 2497 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_SHFT 0 2498 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN(x) \ 2499 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK) 2500 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_INM(x, mask) \ 2501 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), mask) 2502 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUT(x, val) \ 2503 out_dword( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), val) 2504 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUTM(x, mask, val) \ 2505 do {\ 2506 HWIO_INTLOCK(); \ 2507 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN(x)); \ 2508 HWIO_INTFREE();\ 2509 } while (0) 2510 2511 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_BMSK 0xffffffff 2512 #define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_SHFT 0x0 2513 2514 //// Register WFSS_CE_COMMON_R1_TESTBUS_LOW //// 2515 2516 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x) (x+0x0000040c) 2517 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_PHYS(x) (x+0x0000040c) 2518 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK 0xffffffff 2519 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_SHFT 0 2520 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_IN(x) \ 2521 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK) 2522 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_INM(x, mask) \ 2523 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), mask) 2524 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_OUT(x, val) \ 2525 out_dword( HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), val) 2526 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_OUTM(x, mask, val) \ 2527 do {\ 2528 HWIO_INTLOCK(); \ 2529 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_IN(x)); \ 2530 HWIO_INTFREE();\ 2531 } while (0) 2532 2533 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_BMSK 0xffffffff 2534 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_SHFT 0x0 2535 2536 //// Register WFSS_CE_COMMON_R1_TESTBUS_HIGH //// 2537 2538 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x) (x+0x00000410) 2539 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_PHYS(x) (x+0x00000410) 2540 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK 0x000000ff 2541 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_SHFT 0 2542 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_IN(x) \ 2543 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK) 2544 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_INM(x, mask) \ 2545 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), mask) 2546 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_OUT(x, val) \ 2547 out_dword( HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), val) 2548 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_OUTM(x, mask, val) \ 2549 do {\ 2550 HWIO_INTLOCK(); \ 2551 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_IN(x)); \ 2552 HWIO_INTFREE();\ 2553 } while (0) 2554 2555 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_BMSK 0x000000ff 2556 #define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_SHFT 0x0 2557 2558 //// Register WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL //// 2559 2560 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) (x+0x00000414) 2561 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) (x+0x00000414) 2562 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff 2563 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_SHFT 0 2564 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ 2565 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK) 2566 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, mask) \ 2567 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask) 2568 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, val) \ 2569 out_dword( HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), val) 2570 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x, mask, val) \ 2571 do {\ 2572 HWIO_INTLOCK(); \ 2573 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)); \ 2574 HWIO_INTFREE();\ 2575 } while (0) 2576 2577 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 2578 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 0x11 2579 2580 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x0001fffc 2581 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 0x2 2582 2583 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x00000002 2584 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 0x1 2585 2586 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x00000001 2587 #define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0x0 2588 2589 //// Register WFSS_CE_COMMON_R1_END_OF_TEST_CHECK //// 2590 2591 #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00000418) 2592 #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00000418) 2593 #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK 0x00000001 2594 #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_SHFT 0 2595 #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN(x) \ 2596 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK) 2597 #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_INM(x, mask) \ 2598 in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), mask) 2599 #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUT(x, val) \ 2600 out_dword( HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), val) 2601 #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ 2602 do {\ 2603 HWIO_INTLOCK(); \ 2604 out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN(x)); \ 2605 HWIO_INTFREE();\ 2606 } while (0) 2607 2608 #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 2609 #define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 2610 2611 2612 /////////////////////////////////////////////////////////////////////////////////////////////// 2613 // Register Data for Block WFSS_CE_REG 2614 /////////////////////////////////////////////////////////////////////////////////////////////// 2615 2616 2617 #endif 2618 2619