xref: /wlan-driver/fw-api/hw/qca9574/phyrx_he_sig_a_mu_ul.h (revision 5113495b16420b49004c444715d2daae2066e7dc) 
1*5113495bSYour Name /*
2*5113495bSYour Name  * Copyright (c) 2021 The Linux Foundation. All rights reserved.
3*5113495bSYour Name  *
4*5113495bSYour Name  * Permission to use, copy, modify, and/or distribute this software for any
5*5113495bSYour Name  * purpose with or without fee is hereby granted, provided that the above
6*5113495bSYour Name  * copyright notice and this permission notice appear in all copies.
7*5113495bSYour Name  *
8*5113495bSYour Name  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9*5113495bSYour Name  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10*5113495bSYour Name  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11*5113495bSYour Name  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12*5113495bSYour Name  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13*5113495bSYour Name  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14*5113495bSYour Name  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15*5113495bSYour Name  */
16*5113495bSYour Name 
17*5113495bSYour Name // $ATH_LICENSE_HW_HDR_C$
18*5113495bSYour Name //
19*5113495bSYour Name // DO NOT EDIT!  This file is automatically generated
20*5113495bSYour Name //               These definitions are tied to a particular hardware layout
21*5113495bSYour Name 
22*5113495bSYour Name 
23*5113495bSYour Name #ifndef _PHYRX_HE_SIG_A_MU_UL_H_
24*5113495bSYour Name #define _PHYRX_HE_SIG_A_MU_UL_H_
25*5113495bSYour Name #if !defined(__ASSEMBLER__)
26*5113495bSYour Name #endif
27*5113495bSYour Name 
28*5113495bSYour Name #include "he_sig_a_mu_ul_info.h"
29*5113495bSYour Name 
30*5113495bSYour Name // ################ START SUMMARY #################
31*5113495bSYour Name //
32*5113495bSYour Name //	Dword	Fields
33*5113495bSYour Name //	0-1	struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details;
34*5113495bSYour Name //
35*5113495bSYour Name // ################ END SUMMARY #################
36*5113495bSYour Name 
37*5113495bSYour Name #define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_UL 2
38*5113495bSYour Name 
39*5113495bSYour Name struct phyrx_he_sig_a_mu_ul {
40*5113495bSYour Name     struct            he_sig_a_mu_ul_info                       phyrx_he_sig_a_mu_ul_info_details;
41*5113495bSYour Name };
42*5113495bSYour Name 
43*5113495bSYour Name /*
44*5113495bSYour Name 
45*5113495bSYour Name struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details
46*5113495bSYour Name 
47*5113495bSYour Name 			See detailed description of the STRUCT
48*5113495bSYour Name */
49*5113495bSYour Name 
50*5113495bSYour Name 
51*5113495bSYour Name  /* EXTERNAL REFERENCE : struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details */
52*5113495bSYour Name 
53*5113495bSYour Name 
54*5113495bSYour Name /* Description		PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION
55*5113495bSYour Name 
56*5113495bSYour Name 			Indicates whether the transmission is SU PPDU or a
57*5113495bSYour Name 			trigger based UL MU PDDU
58*5113495bSYour Name 
59*5113495bSYour Name 			<enum 0 HE_SIGA_FORMAT_HE_TRIG>
60*5113495bSYour Name 
61*5113495bSYour Name 			<enum 1 HE_SIGA_FORMAT_SU_OR_EXT_SU>
62*5113495bSYour Name 
63*5113495bSYour Name 			<legal all>
64*5113495bSYour Name */
65*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000
66*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0
67*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001
68*5113495bSYour Name 
69*5113495bSYour Name /* Description		PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID
70*5113495bSYour Name 
71*5113495bSYour Name 			BSS color ID
72*5113495bSYour Name 
73*5113495bSYour Name 			<legal all>
74*5113495bSYour Name */
75*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000
76*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1
77*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000007e
78*5113495bSYour Name 
79*5113495bSYour Name /* Description		PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE
80*5113495bSYour Name 
81*5113495bSYour Name 			Spatial reuse
82*5113495bSYour Name 
83*5113495bSYour Name 
84*5113495bSYour Name 
85*5113495bSYour Name 			<legal all>
86*5113495bSYour Name */
87*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000
88*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7
89*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x007fff80
90*5113495bSYour Name 
91*5113495bSYour Name /* Description		PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A
92*5113495bSYour Name 
93*5113495bSYour Name 			Note: spec indicates this shall be set to 1
94*5113495bSYour Name 
95*5113495bSYour Name 			<legal 1>
96*5113495bSYour Name */
97*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
98*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23
99*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x00800000
100*5113495bSYour Name 
101*5113495bSYour Name /* Description		PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW
102*5113495bSYour Name 
103*5113495bSYour Name 			Bandwidth of the PPDU.
104*5113495bSYour Name 
105*5113495bSYour Name 
106*5113495bSYour Name 
107*5113495bSYour Name 			<enum 0 HE_SIG_A_MU_UL_BW20> 20 Mhz
108*5113495bSYour Name 
109*5113495bSYour Name 			<enum 1 HE_SIG_A_MU_UL_BW40> 40 Mhz
110*5113495bSYour Name 
111*5113495bSYour Name 			<enum 2 HE_SIG_A_MU_UL_BW80> 80 Mhz
112*5113495bSYour Name 
113*5113495bSYour Name 			<enum 3 HE_SIG_A_MU_UL_BW160> 160 MHz or 80+80 MHz
114*5113495bSYour Name 
115*5113495bSYour Name 
116*5113495bSYour Name 
117*5113495bSYour Name 			On RX side, Field Used by MAC HW
118*5113495bSYour Name 
119*5113495bSYour Name 			<legal 0-3>
120*5113495bSYour Name */
121*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000
122*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24
123*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x03000000
124*5113495bSYour Name 
125*5113495bSYour Name /* Description		PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B
126*5113495bSYour Name 
127*5113495bSYour Name 			<legal 0>
128*5113495bSYour Name */
129*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
130*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26
131*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000
132*5113495bSYour Name 
133*5113495bSYour Name /* Description		PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION
134*5113495bSYour Name 
135*5113495bSYour Name 			Indicates the remaining time in the current TXOP <legal
136*5113495bSYour Name 			all>
137*5113495bSYour Name */
138*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004
139*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 0
140*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f
141*5113495bSYour Name 
142*5113495bSYour Name /* Description		PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A
143*5113495bSYour Name 
144*5113495bSYour Name 			Set to value indicated in the trigger frame
145*5113495bSYour Name 
146*5113495bSYour Name 			<legal 255>
147*5113495bSYour Name */
148*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
149*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 7
150*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff80
151*5113495bSYour Name 
152*5113495bSYour Name /* Description		PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC
153*5113495bSYour Name 
154*5113495bSYour Name 			CRC for HE-SIG-A contents.
155*5113495bSYour Name 
156*5113495bSYour Name 			This CRC may also cover some fields of L-SIG (TBD)
157*5113495bSYour Name 
158*5113495bSYour Name 			<legal all>
159*5113495bSYour Name */
160*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x00000004
161*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 16
162*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f0000
163*5113495bSYour Name 
164*5113495bSYour Name /* Description		PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL
165*5113495bSYour Name 
166*5113495bSYour Name 			BCC encoding (similar to VHT-SIG-A) with 6 tail bits is
167*5113495bSYour Name 			used
168*5113495bSYour Name 
169*5113495bSYour Name 			<legal 0>
170*5113495bSYour Name */
171*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x00000004
172*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 20
173*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f00000
174*5113495bSYour Name 
175*5113495bSYour Name /* Description		PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B
176*5113495bSYour Name 
177*5113495bSYour Name 			<legal 0>
178*5113495bSYour Name */
179*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004
180*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 26
181*5113495bSYour Name #define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0xfc000000
182*5113495bSYour Name 
183*5113495bSYour Name 
184*5113495bSYour Name #endif // _PHYRX_HE_SIG_A_MU_UL_H_
185