1 /* 2 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 // $ATH_LICENSE_HW_HDR_C$ 18 // 19 // DO NOT EDIT! This file is automatically generated 20 // These definitions are tied to a particular hardware layout 21 22 23 #ifndef _PHYRX_PKT_END_INFO_H_ 24 #define _PHYRX_PKT_END_INFO_H_ 25 #if !defined(__ASSEMBLER__) 26 #endif 27 28 #include "rx_location_info.h" 29 #include "rx_timing_offset_info.h" 30 #include "receive_rssi_info.h" 31 32 // ################ START SUMMARY ################# 33 // 34 // Dword Fields 35 // 0 phy_internal_nap[0], location_info_valid[1], timing_info_valid[2], rssi_info_valid[3], rx_frame_correction_needed[4], frameless_frame_received[5], reserved_0a[11:6], dl_ofdma_info_valid[12], dl_ofdma_ru_start_index[19:13], dl_ofdma_ru_width[26:20], reserved_0b[31:27] 36 // 1 phy_timestamp_1_lower_32[31:0] 37 // 2 phy_timestamp_1_upper_32[31:0] 38 // 3 phy_timestamp_2_lower_32[31:0] 39 // 4 phy_timestamp_2_upper_32[31:0] 40 // 5-13 struct rx_location_info rx_location_info_details; 41 // 14 struct rx_timing_offset_info rx_timing_offset_info_details; 42 // 15-30 struct receive_rssi_info post_rssi_info_details; 43 // 31 phy_sw_status_31_0[31:0] 44 // 32 phy_sw_status_63_32[31:0] 45 // 46 // ################ END SUMMARY ################# 47 48 #define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 33 49 50 struct phyrx_pkt_end_info { 51 uint32_t phy_internal_nap : 1, //[0] 52 location_info_valid : 1, //[1] 53 timing_info_valid : 1, //[2] 54 rssi_info_valid : 1, //[3] 55 rx_frame_correction_needed : 1, //[4] 56 frameless_frame_received : 1, //[5] 57 reserved_0a : 6, //[11:6] 58 dl_ofdma_info_valid : 1, //[12] 59 dl_ofdma_ru_start_index : 7, //[19:13] 60 dl_ofdma_ru_width : 7, //[26:20] 61 reserved_0b : 5; //[31:27] 62 uint32_t phy_timestamp_1_lower_32 : 32; //[31:0] 63 uint32_t phy_timestamp_1_upper_32 : 32; //[31:0] 64 uint32_t phy_timestamp_2_lower_32 : 32; //[31:0] 65 uint32_t phy_timestamp_2_upper_32 : 32; //[31:0] 66 struct rx_location_info rx_location_info_details; 67 struct rx_timing_offset_info rx_timing_offset_info_details; 68 struct receive_rssi_info post_rssi_info_details; 69 uint32_t phy_sw_status_31_0 : 32; //[31:0] 70 uint32_t phy_sw_status_63_32 : 32; //[31:0] 71 }; 72 73 /* 74 75 phy_internal_nap 76 77 When set, PHY RX entered an internal NAP state, as PHY 78 determined that this reception was not destined to this 79 device 80 81 location_info_valid 82 83 Indicates that the RX_LOCATION_INFO structure later on 84 in the TLV contains valid info 85 86 timing_info_valid 87 88 Indicates that the RX_TIMING_OFFSET_INFO structure later 89 on in the TLV contains valid info 90 91 rssi_info_valid 92 93 Indicates that the RECEIVE_RSSI_INFO structure later on 94 in the TLV contains valid info 95 96 rx_frame_correction_needed 97 98 When clear, no action is needed in the MAC. 99 100 101 102 When set, the falling edge of the rx_frame happened 4us 103 too late. MAC will need to compensate for this delay in 104 order to maintain proper SIFS timing and/or not to get 105 de-slotted. 106 107 108 109 PHY uses this for very short 11a frames. 110 111 112 113 When set, PHY will have passed this TLV to the MAC up to 114 8 us into the 'real SIFS' time, and thus within 4us from the 115 falling edge of the rx_frame. 116 117 118 119 <legal all> 120 121 frameless_frame_received 122 123 When set, PHY has received the 'frameless frame' . Can 124 be used in the 'MU-RTS -CTS exchange where CTS reception can 125 be problematic. 126 127 <legal all> 128 129 reserved_0a 130 131 <legal 0> 132 133 dl_ofdma_info_valid 134 135 When set, the following DL_ofdma_... fields are valid. 136 137 It provides the MAC insight into which RU was allocated 138 to this device. 139 140 <legal all> 141 142 dl_ofdma_ru_start_index 143 144 RU index number to which User is assigned 145 146 RU numbering is over the entire BW, starting from 0 and 147 in increasing frequency order and not primary-secondary 148 order 149 150 <legal 0-73> 151 152 dl_ofdma_ru_width 153 154 The size of the RU for this user. 155 156 In units of 1 (26 tone) RU 157 158 <legal 1-74> 159 160 reserved_0b 161 162 <legal 0> 163 164 phy_timestamp_1_lower_32 165 166 TODO PHY: cleanup descriptionThe PHY timestamp in the 167 AMPI of the first rising edge of rx_clear_pri after 168 TX_PHY_DESC. . This field should set to 0 by the PHY and 169 should be updated by the AMPI before being forwarded to the 170 rest of the MAC. This field indicates the lower 32 bits of 171 the timestamp 172 173 phy_timestamp_1_upper_32 174 175 TODO PHY: cleanup description 176 177 The PHY timestamp in the AMPI of the first rising edge 178 of rx_clear_pri after TX_PHY_DESC. This field should set to 179 0 by the PHY and should be updated by the AMPI before being 180 forwarded to the rest of the MAC. This field indicates the 181 upper 32 bits of the timestamp 182 183 phy_timestamp_2_lower_32 184 185 TODO PHY: cleanup description 186 187 The PHY timestamp in the AMPI of the rising edge of 188 rx_clear_pri after RX_RSSI_LEGACY. This field should set to 189 0 by the PHY and should be updated by the AMPI before being 190 forwarded to the rest of the MAC. This field indicates the 191 lower 32 bits of the timestamp 192 193 phy_timestamp_2_upper_32 194 195 TODO PHY: cleanup description 196 197 The PHY timestamp in the AMPI of the rising edge of 198 rx_clear_pri after RX_RSSI_LEGACY. This field should set to 199 0 by the PHY and should be updated by the AMPI before being 200 forwarded to the rest of the MAC. This field indicates the 201 upper 32 bits of the timestamp 202 203 struct rx_location_info rx_location_info_details 204 205 Overview of location related info 206 207 struct rx_timing_offset_info rx_timing_offset_info_details 208 209 Overview of timing offset related info 210 211 struct receive_rssi_info post_rssi_info_details 212 213 Overview of the post-RSSI values. 214 215 phy_sw_status_31_0 216 217 Some PHY micro code status that can be put in here. 218 Details of definition within SW specification 219 220 This field can be used for debugging, FW - SW message 221 exchange, etc. 222 223 It could for example be a pointer to a DDR memory 224 location where PHY FW put some debug info. 225 226 <legal all> 227 228 phy_sw_status_63_32 229 230 Some PHY micro code status that can be put in here. 231 Details of definition within SW specification 232 233 This field can be used for debugging, FW - SW message 234 exchange, etc. 235 236 It could for example be a pointer to a DDR memory 237 location where PHY FW put some debug info. 238 239 <legal all> 240 */ 241 242 243 /* Description PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP 244 245 When set, PHY RX entered an internal NAP state, as PHY 246 determined that this reception was not destined to this 247 device 248 */ 249 #define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_OFFSET 0x00000000 250 #define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_LSB 0 251 #define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_MASK 0x00000001 252 253 /* Description PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID 254 255 Indicates that the RX_LOCATION_INFO structure later on 256 in the TLV contains valid info 257 */ 258 #define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_OFFSET 0x00000000 259 #define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_LSB 1 260 #define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_MASK 0x00000002 261 262 /* Description PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID 263 264 Indicates that the RX_TIMING_OFFSET_INFO structure later 265 on in the TLV contains valid info 266 */ 267 #define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_OFFSET 0x00000000 268 #define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_LSB 2 269 #define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_MASK 0x00000004 270 271 /* Description PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID 272 273 Indicates that the RECEIVE_RSSI_INFO structure later on 274 in the TLV contains valid info 275 */ 276 #define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_OFFSET 0x00000000 277 #define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_LSB 3 278 #define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_MASK 0x00000008 279 280 /* Description PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED 281 282 When clear, no action is needed in the MAC. 283 284 285 286 When set, the falling edge of the rx_frame happened 4us 287 too late. MAC will need to compensate for this delay in 288 order to maintain proper SIFS timing and/or not to get 289 de-slotted. 290 291 292 293 PHY uses this for very short 11a frames. 294 295 296 297 When set, PHY will have passed this TLV to the MAC up to 298 8 us into the 'real SIFS' time, and thus within 4us from the 299 falling edge of the rx_frame. 300 301 302 303 <legal all> 304 */ 305 #define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_OFFSET 0x00000000 306 #define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_LSB 4 307 #define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_MASK 0x00000010 308 309 /* Description PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED 310 311 When set, PHY has received the 'frameless frame' . Can 312 be used in the 'MU-RTS -CTS exchange where CTS reception can 313 be problematic. 314 315 <legal all> 316 */ 317 #define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 318 #define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_LSB 5 319 #define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 320 321 /* Description PHYRX_PKT_END_INFO_0_RESERVED_0A 322 323 <legal 0> 324 */ 325 #define PHYRX_PKT_END_INFO_0_RESERVED_0A_OFFSET 0x00000000 326 #define PHYRX_PKT_END_INFO_0_RESERVED_0A_LSB 6 327 #define PHYRX_PKT_END_INFO_0_RESERVED_0A_MASK 0x00000fc0 328 329 /* Description PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID 330 331 When set, the following DL_ofdma_... fields are valid. 332 333 It provides the MAC insight into which RU was allocated 334 to this device. 335 336 <legal all> 337 */ 338 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_OFFSET 0x00000000 339 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_LSB 12 340 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_MASK 0x00001000 341 342 /* Description PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX 343 344 RU index number to which User is assigned 345 346 RU numbering is over the entire BW, starting from 0 and 347 in increasing frequency order and not primary-secondary 348 order 349 350 <legal 0-73> 351 */ 352 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_OFFSET 0x00000000 353 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_LSB 13 354 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_MASK 0x000fe000 355 356 /* Description PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH 357 358 The size of the RU for this user. 359 360 In units of 1 (26 tone) RU 361 362 <legal 1-74> 363 */ 364 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_OFFSET 0x00000000 365 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_LSB 20 366 #define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_MASK 0x07f00000 367 368 /* Description PHYRX_PKT_END_INFO_0_RESERVED_0B 369 370 <legal 0> 371 */ 372 #define PHYRX_PKT_END_INFO_0_RESERVED_0B_OFFSET 0x00000000 373 #define PHYRX_PKT_END_INFO_0_RESERVED_0B_LSB 27 374 #define PHYRX_PKT_END_INFO_0_RESERVED_0B_MASK 0xf8000000 375 376 /* Description PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32 377 378 TODO PHY: cleanup descriptionThe PHY timestamp in the 379 AMPI of the first rising edge of rx_clear_pri after 380 TX_PHY_DESC. . This field should set to 0 by the PHY and 381 should be updated by the AMPI before being forwarded to the 382 rest of the MAC. This field indicates the lower 32 bits of 383 the timestamp 384 */ 385 #define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 386 #define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_LSB 0 387 #define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff 388 389 /* Description PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32 390 391 TODO PHY: cleanup description 392 393 The PHY timestamp in the AMPI of the first rising edge 394 of rx_clear_pri after TX_PHY_DESC. This field should set to 395 0 by the PHY and should be updated by the AMPI before being 396 forwarded to the rest of the MAC. This field indicates the 397 upper 32 bits of the timestamp 398 */ 399 #define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 400 #define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_LSB 0 401 #define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff 402 403 /* Description PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32 404 405 TODO PHY: cleanup description 406 407 The PHY timestamp in the AMPI of the rising edge of 408 rx_clear_pri after RX_RSSI_LEGACY. This field should set to 409 0 by the PHY and should be updated by the AMPI before being 410 forwarded to the rest of the MAC. This field indicates the 411 lower 32 bits of the timestamp 412 */ 413 #define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c 414 #define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_LSB 0 415 #define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff 416 417 /* Description PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32 418 419 TODO PHY: cleanup description 420 421 The PHY timestamp in the AMPI of the rising edge of 422 rx_clear_pri after RX_RSSI_LEGACY. This field should set to 423 0 by the PHY and should be updated by the AMPI before being 424 forwarded to the rest of the MAC. This field indicates the 425 upper 32 bits of the timestamp 426 */ 427 #define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 428 #define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_LSB 0 429 #define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff 430 431 /* EXTERNAL REFERENCE : struct rx_location_info rx_location_info_details */ 432 433 434 /* Description PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY 435 436 For 20/40/80, this field shows the RTT first arrival 437 correction value computed from L-LTF on the first selected 438 Rx chain 439 440 441 442 For 80+80, this field shows the RTT first arrival 443 correction value computed from L-LTF on pri80 on the 444 selected pri80 Rx chain 445 446 447 448 16 bits, signed 12.4. 12 bits integer to cover -6.4us to 449 6.4us, and 4 bits fraction to cover pri80 and 32x FAC 450 interpolation 451 452 453 454 clock unit is 320MHz 455 456 <legal all> 457 */ 458 #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_OFFSET 0x00000014 459 #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_LSB 0 460 #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_MASK 0x0000ffff 461 462 /* Description PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80 463 464 For 20/40/80, this field shows the RTT first arrival 465 correction value computed from L-LTF on the second selected 466 Rx chain 467 468 469 470 For 80+80, this field shows the RTT first arrival 471 correction value computed from L-LTF on ext80 on the 472 selected ext80 Rx chain 473 474 475 476 16 bits, signed 12.4. 12 bits integer to cover -6.4us to 477 6.4us, and 4 bits fraction to cover ext80 and 32x FAC 478 interpolation 479 480 481 482 clock unit is 320MHz 483 484 <legal all> 485 */ 486 #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_OFFSET 0x00000014 487 #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_LSB 16 488 #define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_MASK 0xffff0000 489 490 /* Description PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT 491 492 For 20/40/80, this field shows the RTT first arrival 493 correction value computed from (V)HT/HE-LTF on the first 494 selected Rx chain 495 496 497 498 For 80+80, this field shows the RTT first arrival 499 correction value computed from (V)HT/HE-LTF on pri80 on the 500 selected pri80 Rx chain 501 502 503 504 16 bits, signed 12.4. 12 bits integer to cover -6.4us to 505 6.4us, and 4 bits fraction to cover pri80 and 32x FAC 506 interpolation 507 508 509 510 clock unit is 320MHz 511 512 <legal all> 513 */ 514 #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_OFFSET 0x00000018 515 #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_LSB 0 516 #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_MASK 0x0000ffff 517 518 /* Description PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80 519 520 For 20/40/80, this field shows the RTT first arrival 521 correction value computed from (V)HT/HE-LTF on the second 522 selected Rx chain 523 524 525 526 For 80+80, this field shows the RTT first arrival 527 correction value computed from (V)HT/HE-LTF on ext80 on the 528 selected ext80 Rx chain 529 530 531 532 16 bits, signed 12.4. 12 bits integer to cover -6.4us to 533 6.4us, and 4 bits fraction to cover ext80 and 32x FAC 534 interpolation 535 536 537 538 clock unit is 320MHz 539 540 <legal all> 541 */ 542 #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_OFFSET 0x00000018 543 #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_LSB 16 544 #define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_MASK 0xffff0000 545 546 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS 547 548 Status of rtt_fac_legacy 549 550 551 552 <enum 0 location_fac_legacy_status_not_valid> 553 554 <enum 1 location_fac_legacy_status_valid> 555 556 <legal all> 557 */ 558 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_OFFSET 0x0000001c 559 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_LSB 0 560 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_MASK 0x00000001 561 562 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS 563 564 Status of rtt_fac_legacy_ext80 565 566 567 568 <enum 0 location_fac_legacy_ext80_status_not_valid> 569 570 <enum 1 location_fac_legacy_ext80_status_valid> 571 572 <legal all> 573 */ 574 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_OFFSET 0x0000001c 575 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_LSB 1 576 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_MASK 0x00000002 577 578 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS 579 580 Status of rtt_fac_vht 581 582 583 584 <enum 0 location_fac_vht_status_not_valid> 585 586 <enum 1 location_fac_vht_status_valid> 587 588 <legal all> 589 */ 590 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_OFFSET 0x0000001c 591 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_LSB 2 592 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_MASK 0x00000004 593 594 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS 595 596 Status of rtt_fac_vht_ext80 597 598 599 600 <enum 0 location_fac_vht_ext80_status_not_valid> 601 602 <enum 1 location_fac_vht_ext80_status_valid> 603 604 <legal all> 605 */ 606 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_OFFSET 0x0000001c 607 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_LSB 3 608 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_MASK 0x00000008 609 610 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS 611 612 To support fine SIFS adjustment, need to provide FAC 613 value @ integer number of 320 MHz clock cycles to MAC. It 614 is from L-LTF if it is a Legacy packet and from (V)HT/HE-LTF 615 if it is a (V)HT/HE packet 616 617 618 619 12 bits, signed, no fractional part 620 621 <legal all> 622 */ 623 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_OFFSET 0x0000001c 624 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_LSB 4 625 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_MASK 0x0000fff0 626 627 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS 628 629 Status of rtt_fac_sifs 630 631 0: not valid 632 633 1: valid and from L-LTF 634 635 2: valid and from (V)HT/HE-LTF 636 637 3: reserved 638 639 <legal 0-2> 640 */ 641 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_OFFSET 0x0000001c 642 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_LSB 16 643 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_MASK 0x00030000 644 645 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS 646 647 Status of channel frequency response dump 648 649 650 651 <enum 0 location_CFR_dump_not_valid> 652 653 <enum 1 location_CFR_dump_valid> 654 655 <legal all> 656 */ 657 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000001c 658 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 18 659 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00040000 660 661 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS 662 663 Status of channel impulse response dump 664 665 666 667 <enum 0 location_CIR_dump_not_valid> 668 669 <enum 1 location_CIR_dump_valid> 670 671 <legal all> 672 */ 673 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000001c 674 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 19 675 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0x00080000 676 677 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE 678 679 Channel dump size. It shows how many tones in CFR in 680 one chain, for example, it will show 52 for Legacy20 and 484 681 for VHT160 682 683 684 685 <legal all> 686 */ 687 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_OFFSET 0x0000001c 688 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_LSB 20 689 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_MASK 0x7ff00000 690 691 /* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE 692 693 Indicator showing if HW IFFT mode or SW IFFT mode 694 695 696 697 <enum 0 location_sw_ifft_mode> 698 699 <enum 1 location_hw_ifft_mode> 700 701 <legal all> 702 */ 703 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000001c 704 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 31 705 #define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x80000000 706 707 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS 708 709 Indicate if BTCF is used to capture the timestamps 710 711 712 713 <enum 0 location_not_BTCF_based_ts> 714 715 <enum 1 location_BTCF_based_ts> 716 717 <legal all> 718 */ 719 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_OFFSET 0x00000020 720 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_LSB 0 721 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_MASK 0x00000001 722 723 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE 724 725 Indicate preamble type 726 727 728 729 <enum 0 location_preamble_type_legacy> 730 731 <enum 1 location_preamble_type_ht> 732 733 <enum 2 location_preamble_type_vht> 734 735 <enum 3 location_preamble_type_he_su_4xltf> 736 737 <enum 4 location_preamble_type_he_su_2xltf> 738 739 <enum 5 location_preamble_type_he_su_1xltf> 740 741 <enum 6 742 location_preamble_type_he_trigger_based_ul_4xltf> 743 744 <enum 7 745 location_preamble_type_he_trigger_based_ul_2xltf> 746 747 <enum 8 748 location_preamble_type_he_trigger_based_ul_1xltf> 749 750 <enum 9 location_preamble_type_he_mu_4xltf> 751 752 <enum 10 location_preamble_type_he_mu_2xltf> 753 754 <enum 11 location_preamble_type_he_mu_1xltf> 755 756 <enum 12 757 location_preamble_type_he_extended_range_su_4xltf> 758 759 <enum 13 760 location_preamble_type_he_extended_range_su_2xltf> 761 762 <enum 14 763 location_preamble_type_he_extended_range_su_1xltf> 764 765 <legal 0-14> 766 */ 767 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x00000020 768 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 1 769 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000003e 770 771 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG 772 773 Indicate the bandwidth of L-LTF 774 775 776 777 <enum 0 location_pkt_bw_20MHz> 778 779 <enum 1 location_pkt_bw_40MHz> 780 781 <enum 2 location_pkt_bw_80MHz> 782 783 <enum 3 location_pkt_bw_160MHz> 784 785 <legal all> 786 */ 787 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x00000020 788 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 6 789 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x000000c0 790 791 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT 792 793 Indicate the bandwidth of (V)HT/HE-LTF 794 795 796 797 <enum 0 location_pkt_bw_20MHz> 798 799 <enum 1 location_pkt_bw_40MHz> 800 801 <enum 2 location_pkt_bw_80MHz> 802 803 <enum 3 location_pkt_bw_160MHz> 804 805 <legal all> 806 */ 807 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x00000020 808 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 8 809 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x00000300 810 811 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE 812 813 Indicate GI (guard interval) type 814 815 816 817 <enum 0 gi_0_8_us > HE related GI. Can also be used 818 for HE 819 820 <enum 1 gi_0_4_us > HE related GI. Can also be used 821 for HE 822 823 <enum 2 gi_1_6_us > HE related GI 824 825 <enum 3 gi_3_2_us > HE related GI 826 827 <legal 0 - 3> 828 */ 829 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x00000020 830 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 10 831 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000c00 832 833 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE 834 835 Bits 0~4 indicate MCS rate, if Legacy, 836 837 0: 48 Mbps, 838 839 1: 24 Mbps, 840 841 2: 12 Mbps, 842 843 3: 6 Mbps, 844 845 4: 54 Mbps, 846 847 5: 36 Mbps, 848 849 6: 18 Mbps, 850 851 7: 9 Mbps, 852 853 854 855 if HT, 0-7: MCS0-MCS7, 856 857 if VHT, 0-9: MCS0-MCS9, 858 859 860 <legal all> 861 */ 862 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x00000020 863 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 12 864 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0x0001f000 865 866 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN 867 868 For 20/40/80, this field shows the first selected Rx 869 chain that is used in HW IFFT mode 870 871 872 873 For 80+80, this field shows the selected pri80 Rx chain 874 that is used in HW IFFT mode 875 876 877 878 <enum 0 location_strongest_chain_is_0> 879 880 <enum 1 location_strongest_chain_is_1> 881 882 <enum 2 location_strongest_chain_is_2> 883 884 <enum 3 location_strongest_chain_is_3> 885 886 <enum 4 location_strongest_chain_is_4> 887 888 <enum 5 location_strongest_chain_is_5> 889 890 <enum 6 location_strongest_chain_is_6> 891 892 <enum 7 location_strongest_chain_is_7> 893 894 <legal all> 895 */ 896 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_OFFSET 0x00000020 897 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_LSB 17 898 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_MASK 0x000e0000 899 900 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80 901 902 For 20/40/80, this field shows the second selected Rx 903 chain that is used in HW IFFT mode 904 905 906 907 For 80+80, this field shows the selected ext80 Rx chain 908 that is used in HW IFFT mode 909 910 911 912 <enum 0 location_strongest_chain_is_0> 913 914 <enum 1 location_strongest_chain_is_1> 915 916 <enum 2 location_strongest_chain_is_2> 917 918 <enum 3 location_strongest_chain_is_3> 919 920 <enum 4 location_strongest_chain_is_4> 921 922 <enum 5 location_strongest_chain_is_5> 923 924 <enum 6 location_strongest_chain_is_6> 925 926 <enum 7 location_strongest_chain_is_7> 927 928 <legal all> 929 */ 930 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_OFFSET 0x00000020 931 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_LSB 20 932 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_MASK 0x00700000 933 934 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK 935 936 Rx chain mask, each bit is a Rx chain 937 938 0: the Rx chain is not used 939 940 1: the Rx chain is used 941 942 Support up to 8 Rx chains 943 944 <legal all> 945 */ 946 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x00000020 947 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 23 948 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x7f800000 949 950 /* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3 951 952 <legal 0> 953 */ 954 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x00000020 955 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 31 956 #define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x80000000 957 958 /* Description PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS 959 960 RX packet start timestamp 961 962 963 964 It reports the time the first L-STF ADC sample arrived 965 at RX antenna 966 967 968 969 clock unit is 480MHz 970 971 <legal all> 972 */ 973 #define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x00000024 974 #define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 0 975 #define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff 976 977 /* Description PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS 978 979 RX packet end timestamp 980 981 982 983 It reports the time the last symbol's last ADC sample 984 arrived at RX antenna 985 986 987 988 clock unit is 480MHz 989 990 <legal all> 991 */ 992 #define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x00000028 993 #define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 0 994 #define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff 995 996 /* Description PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START 997 998 The phase of the SFO of the first symbol's first FFT 999 input sample 1000 1001 1002 1003 12 bits, signed 6.6. 6 bits integer to cover -66.7ns to 1004 66.7ns, and 6 bits fraction to provide a resolution of 1005 0.03ns 1006 1007 1008 1009 clock unit is 480MHz 1010 1011 <legal all> 1012 */ 1013 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_OFFSET 0x0000002c 1014 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_LSB 0 1015 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_MASK 0x00000fff 1016 1017 /* Description PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END 1018 1019 The phase of the SFO of the last symbol's last FFT input 1020 sample 1021 1022 1023 1024 12 bits, signed 6.6. 6 bits integer to cover -66.7ns to 1025 66.7ns, and 6 bits fraction to provide a resolution of 1026 0.03ns 1027 1028 1029 1030 clock unit is 480MHz 1031 1032 <legal all> 1033 */ 1034 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_OFFSET 0x0000002c 1035 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_LSB 12 1036 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_MASK 0x00fff000 1037 1038 /* Description PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8 1039 1040 The high 8 bits of the 40 bits pointer pointed to the 1041 external RTT channel information buffer 1042 1043 1044 1045 8 bits 1046 1047 <legal all> 1048 */ 1049 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000002c 1050 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 24 1051 #define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0xff000000 1052 1053 /* Description PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32 1054 1055 The low 32 bits of the 40 bits pointer pointed to the 1056 external RTT channel information buffer 1057 1058 1059 1060 32 bits 1061 1062 <legal all> 1063 */ 1064 #define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000030 1065 #define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 1066 #define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff 1067 1068 /* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT 1069 1070 CFO measurement. Needed for passive locationing 1071 1072 1073 1074 14 bits, signed 1.13. 13 bits fraction to provide a 1075 resolution of 153 Hz 1076 1077 1078 1079 In units of cycles/800 ns 1080 1081 <legal all> 1082 */ 1083 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x00000034 1084 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0 1085 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x00003fff 1086 1087 /* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD 1088 1089 Channel delay spread measurement. Needed for selecting 1090 GI length 1091 1092 1093 1094 8 bits, unsigned. At 25 ns step. Can represent up to 1095 6375 ns 1096 1097 1098 1099 In units of cycles @ 40 MHz 1100 1101 <legal all> 1102 */ 1103 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_OFFSET 0x00000034 1104 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_LSB 14 1105 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_MASK 0x003fc000 1106 1107 /* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL 1108 1109 Indicate which timing backoff value is used 1110 1111 1112 1113 <enum 0 timing_backoff_low_rssi> 1114 1115 <enum 1 timing_backoff_mid_rssi> 1116 1117 <enum 2 timing_backoff_high_rssi> 1118 1119 <enum 3 reserved> 1120 1121 <legal all> 1122 */ 1123 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000034 1124 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 22 1125 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x00c00000 1126 1127 /* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8 1128 1129 <legal 0> 1130 */ 1131 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_OFFSET 0x00000034 1132 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_LSB 24 1133 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_MASK 0x7f000000 1134 1135 /* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID 1136 1137 <enum 0 rx_location_info_is_not_valid> 1138 1139 <enum 1 rx_location_info_is_valid> 1140 1141 <legal all> 1142 */ 1143 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x00000034 1144 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 31 1145 #define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x80000000 1146 1147 /* EXTERNAL REFERENCE : struct rx_timing_offset_info rx_timing_offset_info_details */ 1148 1149 1150 /* Description PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET 1151 1152 Cumulative reference frequency error at end of RX 1153 1154 <legal all> 1155 */ 1156 #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000038 1157 #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0 1158 #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff 1159 1160 /* Description PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED 1161 1162 <legal 0> 1163 */ 1164 #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x00000038 1165 #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 12 1166 #define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff000 1167 1168 /* EXTERNAL REFERENCE : struct receive_rssi_info post_rssi_info_details */ 1169 1170 1171 /* Description PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0 1172 1173 RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. 1174 1175 Value of 0x80 indicates invalid. 1176 */ 1177 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000003c 1178 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 1179 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff 1180 1181 /* Description PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0 1182 1183 RSSI of RX PPDU on chain 0 of extension 20 MHz 1184 bandwidth. 1185 1186 Value of 0x80 indicates invalid. 1187 */ 1188 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000003c 1189 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 1190 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 1191 1192 /* Description PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0 1193 1194 RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz 1195 bandwidth. 1196 1197 Value of 0x80 indicates invalid. 1198 */ 1199 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000003c 1200 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 1201 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 1202 1203 /* Description PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0 1204 1205 RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz 1206 bandwidth. 1207 1208 Value of 0x80 indicates invalid. 1209 */ 1210 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000003c 1211 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 1212 #define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 1213 1214 /* Description PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0 1215 1216 RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz 1217 bandwidth. 1218 1219 Value of 0x80 indicates invalid. 1220 */ 1221 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000040 1222 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 1223 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff 1224 1225 /* Description PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0 1226 1227 RSSI of RX PPDU on chain 0 of extension 80, low-high 20 1228 MHz bandwidth. 1229 1230 Value of 0x80 indicates invalid. 1231 */ 1232 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000040 1233 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 1234 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 1235 1236 /* Description PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0 1237 1238 RSSI of RX PPDU on chain 0 of extension 80, high-low 20 1239 MHz bandwidth. 1240 1241 Value of 0x80 indicates invalid. 1242 */ 1243 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000040 1244 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 1245 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 1246 1247 /* Description PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0 1248 1249 RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz 1250 bandwidth. 1251 1252 Value of 0x80 indicates invalid. 1253 */ 1254 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000040 1255 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 1256 #define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 1257 1258 /* Description PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1 1259 1260 RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. 1261 1262 Value of 0x80 indicates invalid. 1263 */ 1264 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000044 1265 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 1266 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff 1267 1268 /* Description PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1 1269 1270 RSSI of RX PPDU on chain 1 of extension 20 MHz 1271 bandwidth. 1272 1273 Value of 0x80 indicates invalid. 1274 */ 1275 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000044 1276 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 1277 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 1278 1279 /* Description PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1 1280 1281 RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz 1282 bandwidth. 1283 1284 Value of 0x80 indicates invalid. 1285 */ 1286 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000044 1287 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 1288 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 1289 1290 /* Description PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1 1291 1292 RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz 1293 bandwidth. 1294 1295 Value of 0x80 indicates invalid. 1296 */ 1297 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000044 1298 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 1299 #define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 1300 1301 /* Description PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1 1302 1303 RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz 1304 bandwidth. 1305 1306 Value of 0x80 indicates invalid. 1307 */ 1308 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000048 1309 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 1310 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff 1311 1312 /* Description PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1 1313 1314 RSSI of RX PPDU on chain 1 of extension 80, low-high 20 1315 MHz bandwidth. 1316 1317 Value of 0x80 indicates invalid. 1318 */ 1319 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000048 1320 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 1321 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 1322 1323 /* Description PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1 1324 1325 RSSI of RX PPDU on chain 1 of extension 80, high-low 20 1326 MHz bandwidth. 1327 1328 Value of 0x80 indicates invalid. 1329 */ 1330 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000048 1331 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 1332 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 1333 1334 /* Description PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1 1335 1336 RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz 1337 bandwidth. 1338 1339 Value of 0x80 indicates invalid. 1340 */ 1341 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000048 1342 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 1343 #define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 1344 1345 /* Description PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2 1346 1347 RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. 1348 1349 Value of 0x80 indicates invalid. 1350 */ 1351 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000004c 1352 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 1353 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff 1354 1355 /* Description PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2 1356 1357 RSSI of RX PPDU on chain 2 of extension 20 MHz 1358 bandwidth. 1359 1360 Value of 0x80 indicates invalid. 1361 */ 1362 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000004c 1363 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 1364 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 1365 1366 /* Description PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2 1367 1368 RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz 1369 bandwidth. 1370 1371 Value of 0x80 indicates invalid. 1372 */ 1373 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000004c 1374 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 1375 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 1376 1377 /* Description PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2 1378 1379 RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz 1380 bandwidth. 1381 1382 Value of 0x80 indicates invalid. 1383 */ 1384 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000004c 1385 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 1386 #define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 1387 1388 /* Description PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2 1389 1390 RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz 1391 bandwidth. 1392 1393 Value of 0x80 indicates invalid. 1394 */ 1395 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000050 1396 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 1397 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff 1398 1399 /* Description PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2 1400 1401 RSSI of RX PPDU on chain 2 of extension 80, low-high 20 1402 MHz bandwidth. 1403 1404 Value of 0x80 indicates invalid. 1405 */ 1406 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000050 1407 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 1408 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 1409 1410 /* Description PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2 1411 1412 RSSI of RX PPDU on chain 2 of extension 80, high-low 20 1413 MHz bandwidth. 1414 1415 Value of 0x80 indicates invalid. 1416 */ 1417 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000050 1418 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 1419 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 1420 1421 /* Description PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2 1422 1423 RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz 1424 bandwidth. 1425 1426 Value of 0x80 indicates invalid. 1427 */ 1428 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000050 1429 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 1430 #define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 1431 1432 /* Description PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3 1433 1434 RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. 1435 1436 Value of 0x80 indicates invalid. 1437 */ 1438 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000054 1439 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 1440 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff 1441 1442 /* Description PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3 1443 1444 RSSI of RX PPDU on chain 3 of extension 20 MHz 1445 bandwidth. 1446 1447 Value of 0x80 indicates invalid. 1448 */ 1449 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000054 1450 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 1451 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 1452 1453 /* Description PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3 1454 1455 RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz 1456 bandwidth. 1457 1458 Value of 0x80 indicates invalid. 1459 */ 1460 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000054 1461 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 1462 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 1463 1464 /* Description PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3 1465 1466 RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz 1467 bandwidth. 1468 1469 Value of 0x80 indicates invalid. 1470 */ 1471 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000054 1472 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 1473 #define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 1474 1475 /* Description PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3 1476 1477 RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz 1478 bandwidth. 1479 1480 Value of 0x80 indicates invalid. 1481 */ 1482 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000058 1483 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 1484 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff 1485 1486 /* Description PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3 1487 1488 RSSI of RX PPDU on chain 3 of extension 80, low-high 20 1489 MHz bandwidth. 1490 1491 Value of 0x80 indicates invalid. 1492 */ 1493 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000058 1494 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 1495 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 1496 1497 /* Description PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3 1498 1499 RSSI of RX PPDU on chain 3 of extension 80, high-low 20 1500 MHz bandwidth. 1501 1502 Value of 0x80 indicates invalid. 1503 */ 1504 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000058 1505 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 1506 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 1507 1508 /* Description PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3 1509 1510 RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz 1511 bandwidth. 1512 1513 Value of 0x80 indicates invalid. 1514 */ 1515 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000058 1516 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 1517 #define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 1518 1519 /* Description PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4 1520 1521 RSSI of RX PPDU on chain 4 of primary 20 MHz bandwidth. 1522 1523 Value of 0x80 indicates invalid. 1524 */ 1525 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000005c 1526 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0 1527 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff 1528 1529 /* Description PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4 1530 1531 RSSI of RX PPDU on chain 4 of extension 20 MHz 1532 bandwidth. 1533 1534 Value of 0x80 indicates invalid. 1535 */ 1536 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000005c 1537 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8 1538 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00 1539 1540 /* Description PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4 1541 1542 RSSI of RX PPDU on chain 4 of extension 40, low 20 MHz 1543 bandwidth. 1544 1545 Value of 0x80 indicates invalid. 1546 */ 1547 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000005c 1548 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16 1549 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000 1550 1551 /* Description PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4 1552 1553 RSSI of RX PPDU on chain 4 of extension 40, high 20 MHz 1554 bandwidth. 1555 1556 Value of 0x80 indicates invalid. 1557 */ 1558 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000005c 1559 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24 1560 #define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000 1561 1562 /* Description PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4 1563 1564 RSSI of RX PPDU on chain 4 of extension 80, low 20 MHz 1565 bandwidth. 1566 1567 Value of 0x80 indicates invalid. 1568 */ 1569 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000060 1570 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0 1571 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff 1572 1573 /* Description PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4 1574 1575 RSSI of RX PPDU on chain 4 of extension 80, low-high 20 1576 MHz bandwidth. 1577 1578 Value of 0x80 indicates invalid. 1579 */ 1580 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000060 1581 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8 1582 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00 1583 1584 /* Description PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4 1585 1586 RSSI of RX PPDU on chain 4 of extension 80, high-low 20 1587 MHz bandwidth. 1588 1589 Value of 0x80 indicates invalid. 1590 */ 1591 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000060 1592 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16 1593 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000 1594 1595 /* Description PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4 1596 1597 RSSI of RX PPDU on chain 4 of extension 80, high 20 MHz 1598 bandwidth. 1599 1600 Value of 0x80 indicates invalid. 1601 */ 1602 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000060 1603 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24 1604 #define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000 1605 1606 /* Description PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5 1607 1608 RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. 1609 1610 Value of 0x80 indicates invalid. 1611 */ 1612 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000064 1613 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0 1614 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff 1615 1616 /* Description PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5 1617 1618 RSSI of RX PPDU on chain 5 of extension 20 MHz 1619 bandwidth. 1620 1621 Value of 0x80 indicates invalid. 1622 */ 1623 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000064 1624 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8 1625 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00 1626 1627 /* Description PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5 1628 1629 RSSI of RX PPDU on chain 5 of extension 40, low 20 MHz 1630 bandwidth. 1631 1632 Value of 0x80 indicates invalid. 1633 */ 1634 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000064 1635 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16 1636 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000 1637 1638 /* Description PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5 1639 1640 RSSI of RX PPDU on chain 5 of extension 40, high 20 MHz 1641 bandwidth. 1642 1643 Value of 0x80 indicates invalid. 1644 */ 1645 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000064 1646 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24 1647 #define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000 1648 1649 /* Description PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5 1650 1651 RSSI of RX PPDU on chain 5 of extension 80, low 20 MHz 1652 bandwidth. 1653 1654 Value of 0x80 indicates invalid. 1655 */ 1656 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000068 1657 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0 1658 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff 1659 1660 /* Description PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5 1661 1662 RSSI of RX PPDU on chain 5 of extension 80, low-high 20 1663 MHz bandwidth. 1664 1665 Value of 0x80 indicates invalid. 1666 */ 1667 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000068 1668 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8 1669 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00 1670 1671 /* Description PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5 1672 1673 RSSI of RX PPDU on chain 5 of extension 80, high-low 20 1674 MHz bandwidth. 1675 1676 Value of 0x80 indicates invalid. 1677 */ 1678 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000068 1679 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16 1680 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000 1681 1682 /* Description PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5 1683 1684 RSSI of RX PPDU on chain 5 of extension 80, high 20 MHz 1685 bandwidth. 1686 1687 Value of 0x80 indicates invalid. 1688 */ 1689 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000068 1690 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24 1691 #define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000 1692 1693 /* Description PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6 1694 1695 RSSI of RX PPDU on chain 6 of primary 20 MHz bandwidth. 1696 1697 Value of 0x80 indicates invalid. 1698 */ 1699 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000006c 1700 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0 1701 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff 1702 1703 /* Description PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6 1704 1705 RSSI of RX PPDU on chain 6 of extension 20 MHz 1706 bandwidth. 1707 1708 Value of 0x80 indicates invalid. 1709 */ 1710 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000006c 1711 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8 1712 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00 1713 1714 /* Description PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6 1715 1716 RSSI of RX PPDU on chain 6 of extension 40, low 20 MHz 1717 bandwidth. 1718 1719 Value of 0x80 indicates invalid. 1720 */ 1721 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000006c 1722 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16 1723 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000 1724 1725 /* Description PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6 1726 1727 RSSI of RX PPDU on chain 6 of extension 40, high 20 MHz 1728 bandwidth. 1729 1730 Value of 0x80 indicates invalid. 1731 */ 1732 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000006c 1733 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24 1734 #define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000 1735 1736 /* Description PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6 1737 1738 RSSI of RX PPDU on chain 6 of extension 80, low 20 MHz 1739 bandwidth. 1740 1741 Value of 0x80 indicates invalid. 1742 */ 1743 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000070 1744 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0 1745 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff 1746 1747 /* Description PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6 1748 1749 RSSI of RX PPDU on chain 6 of extension 80, low-high 20 1750 MHz bandwidth. 1751 1752 Value of 0x80 indicates invalid. 1753 */ 1754 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000070 1755 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8 1756 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00 1757 1758 /* Description PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6 1759 1760 RSSI of RX PPDU on chain 6 of extension 80, high-low 20 1761 MHz bandwidth. 1762 1763 Value of 0x80 indicates invalid. 1764 */ 1765 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000070 1766 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16 1767 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000 1768 1769 /* Description PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6 1770 1771 RSSI of RX PPDU on chain 6 of extension 80, high 20 MHz 1772 bandwidth. 1773 1774 Value of 0x80 indicates invalid. 1775 */ 1776 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000070 1777 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24 1778 #define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000 1779 1780 /* Description PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7 1781 1782 RSSI of RX PPDU on chain 7 of primary 20 MHz bandwidth. 1783 1784 Value of 0x80 indicates invalid. 1785 */ 1786 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000074 1787 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0 1788 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff 1789 1790 /* Description PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7 1791 1792 RSSI of RX PPDU on chain 7 of extension 20 MHz 1793 bandwidth. 1794 1795 Value of 0x80 indicates invalid. 1796 */ 1797 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000074 1798 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8 1799 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00 1800 1801 /* Description PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7 1802 1803 RSSI of RX PPDU on chain 7 of extension 40, low 20 MHz 1804 bandwidth. 1805 1806 Value of 0x80 indicates invalid. 1807 */ 1808 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000074 1809 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16 1810 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000 1811 1812 /* Description PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7 1813 1814 RSSI of RX PPDU on chain 7 of extension 40, high 20 MHz 1815 bandwidth. 1816 1817 Value of 0x80 indicates invalid. 1818 */ 1819 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000074 1820 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24 1821 #define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000 1822 1823 /* Description PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7 1824 1825 RSSI of RX PPDU on chain 7 of extension 80, low 20 MHz 1826 bandwidth. 1827 1828 Value of 0x80 indicates invalid. 1829 */ 1830 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000078 1831 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0 1832 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff 1833 1834 /* Description PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7 1835 1836 RSSI of RX PPDU on chain 7 of extension 80, low-high 20 1837 MHz bandwidth. 1838 1839 Value of 0x80 indicates invalid. 1840 */ 1841 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000078 1842 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8 1843 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00 1844 1845 /* Description PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7 1846 1847 RSSI of RX PPDU on chain 7 of extension 80, high-low 20 1848 MHz bandwidth. 1849 1850 Value of 0x80 indicates invalid. 1851 */ 1852 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000078 1853 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16 1854 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000 1855 1856 /* Description PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7 1857 1858 RSSI of RX PPDU on chain 7 of extension 80, high 20 MHz 1859 bandwidth. 1860 1861 Value of 0x80 indicates invalid. 1862 */ 1863 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000078 1864 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24 1865 #define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000 1866 1867 /* Description PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0 1868 1869 Some PHY micro code status that can be put in here. 1870 Details of definition within SW specification 1871 1872 This field can be used for debugging, FW - SW message 1873 exchange, etc. 1874 1875 It could for example be a pointer to a DDR memory 1876 location where PHY FW put some debug info. 1877 1878 <legal all> 1879 */ 1880 #define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_OFFSET 0x0000007c 1881 #define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_LSB 0 1882 #define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_MASK 0xffffffff 1883 1884 /* Description PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32 1885 1886 Some PHY micro code status that can be put in here. 1887 Details of definition within SW specification 1888 1889 This field can be used for debugging, FW - SW message 1890 exchange, etc. 1891 1892 It could for example be a pointer to a DDR memory 1893 location where PHY FW put some debug info. 1894 1895 <legal all> 1896 */ 1897 #define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_OFFSET 0x00000080 1898 #define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_LSB 0 1899 #define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_MASK 0xffffffff 1900 1901 1902 #endif // _PHYRX_PKT_END_INFO_H_ 1903