1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any 5*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above 6*5113495bSYour Name * copyright notice and this permission notice appear in all copies. 7*5113495bSYour Name * 8*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*5113495bSYour Name */ 16*5113495bSYour Name 17*5113495bSYour Name // $ATH_LICENSE_HW_HDR_C$ 18*5113495bSYour Name // 19*5113495bSYour Name // DO NOT EDIT! This file is automatically generated 20*5113495bSYour Name // These definitions are tied to a particular hardware layout 21*5113495bSYour Name 22*5113495bSYour Name 23*5113495bSYour Name #ifndef _RX_MPDU_END_H_ 24*5113495bSYour Name #define _RX_MPDU_END_H_ 25*5113495bSYour Name #if !defined(__ASSEMBLER__) 26*5113495bSYour Name #endif 27*5113495bSYour Name 28*5113495bSYour Name 29*5113495bSYour Name // ################ START SUMMARY ################# 30*5113495bSYour Name // 31*5113495bSYour Name // Dword Fields 32*5113495bSYour Name // 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16] 33*5113495bSYour Name // 1 reserved_1a[10:0], unsup_ktype_short_frame[11], rx_in_tx_decrypt_byp[12], overflow_err[13], mpdu_length_err[14], tkip_mic_err[15], decrypt_err[16], unencrypted_frame_err[17], pn_fields_contain_valid_info[18], fcs_err[19], msdu_length_err[20], rxdma0_destination_ring[22:21], rxdma1_destination_ring[24:23], decrypt_status_code[27:25], rx_bitmap_not_updated[28], reserved_1b[31:29] 34*5113495bSYour Name // 35*5113495bSYour Name // ################ END SUMMARY ################# 36*5113495bSYour Name 37*5113495bSYour Name #define NUM_OF_DWORDS_RX_MPDU_END 2 38*5113495bSYour Name 39*5113495bSYour Name struct rx_mpdu_end { 40*5113495bSYour Name uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] 41*5113495bSYour Name sw_frame_group_id : 7, //[8:2] 42*5113495bSYour Name reserved_0 : 7, //[15:9] 43*5113495bSYour Name phy_ppdu_id : 16; //[31:16] 44*5113495bSYour Name uint32_t reserved_1a : 11, //[10:0] 45*5113495bSYour Name unsup_ktype_short_frame : 1, //[11] 46*5113495bSYour Name rx_in_tx_decrypt_byp : 1, //[12] 47*5113495bSYour Name overflow_err : 1, //[13] 48*5113495bSYour Name mpdu_length_err : 1, //[14] 49*5113495bSYour Name tkip_mic_err : 1, //[15] 50*5113495bSYour Name decrypt_err : 1, //[16] 51*5113495bSYour Name unencrypted_frame_err : 1, //[17] 52*5113495bSYour Name pn_fields_contain_valid_info : 1, //[18] 53*5113495bSYour Name fcs_err : 1, //[19] 54*5113495bSYour Name msdu_length_err : 1, //[20] 55*5113495bSYour Name rxdma0_destination_ring : 2, //[22:21] 56*5113495bSYour Name rxdma1_destination_ring : 2, //[24:23] 57*5113495bSYour Name decrypt_status_code : 3, //[27:25] 58*5113495bSYour Name rx_bitmap_not_updated : 1, //[28] 59*5113495bSYour Name reserved_1b : 3; //[31:29] 60*5113495bSYour Name }; 61*5113495bSYour Name 62*5113495bSYour Name /* 63*5113495bSYour Name 64*5113495bSYour Name rxpcu_mpdu_filter_in_category 65*5113495bSYour Name 66*5113495bSYour Name Field indicates what the reason was that this MPDU frame 67*5113495bSYour Name was allowed to come into the receive path by RXPCU 68*5113495bSYour Name 69*5113495bSYour Name <enum 0 rxpcu_filter_pass> This MPDU passed the normal 70*5113495bSYour Name frame filter programming of rxpcu 71*5113495bSYour Name 72*5113495bSYour Name <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 73*5113495bSYour Name regular frame filter and would have been dropped, were it 74*5113495bSYour Name not for the frame fitting into the 'monitor_client' 75*5113495bSYour Name category. 76*5113495bSYour Name 77*5113495bSYour Name <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 78*5113495bSYour Name regular frame filter and also did not pass the 79*5113495bSYour Name rxpcu_monitor_client filter. It would have been dropped 80*5113495bSYour Name accept that it did pass the 'monitor_other' category. 81*5113495bSYour Name 82*5113495bSYour Name <legal 0-2> 83*5113495bSYour Name 84*5113495bSYour Name sw_frame_group_id 85*5113495bSYour Name 86*5113495bSYour Name SW processes frames based on certain classifications. 87*5113495bSYour Name This field indicates to what sw classification this MPDU is 88*5113495bSYour Name mapped. 89*5113495bSYour Name 90*5113495bSYour Name The classification is given in priority order 91*5113495bSYour Name 92*5113495bSYour Name 93*5113495bSYour Name 94*5113495bSYour Name <enum 0 sw_frame_group_NDP_frame> 95*5113495bSYour Name 96*5113495bSYour Name 97*5113495bSYour Name 98*5113495bSYour Name <enum 1 sw_frame_group_Multicast_data> 99*5113495bSYour Name 100*5113495bSYour Name <enum 2 sw_frame_group_Unicast_data> 101*5113495bSYour Name 102*5113495bSYour Name <enum 3 sw_frame_group_Null_data > This includes mpdus 103*5113495bSYour Name of type Data Null as well as QoS Data Null 104*5113495bSYour Name 105*5113495bSYour Name 106*5113495bSYour Name 107*5113495bSYour Name <enum 4 sw_frame_group_mgmt_0000 > 108*5113495bSYour Name 109*5113495bSYour Name <enum 5 sw_frame_group_mgmt_0001 > 110*5113495bSYour Name 111*5113495bSYour Name <enum 6 sw_frame_group_mgmt_0010 > 112*5113495bSYour Name 113*5113495bSYour Name <enum 7 sw_frame_group_mgmt_0011 > 114*5113495bSYour Name 115*5113495bSYour Name <enum 8 sw_frame_group_mgmt_0100 > 116*5113495bSYour Name 117*5113495bSYour Name <enum 9 sw_frame_group_mgmt_0101 > 118*5113495bSYour Name 119*5113495bSYour Name <enum 10 sw_frame_group_mgmt_0110 > 120*5113495bSYour Name 121*5113495bSYour Name <enum 11 sw_frame_group_mgmt_0111 > 122*5113495bSYour Name 123*5113495bSYour Name <enum 12 sw_frame_group_mgmt_1000 > 124*5113495bSYour Name 125*5113495bSYour Name <enum 13 sw_frame_group_mgmt_1001 > 126*5113495bSYour Name 127*5113495bSYour Name <enum 14 sw_frame_group_mgmt_1010 > 128*5113495bSYour Name 129*5113495bSYour Name <enum 15 sw_frame_group_mgmt_1011 > 130*5113495bSYour Name 131*5113495bSYour Name <enum 16 sw_frame_group_mgmt_1100 > 132*5113495bSYour Name 133*5113495bSYour Name <enum 17 sw_frame_group_mgmt_1101 > 134*5113495bSYour Name 135*5113495bSYour Name <enum 18 sw_frame_group_mgmt_1110 > 136*5113495bSYour Name 137*5113495bSYour Name <enum 19 sw_frame_group_mgmt_1111 > 138*5113495bSYour Name 139*5113495bSYour Name 140*5113495bSYour Name 141*5113495bSYour Name <enum 20 sw_frame_group_ctrl_0000 > 142*5113495bSYour Name 143*5113495bSYour Name <enum 21 sw_frame_group_ctrl_0001 > 144*5113495bSYour Name 145*5113495bSYour Name <enum 22 sw_frame_group_ctrl_0010 > 146*5113495bSYour Name 147*5113495bSYour Name <enum 23 sw_frame_group_ctrl_0011 > 148*5113495bSYour Name 149*5113495bSYour Name <enum 24 sw_frame_group_ctrl_0100 > 150*5113495bSYour Name 151*5113495bSYour Name <enum 25 sw_frame_group_ctrl_0101 > 152*5113495bSYour Name 153*5113495bSYour Name <enum 26 sw_frame_group_ctrl_0110 > 154*5113495bSYour Name 155*5113495bSYour Name <enum 27 sw_frame_group_ctrl_0111 > 156*5113495bSYour Name 157*5113495bSYour Name <enum 28 sw_frame_group_ctrl_1000 > 158*5113495bSYour Name 159*5113495bSYour Name <enum 29 sw_frame_group_ctrl_1001 > 160*5113495bSYour Name 161*5113495bSYour Name <enum 30 sw_frame_group_ctrl_1010 > 162*5113495bSYour Name 163*5113495bSYour Name <enum 31 sw_frame_group_ctrl_1011 > 164*5113495bSYour Name 165*5113495bSYour Name <enum 32 sw_frame_group_ctrl_1100 > 166*5113495bSYour Name 167*5113495bSYour Name <enum 33 sw_frame_group_ctrl_1101 > 168*5113495bSYour Name 169*5113495bSYour Name <enum 34 sw_frame_group_ctrl_1110 > 170*5113495bSYour Name 171*5113495bSYour Name <enum 35 sw_frame_group_ctrl_1111 > 172*5113495bSYour Name 173*5113495bSYour Name 174*5113495bSYour Name 175*5113495bSYour Name <enum 36 sw_frame_group_unsupported> This covers type 3 176*5113495bSYour Name and protocol version != 0 177*5113495bSYour Name 178*5113495bSYour Name 179*5113495bSYour Name 180*5113495bSYour Name 181*5113495bSYour Name 182*5113495bSYour Name 183*5113495bSYour Name <legal 0-37> 184*5113495bSYour Name 185*5113495bSYour Name reserved_0 186*5113495bSYour Name 187*5113495bSYour Name <legal 0> 188*5113495bSYour Name 189*5113495bSYour Name phy_ppdu_id 190*5113495bSYour Name 191*5113495bSYour Name A ppdu counter value that PHY increments for every PPDU 192*5113495bSYour Name received. The counter value wraps around 193*5113495bSYour Name 194*5113495bSYour Name <legal all> 195*5113495bSYour Name 196*5113495bSYour Name reserved_1a 197*5113495bSYour Name 198*5113495bSYour Name <legal 0> 199*5113495bSYour Name 200*5113495bSYour Name unsup_ktype_short_frame 201*5113495bSYour Name 202*5113495bSYour Name This bit will be '1' when WEP or TKIP or WAPI key type 203*5113495bSYour Name is received for 11ah short frame. Crypto will bypass the 204*5113495bSYour Name received packet without decryption to RxOLE after setting 205*5113495bSYour Name this bit. 206*5113495bSYour Name 207*5113495bSYour Name rx_in_tx_decrypt_byp 208*5113495bSYour Name 209*5113495bSYour Name Indicates that RX packet is not decrypted as Crypto is 210*5113495bSYour Name busy with TX packet processing. 211*5113495bSYour Name 212*5113495bSYour Name overflow_err 213*5113495bSYour Name 214*5113495bSYour Name RXPCU Receive FIFO ran out of space to receive the full 215*5113495bSYour Name MPDU. Therefor this MPDU is terminated early and is thus 216*5113495bSYour Name corrupted. 217*5113495bSYour Name 218*5113495bSYour Name 219*5113495bSYour Name 220*5113495bSYour Name This MPDU will not be ACKed. 221*5113495bSYour Name 222*5113495bSYour Name RXPCU might still be able to correctly receive the 223*5113495bSYour Name following MPDUs in the PPDU if enough fifo space became 224*5113495bSYour Name available in time 225*5113495bSYour Name 226*5113495bSYour Name mpdu_length_err 227*5113495bSYour Name 228*5113495bSYour Name Set by RXPCU if the expected MPDU length does not 229*5113495bSYour Name correspond with the actually received number of bytes in the 230*5113495bSYour Name MPDU. 231*5113495bSYour Name 232*5113495bSYour Name tkip_mic_err 233*5113495bSYour Name 234*5113495bSYour Name Set by RX CRYPTO when CRYPTO detected a TKIP MIC error 235*5113495bSYour Name for this MPDU 236*5113495bSYour Name 237*5113495bSYour Name decrypt_err 238*5113495bSYour Name 239*5113495bSYour Name Set by RX CRYPTO when CRYPTO detected a decrypt error 240*5113495bSYour Name for this MPDU or CRYPTO received an encrypted frame, but did 241*5113495bSYour Name not get a valid corresponding key id in the peer entry. 242*5113495bSYour Name 243*5113495bSYour Name unencrypted_frame_err 244*5113495bSYour Name 245*5113495bSYour Name Set by RX CRYPTO when CRYPTO detected an unencrypted 246*5113495bSYour Name frame while in the peer entry field 247*5113495bSYour Name 'All_frames_shall_be_encrypted' is set. 248*5113495bSYour Name 249*5113495bSYour Name pn_fields_contain_valid_info 250*5113495bSYour Name 251*5113495bSYour Name Set by RX CRYPTO to indicate that there is a valid PN 252*5113495bSYour Name field present in this MPDU 253*5113495bSYour Name 254*5113495bSYour Name fcs_err 255*5113495bSYour Name 256*5113495bSYour Name Set by RXPCU when there is an FCS error detected for 257*5113495bSYour Name this MPDU 258*5113495bSYour Name 259*5113495bSYour Name NOTE that when this field is set, all other (error) 260*5113495bSYour Name field settings should be ignored as modules could have made 261*5113495bSYour Name wrong decisions based on the corrupted data. 262*5113495bSYour Name 263*5113495bSYour Name msdu_length_err 264*5113495bSYour Name 265*5113495bSYour Name Set by RXOLE when there is an msdu length error detected 266*5113495bSYour Name in at least 1 of the MSDUs embedded within the MPDU 267*5113495bSYour Name 268*5113495bSYour Name rxdma0_destination_ring 269*5113495bSYour Name 270*5113495bSYour Name The ring to which RXDMA0 shall push the frame, assuming 271*5113495bSYour Name no MPDU level errors are detected. In case of MPDU level 272*5113495bSYour Name errors, RXDMA0 might change the RXDMA0 destination 273*5113495bSYour Name 274*5113495bSYour Name 275*5113495bSYour Name 276*5113495bSYour Name <enum 0 rxdma_release_ring > RXDMA0 shall push the 277*5113495bSYour Name frame to the Release ring. Effectively this means the frame 278*5113495bSYour Name needs to be dropped. 279*5113495bSYour Name 280*5113495bSYour Name 281*5113495bSYour Name 282*5113495bSYour Name <enum 1 rxdma2fw_ring > RXDMA0 shall push the frame to 283*5113495bSYour Name the FW ring 284*5113495bSYour Name 285*5113495bSYour Name 286*5113495bSYour Name 287*5113495bSYour Name <enum 2 rxdma2sw_ring > RXDMA0 shall push the frame to 288*5113495bSYour Name the SW ring 289*5113495bSYour Name 290*5113495bSYour Name 291*5113495bSYour Name 292*5113495bSYour Name <enum 3 rxdma2reo_ring > RXDMA0 shall push the frame 293*5113495bSYour Name to the REO entrance ring 294*5113495bSYour Name 295*5113495bSYour Name 296*5113495bSYour Name 297*5113495bSYour Name <legal all> 298*5113495bSYour Name 299*5113495bSYour Name rxdma1_destination_ring 300*5113495bSYour Name 301*5113495bSYour Name The ring to which RXDMA1 shall push the frame, assuming 302*5113495bSYour Name no MPDU level errors are detected. In case of MPDU level 303*5113495bSYour Name errors, RXDMA1 might change the RXDMA destination 304*5113495bSYour Name 305*5113495bSYour Name 306*5113495bSYour Name 307*5113495bSYour Name <enum 0 rxdma_release_ring > RXDMA1 shall push the 308*5113495bSYour Name frame to the Release ring. Effectively this means the frame 309*5113495bSYour Name needs to be dropped. 310*5113495bSYour Name 311*5113495bSYour Name 312*5113495bSYour Name 313*5113495bSYour Name <enum 1 rxdma2fw_ring > RXDMA1 shall push the frame to 314*5113495bSYour Name the FW ring 315*5113495bSYour Name 316*5113495bSYour Name 317*5113495bSYour Name 318*5113495bSYour Name <enum 2 rxdma2sw_ring > RXDMA1 shall push the frame to 319*5113495bSYour Name the SW ring 320*5113495bSYour Name 321*5113495bSYour Name 322*5113495bSYour Name 323*5113495bSYour Name <enum 3 rxdma2reo_ring > RXDMA1 shall push the frame 324*5113495bSYour Name to the REO entrance ring 325*5113495bSYour Name 326*5113495bSYour Name 327*5113495bSYour Name 328*5113495bSYour Name <legal all> 329*5113495bSYour Name 330*5113495bSYour Name decrypt_status_code 331*5113495bSYour Name 332*5113495bSYour Name Field provides insight into the decryption performed 333*5113495bSYour Name 334*5113495bSYour Name 335*5113495bSYour Name 336*5113495bSYour Name <enum 0 decrypt_ok> Frame had protection enabled and 337*5113495bSYour Name decrypted properly 338*5113495bSYour Name 339*5113495bSYour Name <enum 1 decrypt_unprotected_frame > Frame is unprotected 340*5113495bSYour Name and hence bypassed 341*5113495bSYour Name 342*5113495bSYour Name <enum 2 decrypt_data_err > Frame has protection enabled 343*5113495bSYour Name and could not be properly decrypted due to MIC/ICV mismatch 344*5113495bSYour Name etc. 345*5113495bSYour Name 346*5113495bSYour Name <enum 3 decrypt_key_invalid > Frame has protection 347*5113495bSYour Name enabled but the key that was required to decrypt this frame 348*5113495bSYour Name was not valid 349*5113495bSYour Name 350*5113495bSYour Name <enum 4 decrypt_peer_entry_invalid > Frame has 351*5113495bSYour Name protection enabled but the key that was required to decrypt 352*5113495bSYour Name this frame was not valid 353*5113495bSYour Name 354*5113495bSYour Name <enum 5 decrypt_other > Reserved for other indications 355*5113495bSYour Name 356*5113495bSYour Name 357*5113495bSYour Name 358*5113495bSYour Name <legal 0 - 5> 359*5113495bSYour Name 360*5113495bSYour Name rx_bitmap_not_updated 361*5113495bSYour Name 362*5113495bSYour Name Frame is received, but RXPCU could not update the 363*5113495bSYour Name receive bitmap due to (temporary) fifo contraints. 364*5113495bSYour Name 365*5113495bSYour Name <legal all> 366*5113495bSYour Name 367*5113495bSYour Name reserved_1b 368*5113495bSYour Name 369*5113495bSYour Name <legal 0> 370*5113495bSYour Name */ 371*5113495bSYour Name 372*5113495bSYour Name 373*5113495bSYour Name /* Description RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY 374*5113495bSYour Name 375*5113495bSYour Name Field indicates what the reason was that this MPDU frame 376*5113495bSYour Name was allowed to come into the receive path by RXPCU 377*5113495bSYour Name 378*5113495bSYour Name <enum 0 rxpcu_filter_pass> This MPDU passed the normal 379*5113495bSYour Name frame filter programming of rxpcu 380*5113495bSYour Name 381*5113495bSYour Name <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 382*5113495bSYour Name regular frame filter and would have been dropped, were it 383*5113495bSYour Name not for the frame fitting into the 'monitor_client' 384*5113495bSYour Name category. 385*5113495bSYour Name 386*5113495bSYour Name <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 387*5113495bSYour Name regular frame filter and also did not pass the 388*5113495bSYour Name rxpcu_monitor_client filter. It would have been dropped 389*5113495bSYour Name accept that it did pass the 'monitor_other' category. 390*5113495bSYour Name 391*5113495bSYour Name <legal 0-2> 392*5113495bSYour Name */ 393*5113495bSYour Name #define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 394*5113495bSYour Name #define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 395*5113495bSYour Name #define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 396*5113495bSYour Name 397*5113495bSYour Name /* Description RX_MPDU_END_0_SW_FRAME_GROUP_ID 398*5113495bSYour Name 399*5113495bSYour Name SW processes frames based on certain classifications. 400*5113495bSYour Name This field indicates to what sw classification this MPDU is 401*5113495bSYour Name mapped. 402*5113495bSYour Name 403*5113495bSYour Name The classification is given in priority order 404*5113495bSYour Name 405*5113495bSYour Name 406*5113495bSYour Name 407*5113495bSYour Name <enum 0 sw_frame_group_NDP_frame> 408*5113495bSYour Name 409*5113495bSYour Name 410*5113495bSYour Name 411*5113495bSYour Name <enum 1 sw_frame_group_Multicast_data> 412*5113495bSYour Name 413*5113495bSYour Name <enum 2 sw_frame_group_Unicast_data> 414*5113495bSYour Name 415*5113495bSYour Name <enum 3 sw_frame_group_Null_data > This includes mpdus 416*5113495bSYour Name of type Data Null as well as QoS Data Null 417*5113495bSYour Name 418*5113495bSYour Name 419*5113495bSYour Name 420*5113495bSYour Name <enum 4 sw_frame_group_mgmt_0000 > 421*5113495bSYour Name 422*5113495bSYour Name <enum 5 sw_frame_group_mgmt_0001 > 423*5113495bSYour Name 424*5113495bSYour Name <enum 6 sw_frame_group_mgmt_0010 > 425*5113495bSYour Name 426*5113495bSYour Name <enum 7 sw_frame_group_mgmt_0011 > 427*5113495bSYour Name 428*5113495bSYour Name <enum 8 sw_frame_group_mgmt_0100 > 429*5113495bSYour Name 430*5113495bSYour Name <enum 9 sw_frame_group_mgmt_0101 > 431*5113495bSYour Name 432*5113495bSYour Name <enum 10 sw_frame_group_mgmt_0110 > 433*5113495bSYour Name 434*5113495bSYour Name <enum 11 sw_frame_group_mgmt_0111 > 435*5113495bSYour Name 436*5113495bSYour Name <enum 12 sw_frame_group_mgmt_1000 > 437*5113495bSYour Name 438*5113495bSYour Name <enum 13 sw_frame_group_mgmt_1001 > 439*5113495bSYour Name 440*5113495bSYour Name <enum 14 sw_frame_group_mgmt_1010 > 441*5113495bSYour Name 442*5113495bSYour Name <enum 15 sw_frame_group_mgmt_1011 > 443*5113495bSYour Name 444*5113495bSYour Name <enum 16 sw_frame_group_mgmt_1100 > 445*5113495bSYour Name 446*5113495bSYour Name <enum 17 sw_frame_group_mgmt_1101 > 447*5113495bSYour Name 448*5113495bSYour Name <enum 18 sw_frame_group_mgmt_1110 > 449*5113495bSYour Name 450*5113495bSYour Name <enum 19 sw_frame_group_mgmt_1111 > 451*5113495bSYour Name 452*5113495bSYour Name 453*5113495bSYour Name 454*5113495bSYour Name <enum 20 sw_frame_group_ctrl_0000 > 455*5113495bSYour Name 456*5113495bSYour Name <enum 21 sw_frame_group_ctrl_0001 > 457*5113495bSYour Name 458*5113495bSYour Name <enum 22 sw_frame_group_ctrl_0010 > 459*5113495bSYour Name 460*5113495bSYour Name <enum 23 sw_frame_group_ctrl_0011 > 461*5113495bSYour Name 462*5113495bSYour Name <enum 24 sw_frame_group_ctrl_0100 > 463*5113495bSYour Name 464*5113495bSYour Name <enum 25 sw_frame_group_ctrl_0101 > 465*5113495bSYour Name 466*5113495bSYour Name <enum 26 sw_frame_group_ctrl_0110 > 467*5113495bSYour Name 468*5113495bSYour Name <enum 27 sw_frame_group_ctrl_0111 > 469*5113495bSYour Name 470*5113495bSYour Name <enum 28 sw_frame_group_ctrl_1000 > 471*5113495bSYour Name 472*5113495bSYour Name <enum 29 sw_frame_group_ctrl_1001 > 473*5113495bSYour Name 474*5113495bSYour Name <enum 30 sw_frame_group_ctrl_1010 > 475*5113495bSYour Name 476*5113495bSYour Name <enum 31 sw_frame_group_ctrl_1011 > 477*5113495bSYour Name 478*5113495bSYour Name <enum 32 sw_frame_group_ctrl_1100 > 479*5113495bSYour Name 480*5113495bSYour Name <enum 33 sw_frame_group_ctrl_1101 > 481*5113495bSYour Name 482*5113495bSYour Name <enum 34 sw_frame_group_ctrl_1110 > 483*5113495bSYour Name 484*5113495bSYour Name <enum 35 sw_frame_group_ctrl_1111 > 485*5113495bSYour Name 486*5113495bSYour Name 487*5113495bSYour Name 488*5113495bSYour Name <enum 36 sw_frame_group_unsupported> This covers type 3 489*5113495bSYour Name and protocol version != 0 490*5113495bSYour Name 491*5113495bSYour Name 492*5113495bSYour Name 493*5113495bSYour Name 494*5113495bSYour Name 495*5113495bSYour Name 496*5113495bSYour Name <legal 0-37> 497*5113495bSYour Name */ 498*5113495bSYour Name #define RX_MPDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 499*5113495bSYour Name #define RX_MPDU_END_0_SW_FRAME_GROUP_ID_LSB 2 500*5113495bSYour Name #define RX_MPDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc 501*5113495bSYour Name 502*5113495bSYour Name /* Description RX_MPDU_END_0_RESERVED_0 503*5113495bSYour Name 504*5113495bSYour Name <legal 0> 505*5113495bSYour Name */ 506*5113495bSYour Name #define RX_MPDU_END_0_RESERVED_0_OFFSET 0x00000000 507*5113495bSYour Name #define RX_MPDU_END_0_RESERVED_0_LSB 9 508*5113495bSYour Name #define RX_MPDU_END_0_RESERVED_0_MASK 0x0000fe00 509*5113495bSYour Name 510*5113495bSYour Name /* Description RX_MPDU_END_0_PHY_PPDU_ID 511*5113495bSYour Name 512*5113495bSYour Name A ppdu counter value that PHY increments for every PPDU 513*5113495bSYour Name received. The counter value wraps around 514*5113495bSYour Name 515*5113495bSYour Name <legal all> 516*5113495bSYour Name */ 517*5113495bSYour Name #define RX_MPDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000 518*5113495bSYour Name #define RX_MPDU_END_0_PHY_PPDU_ID_LSB 16 519*5113495bSYour Name #define RX_MPDU_END_0_PHY_PPDU_ID_MASK 0xffff0000 520*5113495bSYour Name 521*5113495bSYour Name /* Description RX_MPDU_END_1_RESERVED_1A 522*5113495bSYour Name 523*5113495bSYour Name <legal 0> 524*5113495bSYour Name */ 525*5113495bSYour Name #define RX_MPDU_END_1_RESERVED_1A_OFFSET 0x00000004 526*5113495bSYour Name #define RX_MPDU_END_1_RESERVED_1A_LSB 0 527*5113495bSYour Name #define RX_MPDU_END_1_RESERVED_1A_MASK 0x000007ff 528*5113495bSYour Name 529*5113495bSYour Name /* Description RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME 530*5113495bSYour Name 531*5113495bSYour Name This bit will be '1' when WEP or TKIP or WAPI key type 532*5113495bSYour Name is received for 11ah short frame. Crypto will bypass the 533*5113495bSYour Name received packet without decryption to RxOLE after setting 534*5113495bSYour Name this bit. 535*5113495bSYour Name */ 536*5113495bSYour Name #define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x00000004 537*5113495bSYour Name #define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_LSB 11 538*5113495bSYour Name #define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_MASK 0x00000800 539*5113495bSYour Name 540*5113495bSYour Name /* Description RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP 541*5113495bSYour Name 542*5113495bSYour Name Indicates that RX packet is not decrypted as Crypto is 543*5113495bSYour Name busy with TX packet processing. 544*5113495bSYour Name */ 545*5113495bSYour Name #define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004 546*5113495bSYour Name #define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB 12 547*5113495bSYour Name #define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK 0x00001000 548*5113495bSYour Name 549*5113495bSYour Name /* Description RX_MPDU_END_1_OVERFLOW_ERR 550*5113495bSYour Name 551*5113495bSYour Name RXPCU Receive FIFO ran out of space to receive the full 552*5113495bSYour Name MPDU. Therefor this MPDU is terminated early and is thus 553*5113495bSYour Name corrupted. 554*5113495bSYour Name 555*5113495bSYour Name 556*5113495bSYour Name 557*5113495bSYour Name This MPDU will not be ACKed. 558*5113495bSYour Name 559*5113495bSYour Name RXPCU might still be able to correctly receive the 560*5113495bSYour Name following MPDUs in the PPDU if enough fifo space became 561*5113495bSYour Name available in time 562*5113495bSYour Name */ 563*5113495bSYour Name #define RX_MPDU_END_1_OVERFLOW_ERR_OFFSET 0x00000004 564*5113495bSYour Name #define RX_MPDU_END_1_OVERFLOW_ERR_LSB 13 565*5113495bSYour Name #define RX_MPDU_END_1_OVERFLOW_ERR_MASK 0x00002000 566*5113495bSYour Name 567*5113495bSYour Name /* Description RX_MPDU_END_1_MPDU_LENGTH_ERR 568*5113495bSYour Name 569*5113495bSYour Name Set by RXPCU if the expected MPDU length does not 570*5113495bSYour Name correspond with the actually received number of bytes in the 571*5113495bSYour Name MPDU. 572*5113495bSYour Name */ 573*5113495bSYour Name #define RX_MPDU_END_1_MPDU_LENGTH_ERR_OFFSET 0x00000004 574*5113495bSYour Name #define RX_MPDU_END_1_MPDU_LENGTH_ERR_LSB 14 575*5113495bSYour Name #define RX_MPDU_END_1_MPDU_LENGTH_ERR_MASK 0x00004000 576*5113495bSYour Name 577*5113495bSYour Name /* Description RX_MPDU_END_1_TKIP_MIC_ERR 578*5113495bSYour Name 579*5113495bSYour Name Set by RX CRYPTO when CRYPTO detected a TKIP MIC error 580*5113495bSYour Name for this MPDU 581*5113495bSYour Name */ 582*5113495bSYour Name #define RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET 0x00000004 583*5113495bSYour Name #define RX_MPDU_END_1_TKIP_MIC_ERR_LSB 15 584*5113495bSYour Name #define RX_MPDU_END_1_TKIP_MIC_ERR_MASK 0x00008000 585*5113495bSYour Name 586*5113495bSYour Name /* Description RX_MPDU_END_1_DECRYPT_ERR 587*5113495bSYour Name 588*5113495bSYour Name Set by RX CRYPTO when CRYPTO detected a decrypt error 589*5113495bSYour Name for this MPDU or CRYPTO received an encrypted frame, but did 590*5113495bSYour Name not get a valid corresponding key id in the peer entry. 591*5113495bSYour Name */ 592*5113495bSYour Name #define RX_MPDU_END_1_DECRYPT_ERR_OFFSET 0x00000004 593*5113495bSYour Name #define RX_MPDU_END_1_DECRYPT_ERR_LSB 16 594*5113495bSYour Name #define RX_MPDU_END_1_DECRYPT_ERR_MASK 0x00010000 595*5113495bSYour Name 596*5113495bSYour Name /* Description RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR 597*5113495bSYour Name 598*5113495bSYour Name Set by RX CRYPTO when CRYPTO detected an unencrypted 599*5113495bSYour Name frame while in the peer entry field 600*5113495bSYour Name 'All_frames_shall_be_encrypted' is set. 601*5113495bSYour Name */ 602*5113495bSYour Name #define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004 603*5113495bSYour Name #define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_LSB 17 604*5113495bSYour Name #define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_MASK 0x00020000 605*5113495bSYour Name 606*5113495bSYour Name /* Description RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO 607*5113495bSYour Name 608*5113495bSYour Name Set by RX CRYPTO to indicate that there is a valid PN 609*5113495bSYour Name field present in this MPDU 610*5113495bSYour Name */ 611*5113495bSYour Name #define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000004 612*5113495bSYour Name #define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_LSB 18 613*5113495bSYour Name #define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00040000 614*5113495bSYour Name 615*5113495bSYour Name /* Description RX_MPDU_END_1_FCS_ERR 616*5113495bSYour Name 617*5113495bSYour Name Set by RXPCU when there is an FCS error detected for 618*5113495bSYour Name this MPDU 619*5113495bSYour Name 620*5113495bSYour Name NOTE that when this field is set, all other (error) 621*5113495bSYour Name field settings should be ignored as modules could have made 622*5113495bSYour Name wrong decisions based on the corrupted data. 623*5113495bSYour Name */ 624*5113495bSYour Name #define RX_MPDU_END_1_FCS_ERR_OFFSET 0x00000004 625*5113495bSYour Name #define RX_MPDU_END_1_FCS_ERR_LSB 19 626*5113495bSYour Name #define RX_MPDU_END_1_FCS_ERR_MASK 0x00080000 627*5113495bSYour Name 628*5113495bSYour Name /* Description RX_MPDU_END_1_MSDU_LENGTH_ERR 629*5113495bSYour Name 630*5113495bSYour Name Set by RXOLE when there is an msdu length error detected 631*5113495bSYour Name in at least 1 of the MSDUs embedded within the MPDU 632*5113495bSYour Name */ 633*5113495bSYour Name #define RX_MPDU_END_1_MSDU_LENGTH_ERR_OFFSET 0x00000004 634*5113495bSYour Name #define RX_MPDU_END_1_MSDU_LENGTH_ERR_LSB 20 635*5113495bSYour Name #define RX_MPDU_END_1_MSDU_LENGTH_ERR_MASK 0x00100000 636*5113495bSYour Name 637*5113495bSYour Name /* Description RX_MPDU_END_1_RXDMA0_DESTINATION_RING 638*5113495bSYour Name 639*5113495bSYour Name The ring to which RXDMA0 shall push the frame, assuming 640*5113495bSYour Name no MPDU level errors are detected. In case of MPDU level 641*5113495bSYour Name errors, RXDMA0 might change the RXDMA0 destination 642*5113495bSYour Name 643*5113495bSYour Name 644*5113495bSYour Name 645*5113495bSYour Name <enum 0 rxdma_release_ring > RXDMA0 shall push the 646*5113495bSYour Name frame to the Release ring. Effectively this means the frame 647*5113495bSYour Name needs to be dropped. 648*5113495bSYour Name 649*5113495bSYour Name 650*5113495bSYour Name 651*5113495bSYour Name <enum 1 rxdma2fw_ring > RXDMA0 shall push the frame to 652*5113495bSYour Name the FW ring 653*5113495bSYour Name 654*5113495bSYour Name 655*5113495bSYour Name 656*5113495bSYour Name <enum 2 rxdma2sw_ring > RXDMA0 shall push the frame to 657*5113495bSYour Name the SW ring 658*5113495bSYour Name 659*5113495bSYour Name 660*5113495bSYour Name 661*5113495bSYour Name <enum 3 rxdma2reo_ring > RXDMA0 shall push the frame 662*5113495bSYour Name to the REO entrance ring 663*5113495bSYour Name 664*5113495bSYour Name 665*5113495bSYour Name 666*5113495bSYour Name <legal all> 667*5113495bSYour Name */ 668*5113495bSYour Name #define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_OFFSET 0x00000004 669*5113495bSYour Name #define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_LSB 21 670*5113495bSYour Name #define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_MASK 0x00600000 671*5113495bSYour Name 672*5113495bSYour Name /* Description RX_MPDU_END_1_RXDMA1_DESTINATION_RING 673*5113495bSYour Name 674*5113495bSYour Name The ring to which RXDMA1 shall push the frame, assuming 675*5113495bSYour Name no MPDU level errors are detected. In case of MPDU level 676*5113495bSYour Name errors, RXDMA1 might change the RXDMA destination 677*5113495bSYour Name 678*5113495bSYour Name 679*5113495bSYour Name 680*5113495bSYour Name <enum 0 rxdma_release_ring > RXDMA1 shall push the 681*5113495bSYour Name frame to the Release ring. Effectively this means the frame 682*5113495bSYour Name needs to be dropped. 683*5113495bSYour Name 684*5113495bSYour Name 685*5113495bSYour Name 686*5113495bSYour Name <enum 1 rxdma2fw_ring > RXDMA1 shall push the frame to 687*5113495bSYour Name the FW ring 688*5113495bSYour Name 689*5113495bSYour Name 690*5113495bSYour Name 691*5113495bSYour Name <enum 2 rxdma2sw_ring > RXDMA1 shall push the frame to 692*5113495bSYour Name the SW ring 693*5113495bSYour Name 694*5113495bSYour Name 695*5113495bSYour Name 696*5113495bSYour Name <enum 3 rxdma2reo_ring > RXDMA1 shall push the frame 697*5113495bSYour Name to the REO entrance ring 698*5113495bSYour Name 699*5113495bSYour Name 700*5113495bSYour Name 701*5113495bSYour Name <legal all> 702*5113495bSYour Name */ 703*5113495bSYour Name #define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_OFFSET 0x00000004 704*5113495bSYour Name #define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_LSB 23 705*5113495bSYour Name #define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_MASK 0x01800000 706*5113495bSYour Name 707*5113495bSYour Name /* Description RX_MPDU_END_1_DECRYPT_STATUS_CODE 708*5113495bSYour Name 709*5113495bSYour Name Field provides insight into the decryption performed 710*5113495bSYour Name 711*5113495bSYour Name 712*5113495bSYour Name 713*5113495bSYour Name <enum 0 decrypt_ok> Frame had protection enabled and 714*5113495bSYour Name decrypted properly 715*5113495bSYour Name 716*5113495bSYour Name <enum 1 decrypt_unprotected_frame > Frame is unprotected 717*5113495bSYour Name and hence bypassed 718*5113495bSYour Name 719*5113495bSYour Name <enum 2 decrypt_data_err > Frame has protection enabled 720*5113495bSYour Name and could not be properly decrypted due to MIC/ICV mismatch 721*5113495bSYour Name etc. 722*5113495bSYour Name 723*5113495bSYour Name <enum 3 decrypt_key_invalid > Frame has protection 724*5113495bSYour Name enabled but the key that was required to decrypt this frame 725*5113495bSYour Name was not valid 726*5113495bSYour Name 727*5113495bSYour Name <enum 4 decrypt_peer_entry_invalid > Frame has 728*5113495bSYour Name protection enabled but the key that was required to decrypt 729*5113495bSYour Name this frame was not valid 730*5113495bSYour Name 731*5113495bSYour Name <enum 5 decrypt_other > Reserved for other indications 732*5113495bSYour Name 733*5113495bSYour Name 734*5113495bSYour Name 735*5113495bSYour Name <legal 0 - 5> 736*5113495bSYour Name */ 737*5113495bSYour Name #define RX_MPDU_END_1_DECRYPT_STATUS_CODE_OFFSET 0x00000004 738*5113495bSYour Name #define RX_MPDU_END_1_DECRYPT_STATUS_CODE_LSB 25 739*5113495bSYour Name #define RX_MPDU_END_1_DECRYPT_STATUS_CODE_MASK 0x0e000000 740*5113495bSYour Name 741*5113495bSYour Name /* Description RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED 742*5113495bSYour Name 743*5113495bSYour Name Frame is received, but RXPCU could not update the 744*5113495bSYour Name receive bitmap due to (temporary) fifo contraints. 745*5113495bSYour Name 746*5113495bSYour Name <legal all> 747*5113495bSYour Name */ 748*5113495bSYour Name #define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000004 749*5113495bSYour Name #define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_LSB 28 750*5113495bSYour Name #define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_MASK 0x10000000 751*5113495bSYour Name 752*5113495bSYour Name /* Description RX_MPDU_END_1_RESERVED_1B 753*5113495bSYour Name 754*5113495bSYour Name <legal 0> 755*5113495bSYour Name */ 756*5113495bSYour Name #define RX_MPDU_END_1_RESERVED_1B_OFFSET 0x00000004 757*5113495bSYour Name #define RX_MPDU_END_1_RESERVED_1B_LSB 29 758*5113495bSYour Name #define RX_MPDU_END_1_RESERVED_1B_MASK 0xe0000000 759*5113495bSYour Name 760*5113495bSYour Name 761*5113495bSYour Name #endif // _RX_MPDU_END_H_ 762