1 /* 2 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 // $ATH_LICENSE_HW_HDR_C$ 18 // 19 // DO NOT EDIT! This file is automatically generated 20 // These definitions are tied to a particular hardware layout 21 22 23 #ifndef _RX_MPDU_END_H_ 24 #define _RX_MPDU_END_H_ 25 #if !defined(__ASSEMBLER__) 26 #endif 27 28 29 // ################ START SUMMARY ################# 30 // 31 // Dword Fields 32 // 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16] 33 // 1 reserved_1a[10:0], unsup_ktype_short_frame[11], rx_in_tx_decrypt_byp[12], overflow_err[13], mpdu_length_err[14], tkip_mic_err[15], decrypt_err[16], unencrypted_frame_err[17], pn_fields_contain_valid_info[18], fcs_err[19], msdu_length_err[20], rxdma0_destination_ring[22:21], rxdma1_destination_ring[24:23], decrypt_status_code[27:25], rx_bitmap_not_updated[28], reserved_1b[31:29] 34 // 35 // ################ END SUMMARY ################# 36 37 #define NUM_OF_DWORDS_RX_MPDU_END 2 38 39 struct rx_mpdu_end { 40 uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] 41 sw_frame_group_id : 7, //[8:2] 42 reserved_0 : 7, //[15:9] 43 phy_ppdu_id : 16; //[31:16] 44 uint32_t reserved_1a : 11, //[10:0] 45 unsup_ktype_short_frame : 1, //[11] 46 rx_in_tx_decrypt_byp : 1, //[12] 47 overflow_err : 1, //[13] 48 mpdu_length_err : 1, //[14] 49 tkip_mic_err : 1, //[15] 50 decrypt_err : 1, //[16] 51 unencrypted_frame_err : 1, //[17] 52 pn_fields_contain_valid_info : 1, //[18] 53 fcs_err : 1, //[19] 54 msdu_length_err : 1, //[20] 55 rxdma0_destination_ring : 2, //[22:21] 56 rxdma1_destination_ring : 2, //[24:23] 57 decrypt_status_code : 3, //[27:25] 58 rx_bitmap_not_updated : 1, //[28] 59 reserved_1b : 3; //[31:29] 60 }; 61 62 /* 63 64 rxpcu_mpdu_filter_in_category 65 66 Field indicates what the reason was that this MPDU frame 67 was allowed to come into the receive path by RXPCU 68 69 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 70 frame filter programming of rxpcu 71 72 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 73 regular frame filter and would have been dropped, were it 74 not for the frame fitting into the 'monitor_client' 75 category. 76 77 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 78 regular frame filter and also did not pass the 79 rxpcu_monitor_client filter. It would have been dropped 80 accept that it did pass the 'monitor_other' category. 81 82 <legal 0-2> 83 84 sw_frame_group_id 85 86 SW processes frames based on certain classifications. 87 This field indicates to what sw classification this MPDU is 88 mapped. 89 90 The classification is given in priority order 91 92 93 94 <enum 0 sw_frame_group_NDP_frame> 95 96 97 98 <enum 1 sw_frame_group_Multicast_data> 99 100 <enum 2 sw_frame_group_Unicast_data> 101 102 <enum 3 sw_frame_group_Null_data > This includes mpdus 103 of type Data Null as well as QoS Data Null 104 105 106 107 <enum 4 sw_frame_group_mgmt_0000 > 108 109 <enum 5 sw_frame_group_mgmt_0001 > 110 111 <enum 6 sw_frame_group_mgmt_0010 > 112 113 <enum 7 sw_frame_group_mgmt_0011 > 114 115 <enum 8 sw_frame_group_mgmt_0100 > 116 117 <enum 9 sw_frame_group_mgmt_0101 > 118 119 <enum 10 sw_frame_group_mgmt_0110 > 120 121 <enum 11 sw_frame_group_mgmt_0111 > 122 123 <enum 12 sw_frame_group_mgmt_1000 > 124 125 <enum 13 sw_frame_group_mgmt_1001 > 126 127 <enum 14 sw_frame_group_mgmt_1010 > 128 129 <enum 15 sw_frame_group_mgmt_1011 > 130 131 <enum 16 sw_frame_group_mgmt_1100 > 132 133 <enum 17 sw_frame_group_mgmt_1101 > 134 135 <enum 18 sw_frame_group_mgmt_1110 > 136 137 <enum 19 sw_frame_group_mgmt_1111 > 138 139 140 141 <enum 20 sw_frame_group_ctrl_0000 > 142 143 <enum 21 sw_frame_group_ctrl_0001 > 144 145 <enum 22 sw_frame_group_ctrl_0010 > 146 147 <enum 23 sw_frame_group_ctrl_0011 > 148 149 <enum 24 sw_frame_group_ctrl_0100 > 150 151 <enum 25 sw_frame_group_ctrl_0101 > 152 153 <enum 26 sw_frame_group_ctrl_0110 > 154 155 <enum 27 sw_frame_group_ctrl_0111 > 156 157 <enum 28 sw_frame_group_ctrl_1000 > 158 159 <enum 29 sw_frame_group_ctrl_1001 > 160 161 <enum 30 sw_frame_group_ctrl_1010 > 162 163 <enum 31 sw_frame_group_ctrl_1011 > 164 165 <enum 32 sw_frame_group_ctrl_1100 > 166 167 <enum 33 sw_frame_group_ctrl_1101 > 168 169 <enum 34 sw_frame_group_ctrl_1110 > 170 171 <enum 35 sw_frame_group_ctrl_1111 > 172 173 174 175 <enum 36 sw_frame_group_unsupported> This covers type 3 176 and protocol version != 0 177 178 179 180 181 182 183 <legal 0-37> 184 185 reserved_0 186 187 <legal 0> 188 189 phy_ppdu_id 190 191 A ppdu counter value that PHY increments for every PPDU 192 received. The counter value wraps around 193 194 <legal all> 195 196 reserved_1a 197 198 <legal 0> 199 200 unsup_ktype_short_frame 201 202 This bit will be '1' when WEP or TKIP or WAPI key type 203 is received for 11ah short frame. Crypto will bypass the 204 received packet without decryption to RxOLE after setting 205 this bit. 206 207 rx_in_tx_decrypt_byp 208 209 Indicates that RX packet is not decrypted as Crypto is 210 busy with TX packet processing. 211 212 overflow_err 213 214 RXPCU Receive FIFO ran out of space to receive the full 215 MPDU. Therefor this MPDU is terminated early and is thus 216 corrupted. 217 218 219 220 This MPDU will not be ACKed. 221 222 RXPCU might still be able to correctly receive the 223 following MPDUs in the PPDU if enough fifo space became 224 available in time 225 226 mpdu_length_err 227 228 Set by RXPCU if the expected MPDU length does not 229 correspond with the actually received number of bytes in the 230 MPDU. 231 232 tkip_mic_err 233 234 Set by RX CRYPTO when CRYPTO detected a TKIP MIC error 235 for this MPDU 236 237 decrypt_err 238 239 Set by RX CRYPTO when CRYPTO detected a decrypt error 240 for this MPDU or CRYPTO received an encrypted frame, but did 241 not get a valid corresponding key id in the peer entry. 242 243 unencrypted_frame_err 244 245 Set by RX CRYPTO when CRYPTO detected an unencrypted 246 frame while in the peer entry field 247 'All_frames_shall_be_encrypted' is set. 248 249 pn_fields_contain_valid_info 250 251 Set by RX CRYPTO to indicate that there is a valid PN 252 field present in this MPDU 253 254 fcs_err 255 256 Set by RXPCU when there is an FCS error detected for 257 this MPDU 258 259 NOTE that when this field is set, all other (error) 260 field settings should be ignored as modules could have made 261 wrong decisions based on the corrupted data. 262 263 msdu_length_err 264 265 Set by RXOLE when there is an msdu length error detected 266 in at least 1 of the MSDUs embedded within the MPDU 267 268 rxdma0_destination_ring 269 270 The ring to which RXDMA0 shall push the frame, assuming 271 no MPDU level errors are detected. In case of MPDU level 272 errors, RXDMA0 might change the RXDMA0 destination 273 274 275 276 <enum 0 rxdma_release_ring > RXDMA0 shall push the 277 frame to the Release ring. Effectively this means the frame 278 needs to be dropped. 279 280 281 282 <enum 1 rxdma2fw_ring > RXDMA0 shall push the frame to 283 the FW ring 284 285 286 287 <enum 2 rxdma2sw_ring > RXDMA0 shall push the frame to 288 the SW ring 289 290 291 292 <enum 3 rxdma2reo_ring > RXDMA0 shall push the frame 293 to the REO entrance ring 294 295 296 297 <legal all> 298 299 rxdma1_destination_ring 300 301 The ring to which RXDMA1 shall push the frame, assuming 302 no MPDU level errors are detected. In case of MPDU level 303 errors, RXDMA1 might change the RXDMA destination 304 305 306 307 <enum 0 rxdma_release_ring > RXDMA1 shall push the 308 frame to the Release ring. Effectively this means the frame 309 needs to be dropped. 310 311 312 313 <enum 1 rxdma2fw_ring > RXDMA1 shall push the frame to 314 the FW ring 315 316 317 318 <enum 2 rxdma2sw_ring > RXDMA1 shall push the frame to 319 the SW ring 320 321 322 323 <enum 3 rxdma2reo_ring > RXDMA1 shall push the frame 324 to the REO entrance ring 325 326 327 328 <legal all> 329 330 decrypt_status_code 331 332 Field provides insight into the decryption performed 333 334 335 336 <enum 0 decrypt_ok> Frame had protection enabled and 337 decrypted properly 338 339 <enum 1 decrypt_unprotected_frame > Frame is unprotected 340 and hence bypassed 341 342 <enum 2 decrypt_data_err > Frame has protection enabled 343 and could not be properly decrypted due to MIC/ICV mismatch 344 etc. 345 346 <enum 3 decrypt_key_invalid > Frame has protection 347 enabled but the key that was required to decrypt this frame 348 was not valid 349 350 <enum 4 decrypt_peer_entry_invalid > Frame has 351 protection enabled but the key that was required to decrypt 352 this frame was not valid 353 354 <enum 5 decrypt_other > Reserved for other indications 355 356 357 358 <legal 0 - 5> 359 360 rx_bitmap_not_updated 361 362 Frame is received, but RXPCU could not update the 363 receive bitmap due to (temporary) fifo contraints. 364 365 <legal all> 366 367 reserved_1b 368 369 <legal 0> 370 */ 371 372 373 /* Description RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY 374 375 Field indicates what the reason was that this MPDU frame 376 was allowed to come into the receive path by RXPCU 377 378 <enum 0 rxpcu_filter_pass> This MPDU passed the normal 379 frame filter programming of rxpcu 380 381 <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the 382 regular frame filter and would have been dropped, were it 383 not for the frame fitting into the 'monitor_client' 384 category. 385 386 <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the 387 regular frame filter and also did not pass the 388 rxpcu_monitor_client filter. It would have been dropped 389 accept that it did pass the 'monitor_other' category. 390 391 <legal 0-2> 392 */ 393 #define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 394 #define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 395 #define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 396 397 /* Description RX_MPDU_END_0_SW_FRAME_GROUP_ID 398 399 SW processes frames based on certain classifications. 400 This field indicates to what sw classification this MPDU is 401 mapped. 402 403 The classification is given in priority order 404 405 406 407 <enum 0 sw_frame_group_NDP_frame> 408 409 410 411 <enum 1 sw_frame_group_Multicast_data> 412 413 <enum 2 sw_frame_group_Unicast_data> 414 415 <enum 3 sw_frame_group_Null_data > This includes mpdus 416 of type Data Null as well as QoS Data Null 417 418 419 420 <enum 4 sw_frame_group_mgmt_0000 > 421 422 <enum 5 sw_frame_group_mgmt_0001 > 423 424 <enum 6 sw_frame_group_mgmt_0010 > 425 426 <enum 7 sw_frame_group_mgmt_0011 > 427 428 <enum 8 sw_frame_group_mgmt_0100 > 429 430 <enum 9 sw_frame_group_mgmt_0101 > 431 432 <enum 10 sw_frame_group_mgmt_0110 > 433 434 <enum 11 sw_frame_group_mgmt_0111 > 435 436 <enum 12 sw_frame_group_mgmt_1000 > 437 438 <enum 13 sw_frame_group_mgmt_1001 > 439 440 <enum 14 sw_frame_group_mgmt_1010 > 441 442 <enum 15 sw_frame_group_mgmt_1011 > 443 444 <enum 16 sw_frame_group_mgmt_1100 > 445 446 <enum 17 sw_frame_group_mgmt_1101 > 447 448 <enum 18 sw_frame_group_mgmt_1110 > 449 450 <enum 19 sw_frame_group_mgmt_1111 > 451 452 453 454 <enum 20 sw_frame_group_ctrl_0000 > 455 456 <enum 21 sw_frame_group_ctrl_0001 > 457 458 <enum 22 sw_frame_group_ctrl_0010 > 459 460 <enum 23 sw_frame_group_ctrl_0011 > 461 462 <enum 24 sw_frame_group_ctrl_0100 > 463 464 <enum 25 sw_frame_group_ctrl_0101 > 465 466 <enum 26 sw_frame_group_ctrl_0110 > 467 468 <enum 27 sw_frame_group_ctrl_0111 > 469 470 <enum 28 sw_frame_group_ctrl_1000 > 471 472 <enum 29 sw_frame_group_ctrl_1001 > 473 474 <enum 30 sw_frame_group_ctrl_1010 > 475 476 <enum 31 sw_frame_group_ctrl_1011 > 477 478 <enum 32 sw_frame_group_ctrl_1100 > 479 480 <enum 33 sw_frame_group_ctrl_1101 > 481 482 <enum 34 sw_frame_group_ctrl_1110 > 483 484 <enum 35 sw_frame_group_ctrl_1111 > 485 486 487 488 <enum 36 sw_frame_group_unsupported> This covers type 3 489 and protocol version != 0 490 491 492 493 494 495 496 <legal 0-37> 497 */ 498 #define RX_MPDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 499 #define RX_MPDU_END_0_SW_FRAME_GROUP_ID_LSB 2 500 #define RX_MPDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc 501 502 /* Description RX_MPDU_END_0_RESERVED_0 503 504 <legal 0> 505 */ 506 #define RX_MPDU_END_0_RESERVED_0_OFFSET 0x00000000 507 #define RX_MPDU_END_0_RESERVED_0_LSB 9 508 #define RX_MPDU_END_0_RESERVED_0_MASK 0x0000fe00 509 510 /* Description RX_MPDU_END_0_PHY_PPDU_ID 511 512 A ppdu counter value that PHY increments for every PPDU 513 received. The counter value wraps around 514 515 <legal all> 516 */ 517 #define RX_MPDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000 518 #define RX_MPDU_END_0_PHY_PPDU_ID_LSB 16 519 #define RX_MPDU_END_0_PHY_PPDU_ID_MASK 0xffff0000 520 521 /* Description RX_MPDU_END_1_RESERVED_1A 522 523 <legal 0> 524 */ 525 #define RX_MPDU_END_1_RESERVED_1A_OFFSET 0x00000004 526 #define RX_MPDU_END_1_RESERVED_1A_LSB 0 527 #define RX_MPDU_END_1_RESERVED_1A_MASK 0x000007ff 528 529 /* Description RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME 530 531 This bit will be '1' when WEP or TKIP or WAPI key type 532 is received for 11ah short frame. Crypto will bypass the 533 received packet without decryption to RxOLE after setting 534 this bit. 535 */ 536 #define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x00000004 537 #define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_LSB 11 538 #define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_MASK 0x00000800 539 540 /* Description RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP 541 542 Indicates that RX packet is not decrypted as Crypto is 543 busy with TX packet processing. 544 */ 545 #define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004 546 #define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB 12 547 #define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK 0x00001000 548 549 /* Description RX_MPDU_END_1_OVERFLOW_ERR 550 551 RXPCU Receive FIFO ran out of space to receive the full 552 MPDU. Therefor this MPDU is terminated early and is thus 553 corrupted. 554 555 556 557 This MPDU will not be ACKed. 558 559 RXPCU might still be able to correctly receive the 560 following MPDUs in the PPDU if enough fifo space became 561 available in time 562 */ 563 #define RX_MPDU_END_1_OVERFLOW_ERR_OFFSET 0x00000004 564 #define RX_MPDU_END_1_OVERFLOW_ERR_LSB 13 565 #define RX_MPDU_END_1_OVERFLOW_ERR_MASK 0x00002000 566 567 /* Description RX_MPDU_END_1_MPDU_LENGTH_ERR 568 569 Set by RXPCU if the expected MPDU length does not 570 correspond with the actually received number of bytes in the 571 MPDU. 572 */ 573 #define RX_MPDU_END_1_MPDU_LENGTH_ERR_OFFSET 0x00000004 574 #define RX_MPDU_END_1_MPDU_LENGTH_ERR_LSB 14 575 #define RX_MPDU_END_1_MPDU_LENGTH_ERR_MASK 0x00004000 576 577 /* Description RX_MPDU_END_1_TKIP_MIC_ERR 578 579 Set by RX CRYPTO when CRYPTO detected a TKIP MIC error 580 for this MPDU 581 */ 582 #define RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET 0x00000004 583 #define RX_MPDU_END_1_TKIP_MIC_ERR_LSB 15 584 #define RX_MPDU_END_1_TKIP_MIC_ERR_MASK 0x00008000 585 586 /* Description RX_MPDU_END_1_DECRYPT_ERR 587 588 Set by RX CRYPTO when CRYPTO detected a decrypt error 589 for this MPDU or CRYPTO received an encrypted frame, but did 590 not get a valid corresponding key id in the peer entry. 591 */ 592 #define RX_MPDU_END_1_DECRYPT_ERR_OFFSET 0x00000004 593 #define RX_MPDU_END_1_DECRYPT_ERR_LSB 16 594 #define RX_MPDU_END_1_DECRYPT_ERR_MASK 0x00010000 595 596 /* Description RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR 597 598 Set by RX CRYPTO when CRYPTO detected an unencrypted 599 frame while in the peer entry field 600 'All_frames_shall_be_encrypted' is set. 601 */ 602 #define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004 603 #define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_LSB 17 604 #define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_MASK 0x00020000 605 606 /* Description RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO 607 608 Set by RX CRYPTO to indicate that there is a valid PN 609 field present in this MPDU 610 */ 611 #define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000004 612 #define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_LSB 18 613 #define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00040000 614 615 /* Description RX_MPDU_END_1_FCS_ERR 616 617 Set by RXPCU when there is an FCS error detected for 618 this MPDU 619 620 NOTE that when this field is set, all other (error) 621 field settings should be ignored as modules could have made 622 wrong decisions based on the corrupted data. 623 */ 624 #define RX_MPDU_END_1_FCS_ERR_OFFSET 0x00000004 625 #define RX_MPDU_END_1_FCS_ERR_LSB 19 626 #define RX_MPDU_END_1_FCS_ERR_MASK 0x00080000 627 628 /* Description RX_MPDU_END_1_MSDU_LENGTH_ERR 629 630 Set by RXOLE when there is an msdu length error detected 631 in at least 1 of the MSDUs embedded within the MPDU 632 */ 633 #define RX_MPDU_END_1_MSDU_LENGTH_ERR_OFFSET 0x00000004 634 #define RX_MPDU_END_1_MSDU_LENGTH_ERR_LSB 20 635 #define RX_MPDU_END_1_MSDU_LENGTH_ERR_MASK 0x00100000 636 637 /* Description RX_MPDU_END_1_RXDMA0_DESTINATION_RING 638 639 The ring to which RXDMA0 shall push the frame, assuming 640 no MPDU level errors are detected. In case of MPDU level 641 errors, RXDMA0 might change the RXDMA0 destination 642 643 644 645 <enum 0 rxdma_release_ring > RXDMA0 shall push the 646 frame to the Release ring. Effectively this means the frame 647 needs to be dropped. 648 649 650 651 <enum 1 rxdma2fw_ring > RXDMA0 shall push the frame to 652 the FW ring 653 654 655 656 <enum 2 rxdma2sw_ring > RXDMA0 shall push the frame to 657 the SW ring 658 659 660 661 <enum 3 rxdma2reo_ring > RXDMA0 shall push the frame 662 to the REO entrance ring 663 664 665 666 <legal all> 667 */ 668 #define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_OFFSET 0x00000004 669 #define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_LSB 21 670 #define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_MASK 0x00600000 671 672 /* Description RX_MPDU_END_1_RXDMA1_DESTINATION_RING 673 674 The ring to which RXDMA1 shall push the frame, assuming 675 no MPDU level errors are detected. In case of MPDU level 676 errors, RXDMA1 might change the RXDMA destination 677 678 679 680 <enum 0 rxdma_release_ring > RXDMA1 shall push the 681 frame to the Release ring. Effectively this means the frame 682 needs to be dropped. 683 684 685 686 <enum 1 rxdma2fw_ring > RXDMA1 shall push the frame to 687 the FW ring 688 689 690 691 <enum 2 rxdma2sw_ring > RXDMA1 shall push the frame to 692 the SW ring 693 694 695 696 <enum 3 rxdma2reo_ring > RXDMA1 shall push the frame 697 to the REO entrance ring 698 699 700 701 <legal all> 702 */ 703 #define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_OFFSET 0x00000004 704 #define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_LSB 23 705 #define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_MASK 0x01800000 706 707 /* Description RX_MPDU_END_1_DECRYPT_STATUS_CODE 708 709 Field provides insight into the decryption performed 710 711 712 713 <enum 0 decrypt_ok> Frame had protection enabled and 714 decrypted properly 715 716 <enum 1 decrypt_unprotected_frame > Frame is unprotected 717 and hence bypassed 718 719 <enum 2 decrypt_data_err > Frame has protection enabled 720 and could not be properly decrypted due to MIC/ICV mismatch 721 etc. 722 723 <enum 3 decrypt_key_invalid > Frame has protection 724 enabled but the key that was required to decrypt this frame 725 was not valid 726 727 <enum 4 decrypt_peer_entry_invalid > Frame has 728 protection enabled but the key that was required to decrypt 729 this frame was not valid 730 731 <enum 5 decrypt_other > Reserved for other indications 732 733 734 735 <legal 0 - 5> 736 */ 737 #define RX_MPDU_END_1_DECRYPT_STATUS_CODE_OFFSET 0x00000004 738 #define RX_MPDU_END_1_DECRYPT_STATUS_CODE_LSB 25 739 #define RX_MPDU_END_1_DECRYPT_STATUS_CODE_MASK 0x0e000000 740 741 /* Description RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED 742 743 Frame is received, but RXPCU could not update the 744 receive bitmap due to (temporary) fifo contraints. 745 746 <legal all> 747 */ 748 #define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000004 749 #define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_LSB 28 750 #define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_MASK 0x10000000 751 752 /* Description RX_MPDU_END_1_RESERVED_1B 753 754 <legal 0> 755 */ 756 #define RX_MPDU_END_1_RESERVED_1B_OFFSET 0x00000004 757 #define RX_MPDU_END_1_RESERVED_1B_LSB 29 758 #define RX_MPDU_END_1_RESERVED_1B_MASK 0xe0000000 759 760 761 #endif // _RX_MPDU_END_H_ 762