1 /* 2 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 // $ATH_LICENSE_HW_HDR_C$ 18 // 19 // DO NOT EDIT! This file is automatically generated 20 // These definitions are tied to a particular hardware layout 21 22 23 #ifndef _TCL_STATUS_RING_H_ 24 #define _TCL_STATUS_RING_H_ 25 #if !defined(__ASSEMBLER__) 26 #endif 27 28 29 // ################ START SUMMARY ################# 30 // 31 // Dword Fields 32 // 0 gse_ctrl[3:0], ase_fse_sel[4], cache_op_res[6:5], index_search_en[7], msdu_cnt_n[31:8] 33 // 1 msdu_byte_cnt_n[31:0] 34 // 2 msdu_timestmp_n[31:0] 35 // 3 cmd_meta_data_31_0[31:0] 36 // 4 cmd_meta_data_63_32[31:0] 37 // 5 hash_indx_val[19:0], cache_set_num[23:20], reserved_5a[31:24] 38 // 6 reserved_6a[31:0] 39 // 7 reserved_7a[19:0], ring_id[27:20], looping_count[31:28] 40 // 41 // ################ END SUMMARY ################# 42 43 #define NUM_OF_DWORDS_TCL_STATUS_RING 8 44 45 struct tcl_status_ring { 46 uint32_t gse_ctrl : 4, //[3:0] 47 ase_fse_sel : 1, //[4] 48 cache_op_res : 2, //[6:5] 49 index_search_en : 1, //[7] 50 msdu_cnt_n : 24; //[31:8] 51 uint32_t msdu_byte_cnt_n : 32; //[31:0] 52 uint32_t msdu_timestmp_n : 32; //[31:0] 53 uint32_t cmd_meta_data_31_0 : 32; //[31:0] 54 uint32_t cmd_meta_data_63_32 : 32; //[31:0] 55 uint32_t hash_indx_val : 20, //[19:0] 56 cache_set_num : 4, //[23:20] 57 reserved_5a : 8; //[31:24] 58 uint32_t reserved_6a : 32; //[31:0] 59 uint32_t reserved_7a : 20, //[19:0] 60 ring_id : 8, //[27:20] 61 looping_count : 4; //[31:28] 62 }; 63 64 /* 65 66 gse_ctrl 67 68 GSE control operations. This includes cache operations 69 and table entry statistics read/clear operation. 70 71 <enum 0 rd_stat> Report or Read statistics 72 73 <enum 1 srch_dis> Search disable. Report only Hash 74 75 <enum 2 Wr_bk_single> Write Back single entry 76 77 <enum 3 wr_bk_all> Write Back entire cache entry 78 79 <enum 4 inval_single> Invalidate single cache entry 80 81 <enum 5 inval_all> Invalidate entire cache 82 83 <enum 6 wr_bk_inval_single> Write back and Invalidate 84 single entry in cache 85 86 <enum 7 wr_bk_inval_all> write back and invalidate 87 entire cache 88 89 <enum 8 clr_stat_single> Clear statistics for single 90 entry 91 92 <legal 0-8> 93 94 Rest of the values reserved. 95 96 For all single entry control operations (write back, 97 Invalidate or both)Statistics will be reported 98 99 ase_fse_sel 100 101 Search Engine for which operation is done. 102 103 1'b0: Address Search Engine Result 104 105 1'b1: Flow Search Engine result 106 107 cache_op_res 108 109 Cache operation result. Following are results of cache 110 operation. 111 112 <enum 0 op_done> Operation successful 113 114 <enum 1 not_fnd> Entry not found in Table 115 116 <enum 2 timeout_er> Timeout Error 117 118 <legal 0-2> 119 120 index_search_en 121 122 When this bit is set to 1 control_buffer_addr[19:0] will 123 be considered as index of the AST or Flow table and GSE 124 commands will be executed accordingly on the entry pointed 125 by the index. 126 127 This feature is disabled by setting this bit to 0. 128 129 <enum 0 index_based_cmd_disable> 130 131 <enum 1 index_based_cmd_enable> 132 133 134 135 <legal all> 136 137 msdu_cnt_n 138 139 MSDU count of Entry. Valid when GSE_CTRL is 4'b0111 and 140 4'b1000 141 142 msdu_byte_cnt_n 143 144 MSDU byte count for entry 1. Valid when GSE_CTRL is 145 4'b0111 and 4'b1000 146 147 msdu_timestmp_n 148 149 MSDU timestamp for entry 1. Valid when GSE_CTRL is 150 4'b0111 and 4'b1000 151 152 cmd_meta_data_31_0 153 154 Meta data from input ring 155 156 <legal all> 157 158 cmd_meta_data_63_32 159 160 Meta data from input ring 161 162 <legal all> 163 164 hash_indx_val 165 166 167 Hash value of the entry in table in case of search 168 failed or search disable. 169 170 <legal all> 171 172 cache_set_num 173 174 Cache set number copied from TCL_GSE_CMD 175 176 reserved_5a 177 178 <legal 0> 179 180 reserved_6a 181 182 <legal 0> 183 184 reserved_7a 185 186 <legal 0> 187 188 ring_id 189 190 The buffer pointer ring ID. 191 192 193 194 Helps with debugging when dumping ring contents. 195 196 <legal all> 197 198 looping_count 199 200 A count value that indicates the number of times the 201 producer of entries into the Ring has looped around the 202 ring. 203 204 At initialization time, this value is set to 0. On the 205 first loop, this value is set to 1. After the max value is 206 reached allowed by the number of bits for this field, the 207 count value continues with 0 again. 208 209 210 211 In case SW is the consumer of the ring entries, it can 212 use this field to figure out up to where the producer of 213 entries has created new entries. This eliminates the need to 214 check where the head pointer' of the ring is located once 215 the SW starts processing an interrupt indicating that new 216 entries have been put into this ring... 217 218 219 220 Also note that SW if it wants only needs to look at the 221 LSB bit of this count value. 222 223 <legal all> 224 */ 225 226 227 /* Description TCL_STATUS_RING_0_GSE_CTRL 228 229 GSE control operations. This includes cache operations 230 and table entry statistics read/clear operation. 231 232 <enum 0 rd_stat> Report or Read statistics 233 234 <enum 1 srch_dis> Search disable. Report only Hash 235 236 <enum 2 Wr_bk_single> Write Back single entry 237 238 <enum 3 wr_bk_all> Write Back entire cache entry 239 240 <enum 4 inval_single> Invalidate single cache entry 241 242 <enum 5 inval_all> Invalidate entire cache 243 244 <enum 6 wr_bk_inval_single> Write back and Invalidate 245 single entry in cache 246 247 <enum 7 wr_bk_inval_all> write back and invalidate 248 entire cache 249 250 <enum 8 clr_stat_single> Clear statistics for single 251 entry 252 253 <legal 0-8> 254 255 Rest of the values reserved. 256 257 For all single entry control operations (write back, 258 Invalidate or both)Statistics will be reported 259 */ 260 #define TCL_STATUS_RING_0_GSE_CTRL_OFFSET 0x00000000 261 #define TCL_STATUS_RING_0_GSE_CTRL_LSB 0 262 #define TCL_STATUS_RING_0_GSE_CTRL_MASK 0x0000000f 263 264 /* Description TCL_STATUS_RING_0_ASE_FSE_SEL 265 266 Search Engine for which operation is done. 267 268 1'b0: Address Search Engine Result 269 270 1'b1: Flow Search Engine result 271 */ 272 #define TCL_STATUS_RING_0_ASE_FSE_SEL_OFFSET 0x00000000 273 #define TCL_STATUS_RING_0_ASE_FSE_SEL_LSB 4 274 #define TCL_STATUS_RING_0_ASE_FSE_SEL_MASK 0x00000010 275 276 /* Description TCL_STATUS_RING_0_CACHE_OP_RES 277 278 Cache operation result. Following are results of cache 279 operation. 280 281 <enum 0 op_done> Operation successful 282 283 <enum 1 not_fnd> Entry not found in Table 284 285 <enum 2 timeout_er> Timeout Error 286 287 <legal 0-2> 288 */ 289 #define TCL_STATUS_RING_0_CACHE_OP_RES_OFFSET 0x00000000 290 #define TCL_STATUS_RING_0_CACHE_OP_RES_LSB 5 291 #define TCL_STATUS_RING_0_CACHE_OP_RES_MASK 0x00000060 292 293 /* Description TCL_STATUS_RING_0_INDEX_SEARCH_EN 294 295 When this bit is set to 1 control_buffer_addr[19:0] will 296 be considered as index of the AST or Flow table and GSE 297 commands will be executed accordingly on the entry pointed 298 by the index. 299 300 This feature is disabled by setting this bit to 0. 301 302 <enum 0 index_based_cmd_disable> 303 304 <enum 1 index_based_cmd_enable> 305 306 307 308 <legal all> 309 */ 310 #define TCL_STATUS_RING_0_INDEX_SEARCH_EN_OFFSET 0x00000000 311 #define TCL_STATUS_RING_0_INDEX_SEARCH_EN_LSB 7 312 #define TCL_STATUS_RING_0_INDEX_SEARCH_EN_MASK 0x00000080 313 314 /* Description TCL_STATUS_RING_0_MSDU_CNT_N 315 316 MSDU count of Entry. Valid when GSE_CTRL is 4'b0111 and 317 4'b1000 318 */ 319 #define TCL_STATUS_RING_0_MSDU_CNT_N_OFFSET 0x00000000 320 #define TCL_STATUS_RING_0_MSDU_CNT_N_LSB 8 321 #define TCL_STATUS_RING_0_MSDU_CNT_N_MASK 0xffffff00 322 323 /* Description TCL_STATUS_RING_1_MSDU_BYTE_CNT_N 324 325 MSDU byte count for entry 1. Valid when GSE_CTRL is 326 4'b0111 and 4'b1000 327 */ 328 #define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_OFFSET 0x00000004 329 #define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_LSB 0 330 #define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_MASK 0xffffffff 331 332 /* Description TCL_STATUS_RING_2_MSDU_TIMESTMP_N 333 334 MSDU timestamp for entry 1. Valid when GSE_CTRL is 335 4'b0111 and 4'b1000 336 */ 337 #define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_OFFSET 0x00000008 338 #define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_LSB 0 339 #define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_MASK 0xffffffff 340 341 /* Description TCL_STATUS_RING_3_CMD_META_DATA_31_0 342 343 Meta data from input ring 344 345 <legal all> 346 */ 347 #define TCL_STATUS_RING_3_CMD_META_DATA_31_0_OFFSET 0x0000000c 348 #define TCL_STATUS_RING_3_CMD_META_DATA_31_0_LSB 0 349 #define TCL_STATUS_RING_3_CMD_META_DATA_31_0_MASK 0xffffffff 350 351 /* Description TCL_STATUS_RING_4_CMD_META_DATA_63_32 352 353 Meta data from input ring 354 355 <legal all> 356 */ 357 #define TCL_STATUS_RING_4_CMD_META_DATA_63_32_OFFSET 0x00000010 358 #define TCL_STATUS_RING_4_CMD_META_DATA_63_32_LSB 0 359 #define TCL_STATUS_RING_4_CMD_META_DATA_63_32_MASK 0xffffffff 360 361 /* Description TCL_STATUS_RING_5_HASH_INDX_VAL 362 363 364 Hash value of the entry in table in case of search 365 failed or search disable. 366 367 <legal all> 368 */ 369 #define TCL_STATUS_RING_5_HASH_INDX_VAL_OFFSET 0x00000014 370 #define TCL_STATUS_RING_5_HASH_INDX_VAL_LSB 0 371 #define TCL_STATUS_RING_5_HASH_INDX_VAL_MASK 0x000fffff 372 373 /* Description TCL_STATUS_RING_5_CACHE_SET_NUM 374 375 Cache set number copied from TCL_GSE_CMD 376 */ 377 #define TCL_STATUS_RING_5_CACHE_SET_NUM_OFFSET 0x00000014 378 #define TCL_STATUS_RING_5_CACHE_SET_NUM_LSB 20 379 #define TCL_STATUS_RING_5_CACHE_SET_NUM_MASK 0x00f00000 380 381 /* Description TCL_STATUS_RING_5_RESERVED_5A 382 383 <legal 0> 384 */ 385 #define TCL_STATUS_RING_5_RESERVED_5A_OFFSET 0x00000014 386 #define TCL_STATUS_RING_5_RESERVED_5A_LSB 24 387 #define TCL_STATUS_RING_5_RESERVED_5A_MASK 0xff000000 388 389 /* Description TCL_STATUS_RING_6_RESERVED_6A 390 391 <legal 0> 392 */ 393 #define TCL_STATUS_RING_6_RESERVED_6A_OFFSET 0x00000018 394 #define TCL_STATUS_RING_6_RESERVED_6A_LSB 0 395 #define TCL_STATUS_RING_6_RESERVED_6A_MASK 0xffffffff 396 397 /* Description TCL_STATUS_RING_7_RESERVED_7A 398 399 <legal 0> 400 */ 401 #define TCL_STATUS_RING_7_RESERVED_7A_OFFSET 0x0000001c 402 #define TCL_STATUS_RING_7_RESERVED_7A_LSB 0 403 #define TCL_STATUS_RING_7_RESERVED_7A_MASK 0x000fffff 404 405 /* Description TCL_STATUS_RING_7_RING_ID 406 407 The buffer pointer ring ID. 408 409 410 411 Helps with debugging when dumping ring contents. 412 413 <legal all> 414 */ 415 #define TCL_STATUS_RING_7_RING_ID_OFFSET 0x0000001c 416 #define TCL_STATUS_RING_7_RING_ID_LSB 20 417 #define TCL_STATUS_RING_7_RING_ID_MASK 0x0ff00000 418 419 /* Description TCL_STATUS_RING_7_LOOPING_COUNT 420 421 A count value that indicates the number of times the 422 producer of entries into the Ring has looped around the 423 ring. 424 425 At initialization time, this value is set to 0. On the 426 first loop, this value is set to 1. After the max value is 427 reached allowed by the number of bits for this field, the 428 count value continues with 0 again. 429 430 431 432 In case SW is the consumer of the ring entries, it can 433 use this field to figure out up to where the producer of 434 entries has created new entries. This eliminates the need to 435 check where the head pointer' of the ring is located once 436 the SW starts processing an interrupt indicating that new 437 entries have been put into this ring... 438 439 440 441 Also note that SW if it wants only needs to look at the 442 LSB bit of this count value. 443 444 <legal all> 445 */ 446 #define TCL_STATUS_RING_7_LOOPING_COUNT_OFFSET 0x0000001c 447 #define TCL_STATUS_RING_7_LOOPING_COUNT_LSB 28 448 #define TCL_STATUS_RING_7_LOOPING_COUNT_MASK 0xf0000000 449 450 451 #endif // _TCL_STATUS_RING_H_ 452