1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any 5*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above 6*5113495bSYour Name * copyright notice and this permission notice appear in all copies. 7*5113495bSYour Name * 8*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*5113495bSYour Name */ 16*5113495bSYour Name 17*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 18*5113495bSYour Name // 19*5113495bSYour Name // wcss_seq_hwiobase.h : automatically generated by Autoseq 3.10 1/18/2021 20*5113495bSYour Name // User Name:c_bipink 21*5113495bSYour Name // 22*5113495bSYour Name // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. 23*5113495bSYour Name // 24*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 25*5113495bSYour Name 26*5113495bSYour Name #ifndef __WCSS_SEQ_BASE_H__ 27*5113495bSYour Name #define __WCSS_SEQ_BASE_H__ 28*5113495bSYour Name 29*5113495bSYour Name #ifdef SCALE_INCLUDES 30*5113495bSYour Name #include "HALhwio.h" 31*5113495bSYour Name #else 32*5113495bSYour Name #include "msmhwio.h" 33*5113495bSYour Name #endif 34*5113495bSYour Name 35*5113495bSYour Name 36*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 37*5113495bSYour Name // Instance Relative Offsets from Block wcss 38*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 39*5113495bSYour Name 40*5113495bSYour Name #define SEQ_WCSS_ECAHB_OFFSET 0x00008000 41*5113495bSYour Name #define SEQ_WCSS_ECAHB_TSLV_OFFSET 0x00009000 42*5113495bSYour Name #define SEQ_WCSS_UMAC_NOC_OFFSET 0x00140000 43*5113495bSYour Name #define SEQ_WCSS_MPSS_OFFSET 0x00200000 44*5113495bSYour Name #define SEQ_WCSS_MPSS_SEG0PDMEM_MPSS_WFAX_PCSS_PDMEM_OFFSET 0x00200000 45*5113495bSYour Name #define SEQ_WCSS_MPSS_SEG0_MPSS_WFAX_PCSS_OFFSET 0x00280000 46*5113495bSYour Name #define SEQ_WCSS_MPSS_SEG0_MPSS_WFAX_PCSS_DUAL_TIMER_OFFSET 0x00281800 47*5113495bSYour Name #define SEQ_WCSS_MPSS_SEG0_MPSS_WFAX_PCSS_WATCHDOG_OFFSET 0x00281c00 48*5113495bSYour Name #define SEQ_WCSS_PHYB_OFFSET 0x00800000 49*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET 0x00800000 50*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_PCSS_B_REG_MAP_OFFSET 0x00880000 51*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC0_B_REG_MAP_OFFSET 0x00880400 52*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC1_B_REG_MAP_OFFSET 0x00880800 53*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET 0x00880c00 54*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET 0x00881000 55*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET 0x00881400 56*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_PCSS_DUAL_TIMER_B_REG_MAP_OFFSET 0x00881800 57*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_PCSS_WATCHDOG_B_REG_MAP_OFFSET 0x00881c00 58*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC5_B_REG_MAP_OFFSET 0x00882c00 59*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_NOC_B_REG_MAP_OFFSET 0x00884000 60*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_TXTD_B_REG_MAP_OFFSET 0x00888000 61*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_TXBF_B_REG_MAP_OFFSET 0x008e8000 62*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_TXFD_B_REG_MAP_OFFSET 0x00918000 63*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_ROBE_B_REG_MAP_OFFSET 0x00920000 64*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_RXTD_B_REG_MAP_OFFSET 0x00928000 65*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_DEMFRONT_B_REG_MAP_OFFSET 0x00930000 66*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_PHYRF_B_REG_MAP_OFFSET 0x009a0000 67*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_OFFSET 0x009c0000 68*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_OFFSET 0x009c0000 69*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_RFA_OTP_OFFSET 0x009c0000 70*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_RFA_OTP_CTRL_OFFSET 0x009c0140 71*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_RFA_TLMM_OFFSET 0x009c4000 72*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_SYSCTRL_OFFSET 0x009c8000 73*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_OFFSET 0x009d4000 74*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_OFFSET 0x009d4000 75*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x009d4300 76*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x009d4800 77*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x009d6000 78*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x009d6040 79*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x009d6080 80*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x009d60c0 81*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x009d6100 82*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x009d6140 83*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x009d6200 84*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x009d6800 85*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x009d6840 86*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x009d6880 87*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x009d68c0 88*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x009d6900 89*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x009d6940 90*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x009d6a00 91*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_DRM_REG_OFFSET 0x009d7c00 92*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_OFFSET 0x009e0000 93*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x009e0000 94*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x009e0400 95*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x009e0800 96*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH0_OFFSET 0x009e1000 97*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH0_OFFSET 0x009e1180 98*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH0_OFFSET 0x009e1300 99*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH0_OFFSET 0x009e1480 100*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x009e1600 101*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_CH0_OFFSET 0x009e1640 102*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x009e2000 103*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH0_OFFSET 0x009e4000 104*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x009e8000 105*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x009e8400 106*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x009e8800 107*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH1_OFFSET 0x009e9000 108*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH1_OFFSET 0x009e9180 109*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH1_OFFSET 0x009e9300 110*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH1_OFFSET 0x009e9480 111*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x009e9600 112*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_CH1_OFFSET 0x009e9640 113*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x009ea000 114*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH1_OFFSET 0x009ec000 115*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH2_OFFSET 0x009f0000 116*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH2_OFFSET 0x009f0400 117*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH2_OFFSET 0x009f0800 118*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH2_OFFSET 0x009f1000 119*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH2_OFFSET 0x009f1180 120*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH2_OFFSET 0x009f1300 121*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH2_OFFSET 0x009f1480 122*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_CH2_OFFSET 0x009f1600 123*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_CH2_OFFSET 0x009f1640 124*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH2_OFFSET 0x009f2000 125*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH2_OFFSET 0x009f4000 126*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH3_OFFSET 0x009f8000 127*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH3_OFFSET 0x009f8400 128*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH3_OFFSET 0x009f8800 129*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH3_OFFSET 0x009f9000 130*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH3_OFFSET 0x009f9180 131*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH3_OFFSET 0x009f9300 132*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH3_OFFSET 0x009f9480 133*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_CH3_OFFSET 0x009f9600 134*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_CH3_OFFSET 0x009f9640 135*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH3_OFFSET 0x009fa000 136*5113495bSYour Name #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH3_OFFSET 0x009fc000 137*5113495bSYour Name #define SEQ_WCSS_UMAC_OFFSET 0x00a00000 138*5113495bSYour Name #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_OFFSET 0x00a00000 139*5113495bSYour Name #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00a00000 140*5113495bSYour Name #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00a01000 141*5113495bSYour Name #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00a02000 142*5113495bSYour Name #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00a03000 143*5113495bSYour Name #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00a04000 144*5113495bSYour Name #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00a05000 145*5113495bSYour Name #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00a06000 146*5113495bSYour Name #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00a07000 147*5113495bSYour Name #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00a08000 148*5113495bSYour Name #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00a09000 149*5113495bSYour Name #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x00a0a000 150*5113495bSYour Name #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x00a0b000 151*5113495bSYour Name #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x00a0c000 152*5113495bSYour Name #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x00a0d000 153*5113495bSYour Name #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x00a0e000 154*5113495bSYour Name #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x00a0f000 155*5113495bSYour Name #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00a10000 156*5113495bSYour Name #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00a11000 157*5113495bSYour Name #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00a12000 158*5113495bSYour Name #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00a13000 159*5113495bSYour Name #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00a14000 160*5113495bSYour Name #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00a15000 161*5113495bSYour Name #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00a16000 162*5113495bSYour Name #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00a17000 163*5113495bSYour Name #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET 0x00a18000 164*5113495bSYour Name #define SEQ_WCSS_UMAC_CXC_TOP_REG_OFFSET 0x00a20000 165*5113495bSYour Name #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00a20000 166*5113495bSYour Name #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00a22000 167*5113495bSYour Name #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00a24000 168*5113495bSYour Name #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00a26000 169*5113495bSYour Name #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00a28000 170*5113495bSYour Name #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x00a2a000 171*5113495bSYour Name #define SEQ_WCSS_UMAC_MAC_TRACER_REG_OFFSET 0x00a30000 172*5113495bSYour Name #define SEQ_WCSS_UMAC_WBM_REG_OFFSET 0x00a34000 173*5113495bSYour Name #define SEQ_WCSS_UMAC_REO_REG_OFFSET 0x00a38000 174*5113495bSYour Name #define SEQ_WCSS_UMAC_TQM_REG_OFFSET 0x00a3c000 175*5113495bSYour Name #define SEQ_WCSS_UMAC_MAC_UMCMN_REG_OFFSET 0x00a40000 176*5113495bSYour Name #define SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET 0x00a44000 177*5113495bSYour Name #define SEQ_WCSS_UMAC_MAC_CMN_PARSER_REG_OFFSET 0x00a47000 178*5113495bSYour Name #define SEQ_WCSS_UMAC_MAC_CCE_TCL_REG_OFFSET 0x00a4a000 179*5113495bSYour Name #define SEQ_WCSS_WMAC2_OFFSET 0x00b00000 180*5113495bSYour Name #define SEQ_WCSS_WMAC2_MAC_PDG_REG_OFFSET 0x00b00000 181*5113495bSYour Name #define SEQ_WCSS_WMAC2_MAC_TXDMA_REG_OFFSET 0x00b03000 182*5113495bSYour Name #define SEQ_WCSS_WMAC2_MAC_RXDMA_REG_OFFSET 0x00b06000 183*5113495bSYour Name #define SEQ_WCSS_WMAC2_MAC_MCMN_REG_OFFSET 0x00b09000 184*5113495bSYour Name #define SEQ_WCSS_WMAC2_MAC_RXPCU_REG_OFFSET 0x00b0c000 185*5113495bSYour Name #define SEQ_WCSS_WMAC2_MAC_TXPCU_REG_OFFSET 0x00b0f000 186*5113495bSYour Name #define SEQ_WCSS_WMAC2_MAC_AMPI_REG_OFFSET 0x00b12000 187*5113495bSYour Name #define SEQ_WCSS_WMAC2_MAC_RXOLE_REG_OFFSET 0x00b15000 188*5113495bSYour Name #define SEQ_WCSS_WMAC2_MAC_RXOLE_PARSER_REG_OFFSET 0x00b18000 189*5113495bSYour Name #define SEQ_WCSS_WMAC2_MAC_CCE_REG_OFFSET 0x00b1b000 190*5113495bSYour Name #define SEQ_WCSS_WMAC2_MAC_TXOLE_REG_OFFSET 0x00b1e000 191*5113495bSYour Name #define SEQ_WCSS_WMAC2_MAC_TXOLE_PARSER_REG_OFFSET 0x00b21000 192*5113495bSYour Name #define SEQ_WCSS_WMAC2_MAC_RRI_REG_OFFSET 0x00b24000 193*5113495bSYour Name #define SEQ_WCSS_WMAC2_MAC_CRYPTO_REG_OFFSET 0x00b27000 194*5113495bSYour Name #define SEQ_WCSS_WMAC2_MAC_HWSCH_REG_OFFSET 0x00b2a000 195*5113495bSYour Name #define SEQ_WCSS_WMAC2_MAC_MXI_REG_OFFSET 0x00b30000 196*5113495bSYour Name #define SEQ_WCSS_WMAC2_MAC_SFM_REG_OFFSET 0x00b33000 197*5113495bSYour Name #define SEQ_WCSS_WMAC2_MAC_RXDMA1_REG_OFFSET 0x00b36000 198*5113495bSYour Name #define SEQ_WCSS_WMAC2_MAC_LPEC_REG_OFFSET 0x00b39000 199*5113495bSYour Name #define SEQ_WCSS_APB_TSLV_OFFSET 0x00b40000 200*5113495bSYour Name #define SEQ_WCSS_WCMN_OFFSET 0x00b50000 201*5113495bSYour Name #define SEQ_WCSS_WFSS_PMM_OFFSET 0x00b60000 202*5113495bSYour Name #define SEQ_WCSS_MSIP_OFFSET 0x00b80000 203*5113495bSYour Name #define SEQ_WCSS_MSIP_PLL_OFFSET 0x00b80000 204*5113495bSYour Name #define SEQ_WCSS_MSIP_BIASCLKS_OFFSET 0x00b80100 205*5113495bSYour Name #define SEQ_WCSS_MSIP_XO_OFFSET 0x00b84000 206*5113495bSYour Name #define SEQ_WCSS_MSIP_MSIP_OTP_OFFSET 0x00b84140 207*5113495bSYour Name #define SEQ_WCSS_MSIP_RBIST_TX_BAREBONE_PHYA_CH0_OFFSET 0x00b8c000 208*5113495bSYour Name #define SEQ_WCSS_MSIP_RBIST_RX_PHYA_CH0_OFFSET 0x00b8c100 209*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_DAC_PHYA_CH0_OFFSET 0x00b8c180 210*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_DAC_DIG_CORRECTION_PHYA_CH0_OFFSET 0x00b8c1c0 211*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_DAC_MISC_PHYA_CH0_OFFSET 0x00b8c2c0 212*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_ADC_PHYA_CH0_OFFSET 0x00b8c340 213*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_I_EVEN_PHYA_CH0_OFFSET 0x00b8c400 214*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_I_ODD_PHYA_CH0_OFFSET 0x00b8c440 215*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_Q_EVEN_PHYA_CH0_OFFSET 0x00b8c480 216*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_Q_ODD_PHYA_CH0_OFFSET 0x00b8c4c0 217*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_RO_PHYA_CH0_OFFSET 0x00b8c500 218*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_BBCLKGEN_PHYA_CH0_OFFSET 0x00b8c600 219*5113495bSYour Name #define SEQ_WCSS_MSIP_RBIST_TX_BAREBONE_PHYA_CH1_OFFSET 0x00b8c800 220*5113495bSYour Name #define SEQ_WCSS_MSIP_RBIST_RX_PHYA_CH1_OFFSET 0x00b8c900 221*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_DAC_PHYA_CH1_OFFSET 0x00b8c980 222*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_DAC_DIG_CORRECTION_PHYA_CH1_OFFSET 0x00b8c9c0 223*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_DAC_MISC_PHYA_CH1_OFFSET 0x00b8cac0 224*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_ADC_PHYA_CH1_OFFSET 0x00b8cb40 225*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_I_EVEN_PHYA_CH1_OFFSET 0x00b8cc00 226*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_I_ODD_PHYA_CH1_OFFSET 0x00b8cc40 227*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_Q_EVEN_PHYA_CH1_OFFSET 0x00b8cc80 228*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_Q_ODD_PHYA_CH1_OFFSET 0x00b8ccc0 229*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_RO_PHYA_CH1_OFFSET 0x00b8cd00 230*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_BBCLKGEN_PHYA_CH1_OFFSET 0x00b8ce00 231*5113495bSYour Name #define SEQ_WCSS_MSIP_RBIST_TX_BAREBONE_PHYA_CH2_OFFSET 0x00b8d000 232*5113495bSYour Name #define SEQ_WCSS_MSIP_RBIST_RX_PHYA_CH2_OFFSET 0x00b8d100 233*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_DAC_PHYA_CH2_OFFSET 0x00b8d180 234*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_DAC_DIG_CORRECTION_PHYA_CH2_OFFSET 0x00b8d1c0 235*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_DAC_MISC_PHYA_CH2_OFFSET 0x00b8d2c0 236*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_ADC_PHYA_CH2_OFFSET 0x00b8d340 237*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_I_EVEN_PHYA_CH2_OFFSET 0x00b8d400 238*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_I_ODD_PHYA_CH2_OFFSET 0x00b8d440 239*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_Q_EVEN_PHYA_CH2_OFFSET 0x00b8d480 240*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_Q_ODD_PHYA_CH2_OFFSET 0x00b8d4c0 241*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_RO_PHYA_CH2_OFFSET 0x00b8d500 242*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_BBCLKGEN_PHYA_CH2_OFFSET 0x00b8d600 243*5113495bSYour Name #define SEQ_WCSS_MSIP_RBIST_TX_BAREBONE_PHYA_CH3_OFFSET 0x00b8d800 244*5113495bSYour Name #define SEQ_WCSS_MSIP_RBIST_RX_PHYA_CH3_OFFSET 0x00b8d900 245*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_DAC_PHYA_CH3_OFFSET 0x00b8d980 246*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_DAC_DIG_CORRECTION_PHYA_CH3_OFFSET 0x00b8d9c0 247*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_DAC_MISC_PHYA_CH3_OFFSET 0x00b8dac0 248*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_ADC_PHYA_CH3_OFFSET 0x00b8db40 249*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_I_EVEN_PHYA_CH3_OFFSET 0x00b8dc00 250*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_I_ODD_PHYA_CH3_OFFSET 0x00b8dc40 251*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_Q_EVEN_PHYA_CH3_OFFSET 0x00b8dc80 252*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_Q_ODD_PHYA_CH3_OFFSET 0x00b8dcc0 253*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_RO_PHYA_CH3_OFFSET 0x00b8dd00 254*5113495bSYour Name #define SEQ_WCSS_MSIP_WL_BBCLKGEN_PHYA_CH3_OFFSET 0x00b8de00 255*5113495bSYour Name #define SEQ_WCSS_PMM_OFFSET 0x00b70000 256*5113495bSYour Name #define SEQ_WCSS_DBG_OFFSET 0x00b90000 257*5113495bSYour Name #define SEQ_WCSS_DBG_ROM_WCSS_DBG_DAPROM_OFFSET 0x00b90000 258*5113495bSYour Name #define SEQ_WCSS_DBG_CSR_WCSS_DBG_CSR_OFFSET 0x00b91000 259*5113495bSYour Name #define SEQ_WCSS_DBG_TSGEN_CXTSGEN_OFFSET 0x00b92000 260*5113495bSYour Name #define SEQ_WCSS_DBG_CTIDBG_QC_CTI_24T_8CH_OFFSET 0x00b94000 261*5113495bSYour Name #define SEQ_WCSS_DBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00b95000 262*5113495bSYour Name #define SEQ_WCSS_DBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00b96000 263*5113495bSYour Name #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_OFFSET 0x00b98000 264*5113495bSYour Name #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00b98280 265*5113495bSYour Name #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00b98000 266*5113495bSYour Name #define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_OFFSET 0x00b99000 267*5113495bSYour Name #define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00b99280 268*5113495bSYour Name #define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00b99000 269*5113495bSYour Name #define SEQ_WCSS_DBG_TPDA_TPDA_S2_W64_D2_M64_CS4C2456A_OFFSET 0x00b9a000 270*5113495bSYour Name #define SEQ_WCSS_DBG_FUN_CXATBFUNNEL_128W8SP_OFFSET 0x00b9b000 271*5113495bSYour Name #define SEQ_WCSS_DBG_TMC_CXTMC_F128W8K_OFFSET 0x00b9c000 272*5113495bSYour Name #define SEQ_WCSS_DBG_UMACDBG_UMAC_DBG_OFFSET 0x00ba0000 273*5113495bSYour Name #define SEQ_WCSS_DBG_UMACDBG_UMAC_DBG_UNOC_UMAC_NOC_OFFSET 0x00ba0000 274*5113495bSYour Name #define SEQ_WCSS_DBG_UMACDBG_UMAC_DBG_UDBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00ba8000 275*5113495bSYour Name #define SEQ_WCSS_DBG_UMACDBG_UMAC_DBG_UDBG_CTI_QC_CTI_15T_8CH_OFFSET 0x00ba9000 276*5113495bSYour Name #define SEQ_WCSS_DBG_UMACDBG_UMAC_DBG_UDBG_P0_MACDBG_CTRL_OFFSET 0x00baa000 277*5113495bSYour Name #define SEQ_WCSS_DBG_UMACDBG_UMAC_DBG_UDBG_P1_MACDBG_CTRL_OFFSET 0x00bab000 278*5113495bSYour Name #define SEQ_WCSS_DBG_UMACDBG_UMAC_DBG_UDBG_P2_MACDBG_CTRL_OFFSET 0x00bac000 279*5113495bSYour Name #define SEQ_WCSS_DBG_PHYA_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bb8000 280*5113495bSYour Name #define SEQ_WCSS_DBG_PHYA_CTI_QC_CTI_10T_8CH_OFFSET 0x00bb9000 281*5113495bSYour Name #define SEQ_WCSS_DBG_PHYA_TRC_PHYTRC_CTRL_OFFSET 0x00bba000 282*5113495bSYour Name #define SEQ_WCSS_DBG_PHYB_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bc8000 283*5113495bSYour Name #define SEQ_WCSS_DBG_PHYB_CTI_QC_CTI_10T_8CH_OFFSET 0x00bc9000 284*5113495bSYour Name #define SEQ_WCSS_DBG_PHYB_TRC_PHYTRC_CTRL_OFFSET 0x00bca000 285*5113495bSYour Name #define SEQ_WCSS_DBG_PHYB_NOC_PHYB_NOC_OFFSET 0x00bc0000 286*5113495bSYour Name #define SEQ_WCSS_DBG_PHYB_CPU0_M3_AHB_AP_OFFSET 0x00bce000 287*5113495bSYour Name #define SEQ_WCSS_DBG_UMAC_CPU_M3_AHB_AP_OFFSET 0x00bf8000 288*5113495bSYour Name #define SEQ_WCSS_DBG_BUS_TIMEOUT_OFFSET 0x00bf9000 289*5113495bSYour Name #define SEQ_WCSS_RET_AHB_OFFSET 0x00c10000 290*5113495bSYour Name #define SEQ_WCSS_WAHB_TSLV_OFFSET 0x00c20000 291*5113495bSYour Name #define SEQ_WCSS_CC_OFFSET 0x00c30000 292*5113495bSYour Name #define SEQ_WCSS_ACMT_OFFSET 0x00c40000 293*5113495bSYour Name #define SEQ_WCSS_WRAPPER_ACMT_OFFSET 0x00c60000 294*5113495bSYour Name #define SEQ_WCSS_Q6SS_WLAN_OFFSET 0x00d00000 295*5113495bSYour Name #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_OFFSET 0x00d00000 296*5113495bSYour Name #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET 0x00d00000 297*5113495bSYour Name #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00d00000 298*5113495bSYour Name #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_OFFSET 0x00d80000 299*5113495bSYour Name #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00d80000 300*5113495bSYour Name #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00d90000 301*5113495bSYour Name #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x00da0000 302*5113495bSYour Name #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x00da1000 303*5113495bSYour Name #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x00da2000 304*5113495bSYour Name #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x00da3000 305*5113495bSYour Name #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x00db0000 306*5113495bSYour Name #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x00db0000 307*5113495bSYour Name 308*5113495bSYour Name 309*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 310*5113495bSYour Name // Instance Relative Offsets from Block mpss_top 311*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 312*5113495bSYour Name 313*5113495bSYour Name #define SEQ_MPSS_TOP_SEG0PDMEM_MPSS_WFAX_PCSS_PDMEM_OFFSET 0x00000000 314*5113495bSYour Name #define SEQ_MPSS_TOP_SEG0_MPSS_WFAX_PCSS_OFFSET 0x00080000 315*5113495bSYour Name #define SEQ_MPSS_TOP_SEG0_MPSS_WFAX_PCSS_DUAL_TIMER_OFFSET 0x00081800 316*5113495bSYour Name #define SEQ_MPSS_TOP_SEG0_MPSS_WFAX_PCSS_WATCHDOG_OFFSET 0x00081c00 317*5113495bSYour Name 318*5113495bSYour Name 319*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 320*5113495bSYour Name // Instance Relative Offsets from Block wfax_top_b 321*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 322*5113495bSYour Name 323*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET 0x00000000 324*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_PCSS_B_REG_MAP_OFFSET 0x00080000 325*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC0_B_REG_MAP_OFFSET 0x00080400 326*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC1_B_REG_MAP_OFFSET 0x00080800 327*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET 0x00080c00 328*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET 0x00081000 329*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET 0x00081400 330*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_PCSS_DUAL_TIMER_B_REG_MAP_OFFSET 0x00081800 331*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_PCSS_WATCHDOG_B_REG_MAP_OFFSET 0x00081c00 332*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC5_B_REG_MAP_OFFSET 0x00082c00 333*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_NOC_B_REG_MAP_OFFSET 0x00084000 334*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_TXTD_B_REG_MAP_OFFSET 0x00088000 335*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_TXBF_B_REG_MAP_OFFSET 0x000e8000 336*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_TXFD_B_REG_MAP_OFFSET 0x00118000 337*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_ROBE_B_REG_MAP_OFFSET 0x00120000 338*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_RXTD_B_REG_MAP_OFFSET 0x00128000 339*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_DEMFRONT_B_REG_MAP_OFFSET 0x00130000 340*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_PHYRF_B_REG_MAP_OFFSET 0x001a0000 341*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_OFFSET 0x001c0000 342*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_OFFSET 0x001c0000 343*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_RFA_OTP_OFFSET 0x001c0000 344*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_RFA_OTP_CTRL_OFFSET 0x001c0140 345*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_RFA_TLMM_OFFSET 0x001c4000 346*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_SYSCTRL_OFFSET 0x001c8000 347*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_OFFSET 0x001d4000 348*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_OFFSET 0x001d4000 349*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x001d4300 350*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x001d4800 351*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x001d6000 352*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x001d6040 353*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x001d6080 354*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x001d60c0 355*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x001d6100 356*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x001d6140 357*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x001d6200 358*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x001d6800 359*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x001d6840 360*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x001d6880 361*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x001d68c0 362*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x001d6900 363*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x001d6940 364*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x001d6a00 365*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_DRM_REG_OFFSET 0x001d7c00 366*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_OFFSET 0x001e0000 367*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x001e0000 368*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x001e0400 369*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x001e0800 370*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH0_OFFSET 0x001e1000 371*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH0_OFFSET 0x001e1180 372*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH0_OFFSET 0x001e1300 373*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH0_OFFSET 0x001e1480 374*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x001e1600 375*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_CH0_OFFSET 0x001e1640 376*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x001e2000 377*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH0_OFFSET 0x001e4000 378*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x001e8000 379*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x001e8400 380*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x001e8800 381*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH1_OFFSET 0x001e9000 382*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH1_OFFSET 0x001e9180 383*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH1_OFFSET 0x001e9300 384*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH1_OFFSET 0x001e9480 385*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x001e9600 386*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_CH1_OFFSET 0x001e9640 387*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x001ea000 388*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH1_OFFSET 0x001ec000 389*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH2_OFFSET 0x001f0000 390*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH2_OFFSET 0x001f0400 391*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH2_OFFSET 0x001f0800 392*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH2_OFFSET 0x001f1000 393*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH2_OFFSET 0x001f1180 394*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH2_OFFSET 0x001f1300 395*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH2_OFFSET 0x001f1480 396*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_CH2_OFFSET 0x001f1600 397*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_CH2_OFFSET 0x001f1640 398*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH2_OFFSET 0x001f2000 399*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH2_OFFSET 0x001f4000 400*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH3_OFFSET 0x001f8000 401*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH3_OFFSET 0x001f8400 402*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH3_OFFSET 0x001f8800 403*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH3_OFFSET 0x001f9000 404*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH3_OFFSET 0x001f9180 405*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH3_OFFSET 0x001f9300 406*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH3_OFFSET 0x001f9480 407*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_CH3_OFFSET 0x001f9600 408*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_CH3_OFFSET 0x001f9640 409*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH3_OFFSET 0x001fa000 410*5113495bSYour Name #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH3_OFFSET 0x001fc000 411*5113495bSYour Name 412*5113495bSYour Name 413*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 414*5113495bSYour Name // Instance Relative Offsets from Block iron2g 415*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 416*5113495bSYour Name 417*5113495bSYour Name #define SEQ_IRON2G_RFA_DIG_OFFSET 0x00000000 418*5113495bSYour Name #define SEQ_IRON2G_RFA_DIG_RFA_OTP_OFFSET 0x00000000 419*5113495bSYour Name #define SEQ_IRON2G_RFA_DIG_RFA_OTP_CTRL_OFFSET 0x00000140 420*5113495bSYour Name #define SEQ_IRON2G_RFA_DIG_RFA_TLMM_OFFSET 0x00004000 421*5113495bSYour Name #define SEQ_IRON2G_RFA_DIG_SYSCTRL_OFFSET 0x00008000 422*5113495bSYour Name #define SEQ_IRON2G_RFA_CMN_OFFSET 0x00014000 423*5113495bSYour Name #define SEQ_IRON2G_RFA_CMN_AON_OFFSET 0x00014000 424*5113495bSYour Name #define SEQ_IRON2G_RFA_CMN_RFFE_M_OFFSET 0x00014300 425*5113495bSYour Name #define SEQ_IRON2G_RFA_CMN_CLKGEN_OFFSET 0x00014800 426*5113495bSYour Name #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00016000 427*5113495bSYour Name #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00016040 428*5113495bSYour Name #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00016080 429*5113495bSYour Name #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x000160c0 430*5113495bSYour Name #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00016100 431*5113495bSYour Name #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x00016140 432*5113495bSYour Name #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00016200 433*5113495bSYour Name #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00016800 434*5113495bSYour Name #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00016840 435*5113495bSYour Name #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x00016880 436*5113495bSYour Name #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x000168c0 437*5113495bSYour Name #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00016900 438*5113495bSYour Name #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x00016940 439*5113495bSYour Name #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x00016a00 440*5113495bSYour Name #define SEQ_IRON2G_RFA_CMN_DRM_REG_OFFSET 0x00017c00 441*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_OFFSET 0x00020000 442*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_MC_CH0_OFFSET 0x00020000 443*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_RXBB_CH0_OFFSET 0x00020400 444*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_TXBB_CH0_OFFSET 0x00020800 445*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_RXFE2_CH0_OFFSET 0x00021000 446*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_RXFE5_CH0_OFFSET 0x00021180 447*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_TXFE2_CH0_OFFSET 0x00021300 448*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_TXFE5_CH0_OFFSET 0x00021480 449*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x00021600 450*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_LO_CH0_OFFSET 0x00021640 451*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_TPC_CH0_OFFSET 0x00022000 452*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_MEM_CH0_OFFSET 0x00024000 453*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_MC_CH1_OFFSET 0x00028000 454*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_RXBB_CH1_OFFSET 0x00028400 455*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_TXBB_CH1_OFFSET 0x00028800 456*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_RXFE2_CH1_OFFSET 0x00029000 457*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_RXFE5_CH1_OFFSET 0x00029180 458*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_TXFE2_CH1_OFFSET 0x00029300 459*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_TXFE5_CH1_OFFSET 0x00029480 460*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x00029600 461*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_LO_CH1_OFFSET 0x00029640 462*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_TPC_CH1_OFFSET 0x0002a000 463*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_MEM_CH1_OFFSET 0x0002c000 464*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_MC_CH2_OFFSET 0x00030000 465*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_RXBB_CH2_OFFSET 0x00030400 466*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_TXBB_CH2_OFFSET 0x00030800 467*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_RXFE2_CH2_OFFSET 0x00031000 468*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_RXFE5_CH2_OFFSET 0x00031180 469*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_TXFE2_CH2_OFFSET 0x00031300 470*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_TXFE5_CH2_OFFSET 0x00031480 471*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_LO_PAL_CH2_OFFSET 0x00031600 472*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_LO_CH2_OFFSET 0x00031640 473*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_TPC_CH2_OFFSET 0x00032000 474*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_MEM_CH2_OFFSET 0x00034000 475*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_MC_CH3_OFFSET 0x00038000 476*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_RXBB_CH3_OFFSET 0x00038400 477*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_TXBB_CH3_OFFSET 0x00038800 478*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_RXFE2_CH3_OFFSET 0x00039000 479*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_RXFE5_CH3_OFFSET 0x00039180 480*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_TXFE2_CH3_OFFSET 0x00039300 481*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_TXFE5_CH3_OFFSET 0x00039480 482*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_LO_PAL_CH3_OFFSET 0x00039600 483*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_LO_CH3_OFFSET 0x00039640 484*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_TPC_CH3_OFFSET 0x0003a000 485*5113495bSYour Name #define SEQ_IRON2G_RFA_WL_WL_MEM_CH3_OFFSET 0x0003c000 486*5113495bSYour Name 487*5113495bSYour Name 488*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 489*5113495bSYour Name // Instance Relative Offsets from Block rfa_dig 490*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 491*5113495bSYour Name 492*5113495bSYour Name #define SEQ_RFA_DIG_RFA_OTP_OFFSET 0x00000000 493*5113495bSYour Name #define SEQ_RFA_DIG_RFA_OTP_CTRL_OFFSET 0x00000140 494*5113495bSYour Name #define SEQ_RFA_DIG_RFA_TLMM_OFFSET 0x00004000 495*5113495bSYour Name #define SEQ_RFA_DIG_SYSCTRL_OFFSET 0x00008000 496*5113495bSYour Name 497*5113495bSYour Name 498*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 499*5113495bSYour Name // Instance Relative Offsets from Block rfa_cmn 500*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 501*5113495bSYour Name 502*5113495bSYour Name #define SEQ_RFA_CMN_AON_OFFSET 0x00000000 503*5113495bSYour Name #define SEQ_RFA_CMN_RFFE_M_OFFSET 0x00000300 504*5113495bSYour Name #define SEQ_RFA_CMN_CLKGEN_OFFSET 0x00000800 505*5113495bSYour Name #define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00002000 506*5113495bSYour Name #define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00002040 507*5113495bSYour Name #define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00002080 508*5113495bSYour Name #define SEQ_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x000020c0 509*5113495bSYour Name #define SEQ_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00002100 510*5113495bSYour Name #define SEQ_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x00002140 511*5113495bSYour Name #define SEQ_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00002200 512*5113495bSYour Name #define SEQ_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00002800 513*5113495bSYour Name #define SEQ_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00002840 514*5113495bSYour Name #define SEQ_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x00002880 515*5113495bSYour Name #define SEQ_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x000028c0 516*5113495bSYour Name #define SEQ_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00002900 517*5113495bSYour Name #define SEQ_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x00002940 518*5113495bSYour Name #define SEQ_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x00002a00 519*5113495bSYour Name #define SEQ_RFA_CMN_DRM_REG_OFFSET 0x00003c00 520*5113495bSYour Name 521*5113495bSYour Name 522*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 523*5113495bSYour Name // Instance Relative Offsets from Block rfa_wl 524*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 525*5113495bSYour Name 526*5113495bSYour Name #define SEQ_RFA_WL_WL_MC_CH0_OFFSET 0x00000000 527*5113495bSYour Name #define SEQ_RFA_WL_WL_RXBB_CH0_OFFSET 0x00000400 528*5113495bSYour Name #define SEQ_RFA_WL_WL_TXBB_CH0_OFFSET 0x00000800 529*5113495bSYour Name #define SEQ_RFA_WL_WL_RXFE2_CH0_OFFSET 0x00001000 530*5113495bSYour Name #define SEQ_RFA_WL_WL_RXFE5_CH0_OFFSET 0x00001180 531*5113495bSYour Name #define SEQ_RFA_WL_WL_TXFE2_CH0_OFFSET 0x00001300 532*5113495bSYour Name #define SEQ_RFA_WL_WL_TXFE5_CH0_OFFSET 0x00001480 533*5113495bSYour Name #define SEQ_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x00001600 534*5113495bSYour Name #define SEQ_RFA_WL_WL_LO_CH0_OFFSET 0x00001640 535*5113495bSYour Name #define SEQ_RFA_WL_WL_TPC_CH0_OFFSET 0x00002000 536*5113495bSYour Name #define SEQ_RFA_WL_WL_MEM_CH0_OFFSET 0x00004000 537*5113495bSYour Name #define SEQ_RFA_WL_WL_MC_CH1_OFFSET 0x00008000 538*5113495bSYour Name #define SEQ_RFA_WL_WL_RXBB_CH1_OFFSET 0x00008400 539*5113495bSYour Name #define SEQ_RFA_WL_WL_TXBB_CH1_OFFSET 0x00008800 540*5113495bSYour Name #define SEQ_RFA_WL_WL_RXFE2_CH1_OFFSET 0x00009000 541*5113495bSYour Name #define SEQ_RFA_WL_WL_RXFE5_CH1_OFFSET 0x00009180 542*5113495bSYour Name #define SEQ_RFA_WL_WL_TXFE2_CH1_OFFSET 0x00009300 543*5113495bSYour Name #define SEQ_RFA_WL_WL_TXFE5_CH1_OFFSET 0x00009480 544*5113495bSYour Name #define SEQ_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x00009600 545*5113495bSYour Name #define SEQ_RFA_WL_WL_LO_CH1_OFFSET 0x00009640 546*5113495bSYour Name #define SEQ_RFA_WL_WL_TPC_CH1_OFFSET 0x0000a000 547*5113495bSYour Name #define SEQ_RFA_WL_WL_MEM_CH1_OFFSET 0x0000c000 548*5113495bSYour Name #define SEQ_RFA_WL_WL_MC_CH2_OFFSET 0x00010000 549*5113495bSYour Name #define SEQ_RFA_WL_WL_RXBB_CH2_OFFSET 0x00010400 550*5113495bSYour Name #define SEQ_RFA_WL_WL_TXBB_CH2_OFFSET 0x00010800 551*5113495bSYour Name #define SEQ_RFA_WL_WL_RXFE2_CH2_OFFSET 0x00011000 552*5113495bSYour Name #define SEQ_RFA_WL_WL_RXFE5_CH2_OFFSET 0x00011180 553*5113495bSYour Name #define SEQ_RFA_WL_WL_TXFE2_CH2_OFFSET 0x00011300 554*5113495bSYour Name #define SEQ_RFA_WL_WL_TXFE5_CH2_OFFSET 0x00011480 555*5113495bSYour Name #define SEQ_RFA_WL_WL_LO_PAL_CH2_OFFSET 0x00011600 556*5113495bSYour Name #define SEQ_RFA_WL_WL_LO_CH2_OFFSET 0x00011640 557*5113495bSYour Name #define SEQ_RFA_WL_WL_TPC_CH2_OFFSET 0x00012000 558*5113495bSYour Name #define SEQ_RFA_WL_WL_MEM_CH2_OFFSET 0x00014000 559*5113495bSYour Name #define SEQ_RFA_WL_WL_MC_CH3_OFFSET 0x00018000 560*5113495bSYour Name #define SEQ_RFA_WL_WL_RXBB_CH3_OFFSET 0x00018400 561*5113495bSYour Name #define SEQ_RFA_WL_WL_TXBB_CH3_OFFSET 0x00018800 562*5113495bSYour Name #define SEQ_RFA_WL_WL_RXFE2_CH3_OFFSET 0x00019000 563*5113495bSYour Name #define SEQ_RFA_WL_WL_RXFE5_CH3_OFFSET 0x00019180 564*5113495bSYour Name #define SEQ_RFA_WL_WL_TXFE2_CH3_OFFSET 0x00019300 565*5113495bSYour Name #define SEQ_RFA_WL_WL_TXFE5_CH3_OFFSET 0x00019480 566*5113495bSYour Name #define SEQ_RFA_WL_WL_LO_PAL_CH3_OFFSET 0x00019600 567*5113495bSYour Name #define SEQ_RFA_WL_WL_LO_CH3_OFFSET 0x00019640 568*5113495bSYour Name #define SEQ_RFA_WL_WL_TPC_CH3_OFFSET 0x0001a000 569*5113495bSYour Name #define SEQ_RFA_WL_WL_MEM_CH3_OFFSET 0x0001c000 570*5113495bSYour Name 571*5113495bSYour Name 572*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 573*5113495bSYour Name // Instance Relative Offsets from Block umac_top_reg 574*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 575*5113495bSYour Name 576*5113495bSYour Name #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_OFFSET 0x00000000 577*5113495bSYour Name #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00000000 578*5113495bSYour Name #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00001000 579*5113495bSYour Name #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00002000 580*5113495bSYour Name #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00003000 581*5113495bSYour Name #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00004000 582*5113495bSYour Name #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00005000 583*5113495bSYour Name #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00006000 584*5113495bSYour Name #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00007000 585*5113495bSYour Name #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00008000 586*5113495bSYour Name #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00009000 587*5113495bSYour Name #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x0000a000 588*5113495bSYour Name #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x0000b000 589*5113495bSYour Name #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x0000c000 590*5113495bSYour Name #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x0000d000 591*5113495bSYour Name #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x0000e000 592*5113495bSYour Name #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x0000f000 593*5113495bSYour Name #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00010000 594*5113495bSYour Name #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00011000 595*5113495bSYour Name #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00012000 596*5113495bSYour Name #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00013000 597*5113495bSYour Name #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00014000 598*5113495bSYour Name #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00015000 599*5113495bSYour Name #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00016000 600*5113495bSYour Name #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00017000 601*5113495bSYour Name #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET 0x00018000 602*5113495bSYour Name #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_OFFSET 0x00020000 603*5113495bSYour Name #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00020000 604*5113495bSYour Name #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00022000 605*5113495bSYour Name #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00024000 606*5113495bSYour Name #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00026000 607*5113495bSYour Name #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00028000 608*5113495bSYour Name #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0002a000 609*5113495bSYour Name #define SEQ_UMAC_TOP_REG_MAC_TRACER_REG_OFFSET 0x00030000 610*5113495bSYour Name #define SEQ_UMAC_TOP_REG_WBM_REG_OFFSET 0x00034000 611*5113495bSYour Name #define SEQ_UMAC_TOP_REG_REO_REG_OFFSET 0x00038000 612*5113495bSYour Name #define SEQ_UMAC_TOP_REG_TQM_REG_OFFSET 0x0003c000 613*5113495bSYour Name #define SEQ_UMAC_TOP_REG_MAC_UMCMN_REG_OFFSET 0x00040000 614*5113495bSYour Name #define SEQ_UMAC_TOP_REG_MAC_TCL_REG_OFFSET 0x00044000 615*5113495bSYour Name #define SEQ_UMAC_TOP_REG_MAC_CMN_PARSER_REG_OFFSET 0x00047000 616*5113495bSYour Name #define SEQ_UMAC_TOP_REG_MAC_CCE_TCL_REG_OFFSET 0x0004a000 617*5113495bSYour Name 618*5113495bSYour Name 619*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 620*5113495bSYour Name // Instance Relative Offsets from Block wfss_ce_reg 621*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 622*5113495bSYour Name 623*5113495bSYour Name #define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00000000 624*5113495bSYour Name #define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00001000 625*5113495bSYour Name #define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00002000 626*5113495bSYour Name #define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00003000 627*5113495bSYour Name #define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00004000 628*5113495bSYour Name #define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00005000 629*5113495bSYour Name #define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00006000 630*5113495bSYour Name #define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00007000 631*5113495bSYour Name #define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00008000 632*5113495bSYour Name #define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00009000 633*5113495bSYour Name #define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x0000a000 634*5113495bSYour Name #define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x0000b000 635*5113495bSYour Name #define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x0000c000 636*5113495bSYour Name #define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x0000d000 637*5113495bSYour Name #define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x0000e000 638*5113495bSYour Name #define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x0000f000 639*5113495bSYour Name #define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00010000 640*5113495bSYour Name #define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00011000 641*5113495bSYour Name #define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00012000 642*5113495bSYour Name #define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00013000 643*5113495bSYour Name #define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00014000 644*5113495bSYour Name #define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00015000 645*5113495bSYour Name #define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00016000 646*5113495bSYour Name #define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00017000 647*5113495bSYour Name #define SEQ_WFSS_CE_REG_WFSS_CE_COMMON_REG_OFFSET 0x00018000 648*5113495bSYour Name 649*5113495bSYour Name 650*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 651*5113495bSYour Name // Instance Relative Offsets from Block cxc_top_reg 652*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 653*5113495bSYour Name 654*5113495bSYour Name #define SEQ_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00000000 655*5113495bSYour Name #define SEQ_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00002000 656*5113495bSYour Name #define SEQ_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00004000 657*5113495bSYour Name #define SEQ_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00006000 658*5113495bSYour Name #define SEQ_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00008000 659*5113495bSYour Name #define SEQ_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0000a000 660*5113495bSYour Name 661*5113495bSYour Name 662*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 663*5113495bSYour Name // Instance Relative Offsets from Block wmac_top_reg 664*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 665*5113495bSYour Name 666*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_PDG_REG_OFFSET 0x00000000 667*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_TXDMA_REG_OFFSET 0x00003000 668*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET 0x00006000 669*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_MCMN_REG_OFFSET 0x00009000 670*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_RXPCU_REG_OFFSET 0x0000c000 671*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_TXPCU_REG_OFFSET 0x0000f000 672*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_AMPI_REG_OFFSET 0x00012000 673*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_RXOLE_REG_OFFSET 0x00015000 674*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_RXOLE_PARSER_REG_OFFSET 0x00018000 675*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_CCE_REG_OFFSET 0x0001b000 676*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_TXOLE_REG_OFFSET 0x0001e000 677*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_TXOLE_PARSER_REG_OFFSET 0x00021000 678*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_RRI_REG_OFFSET 0x00024000 679*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_CRYPTO_REG_OFFSET 0x00027000 680*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_HWSCH_REG_OFFSET 0x0002a000 681*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_MXI_REG_OFFSET 0x00030000 682*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_SFM_REG_OFFSET 0x00033000 683*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_RXDMA1_REG_OFFSET 0x00036000 684*5113495bSYour Name #define SEQ_WMAC_TOP_REG_MAC_LPEC_REG_OFFSET 0x00039000 685*5113495bSYour Name 686*5113495bSYour Name 687*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 688*5113495bSYour Name // Instance Relative Offsets from Block msip 689*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 690*5113495bSYour Name 691*5113495bSYour Name #define SEQ_MSIP_PLL_OFFSET 0x00000000 692*5113495bSYour Name #define SEQ_MSIP_BIASCLKS_OFFSET 0x00000100 693*5113495bSYour Name #define SEQ_MSIP_XO_OFFSET 0x00004000 694*5113495bSYour Name #define SEQ_MSIP_MSIP_OTP_OFFSET 0x00004140 695*5113495bSYour Name #define SEQ_MSIP_RBIST_TX_BAREBONE_PHYA_CH0_OFFSET 0x0000c000 696*5113495bSYour Name #define SEQ_MSIP_RBIST_RX_PHYA_CH0_OFFSET 0x0000c100 697*5113495bSYour Name #define SEQ_MSIP_WL_DAC_PHYA_CH0_OFFSET 0x0000c180 698*5113495bSYour Name #define SEQ_MSIP_WL_DAC_DIG_CORRECTION_PHYA_CH0_OFFSET 0x0000c1c0 699*5113495bSYour Name #define SEQ_MSIP_WL_DAC_MISC_PHYA_CH0_OFFSET 0x0000c2c0 700*5113495bSYour Name #define SEQ_MSIP_WL_ADC_PHYA_CH0_OFFSET 0x0000c340 701*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_I_EVEN_PHYA_CH0_OFFSET 0x0000c400 702*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_I_ODD_PHYA_CH0_OFFSET 0x0000c440 703*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_Q_EVEN_PHYA_CH0_OFFSET 0x0000c480 704*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_Q_ODD_PHYA_CH0_OFFSET 0x0000c4c0 705*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_RO_PHYA_CH0_OFFSET 0x0000c500 706*5113495bSYour Name #define SEQ_MSIP_WL_BBCLKGEN_PHYA_CH0_OFFSET 0x0000c600 707*5113495bSYour Name #define SEQ_MSIP_RBIST_TX_BAREBONE_PHYA_CH1_OFFSET 0x0000c800 708*5113495bSYour Name #define SEQ_MSIP_RBIST_RX_PHYA_CH1_OFFSET 0x0000c900 709*5113495bSYour Name #define SEQ_MSIP_WL_DAC_PHYA_CH1_OFFSET 0x0000c980 710*5113495bSYour Name #define SEQ_MSIP_WL_DAC_DIG_CORRECTION_PHYA_CH1_OFFSET 0x0000c9c0 711*5113495bSYour Name #define SEQ_MSIP_WL_DAC_MISC_PHYA_CH1_OFFSET 0x0000cac0 712*5113495bSYour Name #define SEQ_MSIP_WL_ADC_PHYA_CH1_OFFSET 0x0000cb40 713*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_I_EVEN_PHYA_CH1_OFFSET 0x0000cc00 714*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_I_ODD_PHYA_CH1_OFFSET 0x0000cc40 715*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_Q_EVEN_PHYA_CH1_OFFSET 0x0000cc80 716*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_Q_ODD_PHYA_CH1_OFFSET 0x0000ccc0 717*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_RO_PHYA_CH1_OFFSET 0x0000cd00 718*5113495bSYour Name #define SEQ_MSIP_WL_BBCLKGEN_PHYA_CH1_OFFSET 0x0000ce00 719*5113495bSYour Name #define SEQ_MSIP_RBIST_TX_BAREBONE_PHYA_CH2_OFFSET 0x0000d000 720*5113495bSYour Name #define SEQ_MSIP_RBIST_RX_PHYA_CH2_OFFSET 0x0000d100 721*5113495bSYour Name #define SEQ_MSIP_WL_DAC_PHYA_CH2_OFFSET 0x0000d180 722*5113495bSYour Name #define SEQ_MSIP_WL_DAC_DIG_CORRECTION_PHYA_CH2_OFFSET 0x0000d1c0 723*5113495bSYour Name #define SEQ_MSIP_WL_DAC_MISC_PHYA_CH2_OFFSET 0x0000d2c0 724*5113495bSYour Name #define SEQ_MSIP_WL_ADC_PHYA_CH2_OFFSET 0x0000d340 725*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_I_EVEN_PHYA_CH2_OFFSET 0x0000d400 726*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_I_ODD_PHYA_CH2_OFFSET 0x0000d440 727*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_Q_EVEN_PHYA_CH2_OFFSET 0x0000d480 728*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_Q_ODD_PHYA_CH2_OFFSET 0x0000d4c0 729*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_RO_PHYA_CH2_OFFSET 0x0000d500 730*5113495bSYour Name #define SEQ_MSIP_WL_BBCLKGEN_PHYA_CH2_OFFSET 0x0000d600 731*5113495bSYour Name #define SEQ_MSIP_RBIST_TX_BAREBONE_PHYA_CH3_OFFSET 0x0000d800 732*5113495bSYour Name #define SEQ_MSIP_RBIST_RX_PHYA_CH3_OFFSET 0x0000d900 733*5113495bSYour Name #define SEQ_MSIP_WL_DAC_PHYA_CH3_OFFSET 0x0000d980 734*5113495bSYour Name #define SEQ_MSIP_WL_DAC_DIG_CORRECTION_PHYA_CH3_OFFSET 0x0000d9c0 735*5113495bSYour Name #define SEQ_MSIP_WL_DAC_MISC_PHYA_CH3_OFFSET 0x0000dac0 736*5113495bSYour Name #define SEQ_MSIP_WL_ADC_PHYA_CH3_OFFSET 0x0000db40 737*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_I_EVEN_PHYA_CH3_OFFSET 0x0000dc00 738*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_I_ODD_PHYA_CH3_OFFSET 0x0000dc40 739*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_Q_EVEN_PHYA_CH3_OFFSET 0x0000dc80 740*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_Q_ODD_PHYA_CH3_OFFSET 0x0000dcc0 741*5113495bSYour Name #define SEQ_MSIP_WL_ADC_POSTPROC_RO_PHYA_CH3_OFFSET 0x0000dd00 742*5113495bSYour Name #define SEQ_MSIP_WL_BBCLKGEN_PHYA_CH3_OFFSET 0x0000de00 743*5113495bSYour Name 744*5113495bSYour Name 745*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 746*5113495bSYour Name // Instance Relative Offsets from Block wcssdbg 747*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 748*5113495bSYour Name 749*5113495bSYour Name #define SEQ_WCSSDBG_ROM_WCSS_DBG_DAPROM_OFFSET 0x00000000 750*5113495bSYour Name #define SEQ_WCSSDBG_CSR_WCSS_DBG_CSR_OFFSET 0x00001000 751*5113495bSYour Name #define SEQ_WCSSDBG_TSGEN_CXTSGEN_OFFSET 0x00002000 752*5113495bSYour Name #define SEQ_WCSSDBG_CTIDBG_QC_CTI_24T_8CH_OFFSET 0x00004000 753*5113495bSYour Name #define SEQ_WCSSDBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00005000 754*5113495bSYour Name #define SEQ_WCSSDBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00006000 755*5113495bSYour Name #define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_OFFSET 0x00008000 756*5113495bSYour Name #define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00008280 757*5113495bSYour Name #define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00008000 758*5113495bSYour Name #define SEQ_WCSSDBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_OFFSET 0x00009000 759*5113495bSYour Name #define SEQ_WCSSDBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00009280 760*5113495bSYour Name #define SEQ_WCSSDBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00009000 761*5113495bSYour Name #define SEQ_WCSSDBG_TPDA_TPDA_S2_W64_D2_M64_CS4C2456A_OFFSET 0x0000a000 762*5113495bSYour Name #define SEQ_WCSSDBG_FUN_CXATBFUNNEL_128W8SP_OFFSET 0x0000b000 763*5113495bSYour Name #define SEQ_WCSSDBG_TMC_CXTMC_F128W8K_OFFSET 0x0000c000 764*5113495bSYour Name #define SEQ_WCSSDBG_UMACDBG_UMAC_DBG_OFFSET 0x00010000 765*5113495bSYour Name #define SEQ_WCSSDBG_UMACDBG_UMAC_DBG_UNOC_UMAC_NOC_OFFSET 0x00010000 766*5113495bSYour Name #define SEQ_WCSSDBG_UMACDBG_UMAC_DBG_UDBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00018000 767*5113495bSYour Name #define SEQ_WCSSDBG_UMACDBG_UMAC_DBG_UDBG_CTI_QC_CTI_15T_8CH_OFFSET 0x00019000 768*5113495bSYour Name #define SEQ_WCSSDBG_UMACDBG_UMAC_DBG_UDBG_P0_MACDBG_CTRL_OFFSET 0x0001a000 769*5113495bSYour Name #define SEQ_WCSSDBG_UMACDBG_UMAC_DBG_UDBG_P1_MACDBG_CTRL_OFFSET 0x0001b000 770*5113495bSYour Name #define SEQ_WCSSDBG_UMACDBG_UMAC_DBG_UDBG_P2_MACDBG_CTRL_OFFSET 0x0001c000 771*5113495bSYour Name #define SEQ_WCSSDBG_PHYA_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00028000 772*5113495bSYour Name #define SEQ_WCSSDBG_PHYA_CTI_QC_CTI_10T_8CH_OFFSET 0x00029000 773*5113495bSYour Name #define SEQ_WCSSDBG_PHYA_TRC_PHYTRC_CTRL_OFFSET 0x0002a000 774*5113495bSYour Name #define SEQ_WCSSDBG_PHYB_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00038000 775*5113495bSYour Name #define SEQ_WCSSDBG_PHYB_CTI_QC_CTI_10T_8CH_OFFSET 0x00039000 776*5113495bSYour Name #define SEQ_WCSSDBG_PHYB_TRC_PHYTRC_CTRL_OFFSET 0x0003a000 777*5113495bSYour Name #define SEQ_WCSSDBG_PHYB_NOC_PHYB_NOC_OFFSET 0x00030000 778*5113495bSYour Name #define SEQ_WCSSDBG_PHYB_CPU0_M3_AHB_AP_OFFSET 0x0003e000 779*5113495bSYour Name #define SEQ_WCSSDBG_UMAC_CPU_M3_AHB_AP_OFFSET 0x00068000 780*5113495bSYour Name #define SEQ_WCSSDBG_BUS_TIMEOUT_OFFSET 0x00069000 781*5113495bSYour Name 782*5113495bSYour Name 783*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 784*5113495bSYour Name // Instance Relative Offsets from Block tpdm_atb64_cmb40_dsb256_csbe6c04f7 785*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 786*5113495bSYour Name 787*5113495bSYour Name #define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00000280 788*5113495bSYour Name #define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00000000 789*5113495bSYour Name 790*5113495bSYour Name 791*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 792*5113495bSYour Name // Instance Relative Offsets from Block tpdm_atb32_dsb64_csf49237bd 793*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 794*5113495bSYour Name 795*5113495bSYour Name #define SEQ_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00000280 796*5113495bSYour Name #define SEQ_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00000000 797*5113495bSYour Name 798*5113495bSYour Name 799*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 800*5113495bSYour Name // Instance Relative Offsets from Block umac_dbg 801*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 802*5113495bSYour Name 803*5113495bSYour Name #define SEQ_UMAC_DBG_UNOC_UMAC_NOC_OFFSET 0x00000000 804*5113495bSYour Name #define SEQ_UMAC_DBG_UDBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00008000 805*5113495bSYour Name #define SEQ_UMAC_DBG_UDBG_CTI_QC_CTI_15T_8CH_OFFSET 0x00009000 806*5113495bSYour Name #define SEQ_UMAC_DBG_UDBG_P0_MACDBG_CTRL_OFFSET 0x0000a000 807*5113495bSYour Name #define SEQ_UMAC_DBG_UDBG_P1_MACDBG_CTRL_OFFSET 0x0000b000 808*5113495bSYour Name #define SEQ_UMAC_DBG_UDBG_P2_MACDBG_CTRL_OFFSET 0x0000c000 809*5113495bSYour Name 810*5113495bSYour Name 811*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 812*5113495bSYour Name // Instance Relative Offsets from Block qdsp6v67ss_wlan 813*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 814*5113495bSYour Name 815*5113495bSYour Name #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_OFFSET 0x00000000 816*5113495bSYour Name #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET 0x00000000 817*5113495bSYour Name #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00000000 818*5113495bSYour Name #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_OFFSET 0x00080000 819*5113495bSYour Name #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00080000 820*5113495bSYour Name #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00090000 821*5113495bSYour Name #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x000a0000 822*5113495bSYour Name #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x000a1000 823*5113495bSYour Name #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x000a2000 824*5113495bSYour Name #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x000a3000 825*5113495bSYour Name #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x000b0000 826*5113495bSYour Name #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x000b0000 827*5113495bSYour Name 828*5113495bSYour Name 829*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 830*5113495bSYour Name // Instance Relative Offsets from Block qdsp6v67ss 831*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 832*5113495bSYour Name 833*5113495bSYour Name #define SEQ_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET 0x00000000 834*5113495bSYour Name #define SEQ_QDSP6V67SS_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00000000 835*5113495bSYour Name #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_OFFSET 0x00080000 836*5113495bSYour Name #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00080000 837*5113495bSYour Name #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00090000 838*5113495bSYour Name #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x000a0000 839*5113495bSYour Name #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x000a1000 840*5113495bSYour Name #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x000a2000 841*5113495bSYour Name #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x000a3000 842*5113495bSYour Name #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x000b0000 843*5113495bSYour Name #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x000b0000 844*5113495bSYour Name 845*5113495bSYour Name 846*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 847*5113495bSYour Name // Instance Relative Offsets from Block qdsp6v67ss_public 848*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 849*5113495bSYour Name 850*5113495bSYour Name #define SEQ_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00000000 851*5113495bSYour Name 852*5113495bSYour Name 853*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 854*5113495bSYour Name // Instance Relative Offsets from Block qdsp6v67ss_private 855*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 856*5113495bSYour Name 857*5113495bSYour Name #define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00000000 858*5113495bSYour Name #define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00010000 859*5113495bSYour Name #define SEQ_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x00020000 860*5113495bSYour Name #define SEQ_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x00021000 861*5113495bSYour Name #define SEQ_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x00022000 862*5113495bSYour Name #define SEQ_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x00023000 863*5113495bSYour Name #define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x00030000 864*5113495bSYour Name #define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x00030000 865*5113495bSYour Name 866*5113495bSYour Name 867*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 868*5113495bSYour Name // Instance Relative Offsets from Block q6ss_rscc 869*5113495bSYour Name /////////////////////////////////////////////////////////////////////////////////////////////// 870*5113495bSYour Name 871*5113495bSYour Name #define SEQ_Q6SS_RSCC_RSCC_RSC_OFFSET 0x00000000 872*5113495bSYour Name 873*5113495bSYour Name 874*5113495bSYour Name #endif 875*5113495bSYour Name 876