1 /* 2 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 /////////////////////////////////////////////////////////////////////////////////////////////// 18 // 19 // wcss_seq_hwiobase.h : automatically generated by Autoseq 3.10 1/18/2021 20 // User Name:c_bipink 21 // 22 // !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. 23 // 24 /////////////////////////////////////////////////////////////////////////////////////////////// 25 26 #ifndef __WCSS_SEQ_BASE_H__ 27 #define __WCSS_SEQ_BASE_H__ 28 29 #ifdef SCALE_INCLUDES 30 #include "HALhwio.h" 31 #else 32 #include "msmhwio.h" 33 #endif 34 35 36 /////////////////////////////////////////////////////////////////////////////////////////////// 37 // Instance Relative Offsets from Block wcss 38 /////////////////////////////////////////////////////////////////////////////////////////////// 39 40 #define SEQ_WCSS_ECAHB_OFFSET 0x00008000 41 #define SEQ_WCSS_ECAHB_TSLV_OFFSET 0x00009000 42 #define SEQ_WCSS_UMAC_NOC_OFFSET 0x00140000 43 #define SEQ_WCSS_MPSS_OFFSET 0x00200000 44 #define SEQ_WCSS_MPSS_SEG0PDMEM_MPSS_WFAX_PCSS_PDMEM_OFFSET 0x00200000 45 #define SEQ_WCSS_MPSS_SEG0_MPSS_WFAX_PCSS_OFFSET 0x00280000 46 #define SEQ_WCSS_MPSS_SEG0_MPSS_WFAX_PCSS_DUAL_TIMER_OFFSET 0x00281800 47 #define SEQ_WCSS_MPSS_SEG0_MPSS_WFAX_PCSS_WATCHDOG_OFFSET 0x00281c00 48 #define SEQ_WCSS_PHYB_OFFSET 0x00800000 49 #define SEQ_WCSS_PHYB_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET 0x00800000 50 #define SEQ_WCSS_PHYB_WFAX_PCSS_B_REG_MAP_OFFSET 0x00880000 51 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC0_B_REG_MAP_OFFSET 0x00880400 52 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC1_B_REG_MAP_OFFSET 0x00880800 53 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET 0x00880c00 54 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET 0x00881000 55 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET 0x00881400 56 #define SEQ_WCSS_PHYB_WFAX_PCSS_DUAL_TIMER_B_REG_MAP_OFFSET 0x00881800 57 #define SEQ_WCSS_PHYB_WFAX_PCSS_WATCHDOG_B_REG_MAP_OFFSET 0x00881c00 58 #define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC5_B_REG_MAP_OFFSET 0x00882c00 59 #define SEQ_WCSS_PHYB_WFAX_NOC_B_REG_MAP_OFFSET 0x00884000 60 #define SEQ_WCSS_PHYB_WFAX_TXTD_B_REG_MAP_OFFSET 0x00888000 61 #define SEQ_WCSS_PHYB_WFAX_TXBF_B_REG_MAP_OFFSET 0x008e8000 62 #define SEQ_WCSS_PHYB_WFAX_TXFD_B_REG_MAP_OFFSET 0x00918000 63 #define SEQ_WCSS_PHYB_WFAX_ROBE_B_REG_MAP_OFFSET 0x00920000 64 #define SEQ_WCSS_PHYB_WFAX_RXTD_B_REG_MAP_OFFSET 0x00928000 65 #define SEQ_WCSS_PHYB_WFAX_DEMFRONT_B_REG_MAP_OFFSET 0x00930000 66 #define SEQ_WCSS_PHYB_WFAX_PHYRF_B_REG_MAP_OFFSET 0x009a0000 67 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_OFFSET 0x009c0000 68 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_OFFSET 0x009c0000 69 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_RFA_OTP_OFFSET 0x009c0000 70 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_RFA_OTP_CTRL_OFFSET 0x009c0140 71 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_RFA_TLMM_OFFSET 0x009c4000 72 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_DIG_SYSCTRL_OFFSET 0x009c8000 73 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_OFFSET 0x009d4000 74 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_OFFSET 0x009d4000 75 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x009d4300 76 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x009d4800 77 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x009d6000 78 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x009d6040 79 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x009d6080 80 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x009d60c0 81 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x009d6100 82 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x009d6140 83 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x009d6200 84 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x009d6800 85 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x009d6840 86 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x009d6880 87 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x009d68c0 88 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x009d6900 89 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x009d6940 90 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x009d6a00 91 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_DRM_REG_OFFSET 0x009d7c00 92 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_OFFSET 0x009e0000 93 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x009e0000 94 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x009e0400 95 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x009e0800 96 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH0_OFFSET 0x009e1000 97 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH0_OFFSET 0x009e1180 98 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH0_OFFSET 0x009e1300 99 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH0_OFFSET 0x009e1480 100 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x009e1600 101 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_CH0_OFFSET 0x009e1640 102 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x009e2000 103 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH0_OFFSET 0x009e4000 104 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x009e8000 105 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x009e8400 106 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x009e8800 107 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH1_OFFSET 0x009e9000 108 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH1_OFFSET 0x009e9180 109 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH1_OFFSET 0x009e9300 110 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH1_OFFSET 0x009e9480 111 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x009e9600 112 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_CH1_OFFSET 0x009e9640 113 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x009ea000 114 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH1_OFFSET 0x009ec000 115 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH2_OFFSET 0x009f0000 116 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH2_OFFSET 0x009f0400 117 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH2_OFFSET 0x009f0800 118 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH2_OFFSET 0x009f1000 119 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH2_OFFSET 0x009f1180 120 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH2_OFFSET 0x009f1300 121 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH2_OFFSET 0x009f1480 122 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_CH2_OFFSET 0x009f1600 123 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_CH2_OFFSET 0x009f1640 124 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH2_OFFSET 0x009f2000 125 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH2_OFFSET 0x009f4000 126 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH3_OFFSET 0x009f8000 127 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH3_OFFSET 0x009f8400 128 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH3_OFFSET 0x009f8800 129 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH3_OFFSET 0x009f9000 130 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH3_OFFSET 0x009f9180 131 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH3_OFFSET 0x009f9300 132 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH3_OFFSET 0x009f9480 133 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_CH3_OFFSET 0x009f9600 134 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_CH3_OFFSET 0x009f9640 135 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH3_OFFSET 0x009fa000 136 #define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH3_OFFSET 0x009fc000 137 #define SEQ_WCSS_UMAC_OFFSET 0x00a00000 138 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_OFFSET 0x00a00000 139 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00a00000 140 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00a01000 141 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00a02000 142 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00a03000 143 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00a04000 144 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00a05000 145 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00a06000 146 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00a07000 147 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00a08000 148 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00a09000 149 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x00a0a000 150 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x00a0b000 151 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x00a0c000 152 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x00a0d000 153 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x00a0e000 154 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x00a0f000 155 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00a10000 156 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00a11000 157 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00a12000 158 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00a13000 159 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00a14000 160 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00a15000 161 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00a16000 162 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00a17000 163 #define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET 0x00a18000 164 #define SEQ_WCSS_UMAC_CXC_TOP_REG_OFFSET 0x00a20000 165 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00a20000 166 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00a22000 167 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00a24000 168 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00a26000 169 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00a28000 170 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x00a2a000 171 #define SEQ_WCSS_UMAC_MAC_TRACER_REG_OFFSET 0x00a30000 172 #define SEQ_WCSS_UMAC_WBM_REG_OFFSET 0x00a34000 173 #define SEQ_WCSS_UMAC_REO_REG_OFFSET 0x00a38000 174 #define SEQ_WCSS_UMAC_TQM_REG_OFFSET 0x00a3c000 175 #define SEQ_WCSS_UMAC_MAC_UMCMN_REG_OFFSET 0x00a40000 176 #define SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET 0x00a44000 177 #define SEQ_WCSS_UMAC_MAC_CMN_PARSER_REG_OFFSET 0x00a47000 178 #define SEQ_WCSS_UMAC_MAC_CCE_TCL_REG_OFFSET 0x00a4a000 179 #define SEQ_WCSS_WMAC2_OFFSET 0x00b00000 180 #define SEQ_WCSS_WMAC2_MAC_PDG_REG_OFFSET 0x00b00000 181 #define SEQ_WCSS_WMAC2_MAC_TXDMA_REG_OFFSET 0x00b03000 182 #define SEQ_WCSS_WMAC2_MAC_RXDMA_REG_OFFSET 0x00b06000 183 #define SEQ_WCSS_WMAC2_MAC_MCMN_REG_OFFSET 0x00b09000 184 #define SEQ_WCSS_WMAC2_MAC_RXPCU_REG_OFFSET 0x00b0c000 185 #define SEQ_WCSS_WMAC2_MAC_TXPCU_REG_OFFSET 0x00b0f000 186 #define SEQ_WCSS_WMAC2_MAC_AMPI_REG_OFFSET 0x00b12000 187 #define SEQ_WCSS_WMAC2_MAC_RXOLE_REG_OFFSET 0x00b15000 188 #define SEQ_WCSS_WMAC2_MAC_RXOLE_PARSER_REG_OFFSET 0x00b18000 189 #define SEQ_WCSS_WMAC2_MAC_CCE_REG_OFFSET 0x00b1b000 190 #define SEQ_WCSS_WMAC2_MAC_TXOLE_REG_OFFSET 0x00b1e000 191 #define SEQ_WCSS_WMAC2_MAC_TXOLE_PARSER_REG_OFFSET 0x00b21000 192 #define SEQ_WCSS_WMAC2_MAC_RRI_REG_OFFSET 0x00b24000 193 #define SEQ_WCSS_WMAC2_MAC_CRYPTO_REG_OFFSET 0x00b27000 194 #define SEQ_WCSS_WMAC2_MAC_HWSCH_REG_OFFSET 0x00b2a000 195 #define SEQ_WCSS_WMAC2_MAC_MXI_REG_OFFSET 0x00b30000 196 #define SEQ_WCSS_WMAC2_MAC_SFM_REG_OFFSET 0x00b33000 197 #define SEQ_WCSS_WMAC2_MAC_RXDMA1_REG_OFFSET 0x00b36000 198 #define SEQ_WCSS_WMAC2_MAC_LPEC_REG_OFFSET 0x00b39000 199 #define SEQ_WCSS_APB_TSLV_OFFSET 0x00b40000 200 #define SEQ_WCSS_WCMN_OFFSET 0x00b50000 201 #define SEQ_WCSS_WFSS_PMM_OFFSET 0x00b60000 202 #define SEQ_WCSS_MSIP_OFFSET 0x00b80000 203 #define SEQ_WCSS_MSIP_PLL_OFFSET 0x00b80000 204 #define SEQ_WCSS_MSIP_BIASCLKS_OFFSET 0x00b80100 205 #define SEQ_WCSS_MSIP_XO_OFFSET 0x00b84000 206 #define SEQ_WCSS_MSIP_MSIP_OTP_OFFSET 0x00b84140 207 #define SEQ_WCSS_MSIP_RBIST_TX_BAREBONE_PHYA_CH0_OFFSET 0x00b8c000 208 #define SEQ_WCSS_MSIP_RBIST_RX_PHYA_CH0_OFFSET 0x00b8c100 209 #define SEQ_WCSS_MSIP_WL_DAC_PHYA_CH0_OFFSET 0x00b8c180 210 #define SEQ_WCSS_MSIP_WL_DAC_DIG_CORRECTION_PHYA_CH0_OFFSET 0x00b8c1c0 211 #define SEQ_WCSS_MSIP_WL_DAC_MISC_PHYA_CH0_OFFSET 0x00b8c2c0 212 #define SEQ_WCSS_MSIP_WL_ADC_PHYA_CH0_OFFSET 0x00b8c340 213 #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_I_EVEN_PHYA_CH0_OFFSET 0x00b8c400 214 #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_I_ODD_PHYA_CH0_OFFSET 0x00b8c440 215 #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_Q_EVEN_PHYA_CH0_OFFSET 0x00b8c480 216 #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_Q_ODD_PHYA_CH0_OFFSET 0x00b8c4c0 217 #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_RO_PHYA_CH0_OFFSET 0x00b8c500 218 #define SEQ_WCSS_MSIP_WL_BBCLKGEN_PHYA_CH0_OFFSET 0x00b8c600 219 #define SEQ_WCSS_MSIP_RBIST_TX_BAREBONE_PHYA_CH1_OFFSET 0x00b8c800 220 #define SEQ_WCSS_MSIP_RBIST_RX_PHYA_CH1_OFFSET 0x00b8c900 221 #define SEQ_WCSS_MSIP_WL_DAC_PHYA_CH1_OFFSET 0x00b8c980 222 #define SEQ_WCSS_MSIP_WL_DAC_DIG_CORRECTION_PHYA_CH1_OFFSET 0x00b8c9c0 223 #define SEQ_WCSS_MSIP_WL_DAC_MISC_PHYA_CH1_OFFSET 0x00b8cac0 224 #define SEQ_WCSS_MSIP_WL_ADC_PHYA_CH1_OFFSET 0x00b8cb40 225 #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_I_EVEN_PHYA_CH1_OFFSET 0x00b8cc00 226 #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_I_ODD_PHYA_CH1_OFFSET 0x00b8cc40 227 #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_Q_EVEN_PHYA_CH1_OFFSET 0x00b8cc80 228 #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_Q_ODD_PHYA_CH1_OFFSET 0x00b8ccc0 229 #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_RO_PHYA_CH1_OFFSET 0x00b8cd00 230 #define SEQ_WCSS_MSIP_WL_BBCLKGEN_PHYA_CH1_OFFSET 0x00b8ce00 231 #define SEQ_WCSS_MSIP_RBIST_TX_BAREBONE_PHYA_CH2_OFFSET 0x00b8d000 232 #define SEQ_WCSS_MSIP_RBIST_RX_PHYA_CH2_OFFSET 0x00b8d100 233 #define SEQ_WCSS_MSIP_WL_DAC_PHYA_CH2_OFFSET 0x00b8d180 234 #define SEQ_WCSS_MSIP_WL_DAC_DIG_CORRECTION_PHYA_CH2_OFFSET 0x00b8d1c0 235 #define SEQ_WCSS_MSIP_WL_DAC_MISC_PHYA_CH2_OFFSET 0x00b8d2c0 236 #define SEQ_WCSS_MSIP_WL_ADC_PHYA_CH2_OFFSET 0x00b8d340 237 #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_I_EVEN_PHYA_CH2_OFFSET 0x00b8d400 238 #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_I_ODD_PHYA_CH2_OFFSET 0x00b8d440 239 #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_Q_EVEN_PHYA_CH2_OFFSET 0x00b8d480 240 #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_Q_ODD_PHYA_CH2_OFFSET 0x00b8d4c0 241 #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_RO_PHYA_CH2_OFFSET 0x00b8d500 242 #define SEQ_WCSS_MSIP_WL_BBCLKGEN_PHYA_CH2_OFFSET 0x00b8d600 243 #define SEQ_WCSS_MSIP_RBIST_TX_BAREBONE_PHYA_CH3_OFFSET 0x00b8d800 244 #define SEQ_WCSS_MSIP_RBIST_RX_PHYA_CH3_OFFSET 0x00b8d900 245 #define SEQ_WCSS_MSIP_WL_DAC_PHYA_CH3_OFFSET 0x00b8d980 246 #define SEQ_WCSS_MSIP_WL_DAC_DIG_CORRECTION_PHYA_CH3_OFFSET 0x00b8d9c0 247 #define SEQ_WCSS_MSIP_WL_DAC_MISC_PHYA_CH3_OFFSET 0x00b8dac0 248 #define SEQ_WCSS_MSIP_WL_ADC_PHYA_CH3_OFFSET 0x00b8db40 249 #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_I_EVEN_PHYA_CH3_OFFSET 0x00b8dc00 250 #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_I_ODD_PHYA_CH3_OFFSET 0x00b8dc40 251 #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_Q_EVEN_PHYA_CH3_OFFSET 0x00b8dc80 252 #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_Q_ODD_PHYA_CH3_OFFSET 0x00b8dcc0 253 #define SEQ_WCSS_MSIP_WL_ADC_POSTPROC_RO_PHYA_CH3_OFFSET 0x00b8dd00 254 #define SEQ_WCSS_MSIP_WL_BBCLKGEN_PHYA_CH3_OFFSET 0x00b8de00 255 #define SEQ_WCSS_PMM_OFFSET 0x00b70000 256 #define SEQ_WCSS_DBG_OFFSET 0x00b90000 257 #define SEQ_WCSS_DBG_ROM_WCSS_DBG_DAPROM_OFFSET 0x00b90000 258 #define SEQ_WCSS_DBG_CSR_WCSS_DBG_CSR_OFFSET 0x00b91000 259 #define SEQ_WCSS_DBG_TSGEN_CXTSGEN_OFFSET 0x00b92000 260 #define SEQ_WCSS_DBG_CTIDBG_QC_CTI_24T_8CH_OFFSET 0x00b94000 261 #define SEQ_WCSS_DBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00b95000 262 #define SEQ_WCSS_DBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00b96000 263 #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_OFFSET 0x00b98000 264 #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00b98280 265 #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00b98000 266 #define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_OFFSET 0x00b99000 267 #define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00b99280 268 #define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00b99000 269 #define SEQ_WCSS_DBG_TPDA_TPDA_S2_W64_D2_M64_CS4C2456A_OFFSET 0x00b9a000 270 #define SEQ_WCSS_DBG_FUN_CXATBFUNNEL_128W8SP_OFFSET 0x00b9b000 271 #define SEQ_WCSS_DBG_TMC_CXTMC_F128W8K_OFFSET 0x00b9c000 272 #define SEQ_WCSS_DBG_UMACDBG_UMAC_DBG_OFFSET 0x00ba0000 273 #define SEQ_WCSS_DBG_UMACDBG_UMAC_DBG_UNOC_UMAC_NOC_OFFSET 0x00ba0000 274 #define SEQ_WCSS_DBG_UMACDBG_UMAC_DBG_UDBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00ba8000 275 #define SEQ_WCSS_DBG_UMACDBG_UMAC_DBG_UDBG_CTI_QC_CTI_15T_8CH_OFFSET 0x00ba9000 276 #define SEQ_WCSS_DBG_UMACDBG_UMAC_DBG_UDBG_P0_MACDBG_CTRL_OFFSET 0x00baa000 277 #define SEQ_WCSS_DBG_UMACDBG_UMAC_DBG_UDBG_P1_MACDBG_CTRL_OFFSET 0x00bab000 278 #define SEQ_WCSS_DBG_UMACDBG_UMAC_DBG_UDBG_P2_MACDBG_CTRL_OFFSET 0x00bac000 279 #define SEQ_WCSS_DBG_PHYA_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bb8000 280 #define SEQ_WCSS_DBG_PHYA_CTI_QC_CTI_10T_8CH_OFFSET 0x00bb9000 281 #define SEQ_WCSS_DBG_PHYA_TRC_PHYTRC_CTRL_OFFSET 0x00bba000 282 #define SEQ_WCSS_DBG_PHYB_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bc8000 283 #define SEQ_WCSS_DBG_PHYB_CTI_QC_CTI_10T_8CH_OFFSET 0x00bc9000 284 #define SEQ_WCSS_DBG_PHYB_TRC_PHYTRC_CTRL_OFFSET 0x00bca000 285 #define SEQ_WCSS_DBG_PHYB_NOC_PHYB_NOC_OFFSET 0x00bc0000 286 #define SEQ_WCSS_DBG_PHYB_CPU0_M3_AHB_AP_OFFSET 0x00bce000 287 #define SEQ_WCSS_DBG_UMAC_CPU_M3_AHB_AP_OFFSET 0x00bf8000 288 #define SEQ_WCSS_DBG_BUS_TIMEOUT_OFFSET 0x00bf9000 289 #define SEQ_WCSS_RET_AHB_OFFSET 0x00c10000 290 #define SEQ_WCSS_WAHB_TSLV_OFFSET 0x00c20000 291 #define SEQ_WCSS_CC_OFFSET 0x00c30000 292 #define SEQ_WCSS_ACMT_OFFSET 0x00c40000 293 #define SEQ_WCSS_WRAPPER_ACMT_OFFSET 0x00c60000 294 #define SEQ_WCSS_Q6SS_WLAN_OFFSET 0x00d00000 295 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_OFFSET 0x00d00000 296 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET 0x00d00000 297 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00d00000 298 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_OFFSET 0x00d80000 299 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00d80000 300 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00d90000 301 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x00da0000 302 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x00da1000 303 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x00da2000 304 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x00da3000 305 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x00db0000 306 #define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x00db0000 307 308 309 /////////////////////////////////////////////////////////////////////////////////////////////// 310 // Instance Relative Offsets from Block mpss_top 311 /////////////////////////////////////////////////////////////////////////////////////////////// 312 313 #define SEQ_MPSS_TOP_SEG0PDMEM_MPSS_WFAX_PCSS_PDMEM_OFFSET 0x00000000 314 #define SEQ_MPSS_TOP_SEG0_MPSS_WFAX_PCSS_OFFSET 0x00080000 315 #define SEQ_MPSS_TOP_SEG0_MPSS_WFAX_PCSS_DUAL_TIMER_OFFSET 0x00081800 316 #define SEQ_MPSS_TOP_SEG0_MPSS_WFAX_PCSS_WATCHDOG_OFFSET 0x00081c00 317 318 319 /////////////////////////////////////////////////////////////////////////////////////////////// 320 // Instance Relative Offsets from Block wfax_top_b 321 /////////////////////////////////////////////////////////////////////////////////////////////// 322 323 #define SEQ_WFAX_TOP_B_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET 0x00000000 324 #define SEQ_WFAX_TOP_B_WFAX_PCSS_B_REG_MAP_OFFSET 0x00080000 325 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC0_B_REG_MAP_OFFSET 0x00080400 326 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC1_B_REG_MAP_OFFSET 0x00080800 327 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET 0x00080c00 328 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET 0x00081000 329 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET 0x00081400 330 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DUAL_TIMER_B_REG_MAP_OFFSET 0x00081800 331 #define SEQ_WFAX_TOP_B_WFAX_PCSS_WATCHDOG_B_REG_MAP_OFFSET 0x00081c00 332 #define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC5_B_REG_MAP_OFFSET 0x00082c00 333 #define SEQ_WFAX_TOP_B_WFAX_NOC_B_REG_MAP_OFFSET 0x00084000 334 #define SEQ_WFAX_TOP_B_WFAX_TXTD_B_REG_MAP_OFFSET 0x00088000 335 #define SEQ_WFAX_TOP_B_WFAX_TXBF_B_REG_MAP_OFFSET 0x000e8000 336 #define SEQ_WFAX_TOP_B_WFAX_TXFD_B_REG_MAP_OFFSET 0x00118000 337 #define SEQ_WFAX_TOP_B_WFAX_ROBE_B_REG_MAP_OFFSET 0x00120000 338 #define SEQ_WFAX_TOP_B_WFAX_RXTD_B_REG_MAP_OFFSET 0x00128000 339 #define SEQ_WFAX_TOP_B_WFAX_DEMFRONT_B_REG_MAP_OFFSET 0x00130000 340 #define SEQ_WFAX_TOP_B_WFAX_PHYRF_B_REG_MAP_OFFSET 0x001a0000 341 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_OFFSET 0x001c0000 342 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_OFFSET 0x001c0000 343 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_RFA_OTP_OFFSET 0x001c0000 344 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_RFA_OTP_CTRL_OFFSET 0x001c0140 345 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_RFA_TLMM_OFFSET 0x001c4000 346 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_DIG_SYSCTRL_OFFSET 0x001c8000 347 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_OFFSET 0x001d4000 348 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_OFFSET 0x001d4000 349 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x001d4300 350 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x001d4800 351 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x001d6000 352 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x001d6040 353 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x001d6080 354 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x001d60c0 355 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x001d6100 356 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x001d6140 357 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x001d6200 358 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x001d6800 359 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x001d6840 360 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x001d6880 361 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x001d68c0 362 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x001d6900 363 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x001d6940 364 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x001d6a00 365 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_DRM_REG_OFFSET 0x001d7c00 366 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_OFFSET 0x001e0000 367 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x001e0000 368 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x001e0400 369 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x001e0800 370 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH0_OFFSET 0x001e1000 371 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH0_OFFSET 0x001e1180 372 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH0_OFFSET 0x001e1300 373 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH0_OFFSET 0x001e1480 374 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x001e1600 375 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_CH0_OFFSET 0x001e1640 376 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x001e2000 377 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH0_OFFSET 0x001e4000 378 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x001e8000 379 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x001e8400 380 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x001e8800 381 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH1_OFFSET 0x001e9000 382 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH1_OFFSET 0x001e9180 383 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH1_OFFSET 0x001e9300 384 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH1_OFFSET 0x001e9480 385 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x001e9600 386 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_CH1_OFFSET 0x001e9640 387 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x001ea000 388 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH1_OFFSET 0x001ec000 389 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH2_OFFSET 0x001f0000 390 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH2_OFFSET 0x001f0400 391 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH2_OFFSET 0x001f0800 392 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH2_OFFSET 0x001f1000 393 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH2_OFFSET 0x001f1180 394 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH2_OFFSET 0x001f1300 395 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH2_OFFSET 0x001f1480 396 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_CH2_OFFSET 0x001f1600 397 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_CH2_OFFSET 0x001f1640 398 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH2_OFFSET 0x001f2000 399 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH2_OFFSET 0x001f4000 400 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_CH3_OFFSET 0x001f8000 401 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_CH3_OFFSET 0x001f8400 402 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXBB_CH3_OFFSET 0x001f8800 403 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE2_CH3_OFFSET 0x001f9000 404 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXFE5_CH3_OFFSET 0x001f9180 405 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE2_CH3_OFFSET 0x001f9300 406 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE5_CH3_OFFSET 0x001f9480 407 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_PAL_CH3_OFFSET 0x001f9600 408 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_LO_CH3_OFFSET 0x001f9640 409 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_CH3_OFFSET 0x001fa000 410 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_CH3_OFFSET 0x001fc000 411 412 413 /////////////////////////////////////////////////////////////////////////////////////////////// 414 // Instance Relative Offsets from Block iron2g 415 /////////////////////////////////////////////////////////////////////////////////////////////// 416 417 #define SEQ_IRON2G_RFA_DIG_OFFSET 0x00000000 418 #define SEQ_IRON2G_RFA_DIG_RFA_OTP_OFFSET 0x00000000 419 #define SEQ_IRON2G_RFA_DIG_RFA_OTP_CTRL_OFFSET 0x00000140 420 #define SEQ_IRON2G_RFA_DIG_RFA_TLMM_OFFSET 0x00004000 421 #define SEQ_IRON2G_RFA_DIG_SYSCTRL_OFFSET 0x00008000 422 #define SEQ_IRON2G_RFA_CMN_OFFSET 0x00014000 423 #define SEQ_IRON2G_RFA_CMN_AON_OFFSET 0x00014000 424 #define SEQ_IRON2G_RFA_CMN_RFFE_M_OFFSET 0x00014300 425 #define SEQ_IRON2G_RFA_CMN_CLKGEN_OFFSET 0x00014800 426 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00016000 427 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00016040 428 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00016080 429 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x000160c0 430 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00016100 431 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x00016140 432 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00016200 433 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00016800 434 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00016840 435 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x00016880 436 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x000168c0 437 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00016900 438 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x00016940 439 #define SEQ_IRON2G_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x00016a00 440 #define SEQ_IRON2G_RFA_CMN_DRM_REG_OFFSET 0x00017c00 441 #define SEQ_IRON2G_RFA_WL_OFFSET 0x00020000 442 #define SEQ_IRON2G_RFA_WL_WL_MC_CH0_OFFSET 0x00020000 443 #define SEQ_IRON2G_RFA_WL_WL_RXBB_CH0_OFFSET 0x00020400 444 #define SEQ_IRON2G_RFA_WL_WL_TXBB_CH0_OFFSET 0x00020800 445 #define SEQ_IRON2G_RFA_WL_WL_RXFE2_CH0_OFFSET 0x00021000 446 #define SEQ_IRON2G_RFA_WL_WL_RXFE5_CH0_OFFSET 0x00021180 447 #define SEQ_IRON2G_RFA_WL_WL_TXFE2_CH0_OFFSET 0x00021300 448 #define SEQ_IRON2G_RFA_WL_WL_TXFE5_CH0_OFFSET 0x00021480 449 #define SEQ_IRON2G_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x00021600 450 #define SEQ_IRON2G_RFA_WL_WL_LO_CH0_OFFSET 0x00021640 451 #define SEQ_IRON2G_RFA_WL_WL_TPC_CH0_OFFSET 0x00022000 452 #define SEQ_IRON2G_RFA_WL_WL_MEM_CH0_OFFSET 0x00024000 453 #define SEQ_IRON2G_RFA_WL_WL_MC_CH1_OFFSET 0x00028000 454 #define SEQ_IRON2G_RFA_WL_WL_RXBB_CH1_OFFSET 0x00028400 455 #define SEQ_IRON2G_RFA_WL_WL_TXBB_CH1_OFFSET 0x00028800 456 #define SEQ_IRON2G_RFA_WL_WL_RXFE2_CH1_OFFSET 0x00029000 457 #define SEQ_IRON2G_RFA_WL_WL_RXFE5_CH1_OFFSET 0x00029180 458 #define SEQ_IRON2G_RFA_WL_WL_TXFE2_CH1_OFFSET 0x00029300 459 #define SEQ_IRON2G_RFA_WL_WL_TXFE5_CH1_OFFSET 0x00029480 460 #define SEQ_IRON2G_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x00029600 461 #define SEQ_IRON2G_RFA_WL_WL_LO_CH1_OFFSET 0x00029640 462 #define SEQ_IRON2G_RFA_WL_WL_TPC_CH1_OFFSET 0x0002a000 463 #define SEQ_IRON2G_RFA_WL_WL_MEM_CH1_OFFSET 0x0002c000 464 #define SEQ_IRON2G_RFA_WL_WL_MC_CH2_OFFSET 0x00030000 465 #define SEQ_IRON2G_RFA_WL_WL_RXBB_CH2_OFFSET 0x00030400 466 #define SEQ_IRON2G_RFA_WL_WL_TXBB_CH2_OFFSET 0x00030800 467 #define SEQ_IRON2G_RFA_WL_WL_RXFE2_CH2_OFFSET 0x00031000 468 #define SEQ_IRON2G_RFA_WL_WL_RXFE5_CH2_OFFSET 0x00031180 469 #define SEQ_IRON2G_RFA_WL_WL_TXFE2_CH2_OFFSET 0x00031300 470 #define SEQ_IRON2G_RFA_WL_WL_TXFE5_CH2_OFFSET 0x00031480 471 #define SEQ_IRON2G_RFA_WL_WL_LO_PAL_CH2_OFFSET 0x00031600 472 #define SEQ_IRON2G_RFA_WL_WL_LO_CH2_OFFSET 0x00031640 473 #define SEQ_IRON2G_RFA_WL_WL_TPC_CH2_OFFSET 0x00032000 474 #define SEQ_IRON2G_RFA_WL_WL_MEM_CH2_OFFSET 0x00034000 475 #define SEQ_IRON2G_RFA_WL_WL_MC_CH3_OFFSET 0x00038000 476 #define SEQ_IRON2G_RFA_WL_WL_RXBB_CH3_OFFSET 0x00038400 477 #define SEQ_IRON2G_RFA_WL_WL_TXBB_CH3_OFFSET 0x00038800 478 #define SEQ_IRON2G_RFA_WL_WL_RXFE2_CH3_OFFSET 0x00039000 479 #define SEQ_IRON2G_RFA_WL_WL_RXFE5_CH3_OFFSET 0x00039180 480 #define SEQ_IRON2G_RFA_WL_WL_TXFE2_CH3_OFFSET 0x00039300 481 #define SEQ_IRON2G_RFA_WL_WL_TXFE5_CH3_OFFSET 0x00039480 482 #define SEQ_IRON2G_RFA_WL_WL_LO_PAL_CH3_OFFSET 0x00039600 483 #define SEQ_IRON2G_RFA_WL_WL_LO_CH3_OFFSET 0x00039640 484 #define SEQ_IRON2G_RFA_WL_WL_TPC_CH3_OFFSET 0x0003a000 485 #define SEQ_IRON2G_RFA_WL_WL_MEM_CH3_OFFSET 0x0003c000 486 487 488 /////////////////////////////////////////////////////////////////////////////////////////////// 489 // Instance Relative Offsets from Block rfa_dig 490 /////////////////////////////////////////////////////////////////////////////////////////////// 491 492 #define SEQ_RFA_DIG_RFA_OTP_OFFSET 0x00000000 493 #define SEQ_RFA_DIG_RFA_OTP_CTRL_OFFSET 0x00000140 494 #define SEQ_RFA_DIG_RFA_TLMM_OFFSET 0x00004000 495 #define SEQ_RFA_DIG_SYSCTRL_OFFSET 0x00008000 496 497 498 /////////////////////////////////////////////////////////////////////////////////////////////// 499 // Instance Relative Offsets from Block rfa_cmn 500 /////////////////////////////////////////////////////////////////////////////////////////////// 501 502 #define SEQ_RFA_CMN_AON_OFFSET 0x00000000 503 #define SEQ_RFA_CMN_RFFE_M_OFFSET 0x00000300 504 #define SEQ_RFA_CMN_CLKGEN_OFFSET 0x00000800 505 #define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00002000 506 #define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00002040 507 #define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00002080 508 #define SEQ_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x000020c0 509 #define SEQ_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00002100 510 #define SEQ_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x00002140 511 #define SEQ_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00002200 512 #define SEQ_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00002800 513 #define SEQ_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00002840 514 #define SEQ_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x00002880 515 #define SEQ_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x000028c0 516 #define SEQ_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00002900 517 #define SEQ_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x00002940 518 #define SEQ_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x00002a00 519 #define SEQ_RFA_CMN_DRM_REG_OFFSET 0x00003c00 520 521 522 /////////////////////////////////////////////////////////////////////////////////////////////// 523 // Instance Relative Offsets from Block rfa_wl 524 /////////////////////////////////////////////////////////////////////////////////////////////// 525 526 #define SEQ_RFA_WL_WL_MC_CH0_OFFSET 0x00000000 527 #define SEQ_RFA_WL_WL_RXBB_CH0_OFFSET 0x00000400 528 #define SEQ_RFA_WL_WL_TXBB_CH0_OFFSET 0x00000800 529 #define SEQ_RFA_WL_WL_RXFE2_CH0_OFFSET 0x00001000 530 #define SEQ_RFA_WL_WL_RXFE5_CH0_OFFSET 0x00001180 531 #define SEQ_RFA_WL_WL_TXFE2_CH0_OFFSET 0x00001300 532 #define SEQ_RFA_WL_WL_TXFE5_CH0_OFFSET 0x00001480 533 #define SEQ_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x00001600 534 #define SEQ_RFA_WL_WL_LO_CH0_OFFSET 0x00001640 535 #define SEQ_RFA_WL_WL_TPC_CH0_OFFSET 0x00002000 536 #define SEQ_RFA_WL_WL_MEM_CH0_OFFSET 0x00004000 537 #define SEQ_RFA_WL_WL_MC_CH1_OFFSET 0x00008000 538 #define SEQ_RFA_WL_WL_RXBB_CH1_OFFSET 0x00008400 539 #define SEQ_RFA_WL_WL_TXBB_CH1_OFFSET 0x00008800 540 #define SEQ_RFA_WL_WL_RXFE2_CH1_OFFSET 0x00009000 541 #define SEQ_RFA_WL_WL_RXFE5_CH1_OFFSET 0x00009180 542 #define SEQ_RFA_WL_WL_TXFE2_CH1_OFFSET 0x00009300 543 #define SEQ_RFA_WL_WL_TXFE5_CH1_OFFSET 0x00009480 544 #define SEQ_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x00009600 545 #define SEQ_RFA_WL_WL_LO_CH1_OFFSET 0x00009640 546 #define SEQ_RFA_WL_WL_TPC_CH1_OFFSET 0x0000a000 547 #define SEQ_RFA_WL_WL_MEM_CH1_OFFSET 0x0000c000 548 #define SEQ_RFA_WL_WL_MC_CH2_OFFSET 0x00010000 549 #define SEQ_RFA_WL_WL_RXBB_CH2_OFFSET 0x00010400 550 #define SEQ_RFA_WL_WL_TXBB_CH2_OFFSET 0x00010800 551 #define SEQ_RFA_WL_WL_RXFE2_CH2_OFFSET 0x00011000 552 #define SEQ_RFA_WL_WL_RXFE5_CH2_OFFSET 0x00011180 553 #define SEQ_RFA_WL_WL_TXFE2_CH2_OFFSET 0x00011300 554 #define SEQ_RFA_WL_WL_TXFE5_CH2_OFFSET 0x00011480 555 #define SEQ_RFA_WL_WL_LO_PAL_CH2_OFFSET 0x00011600 556 #define SEQ_RFA_WL_WL_LO_CH2_OFFSET 0x00011640 557 #define SEQ_RFA_WL_WL_TPC_CH2_OFFSET 0x00012000 558 #define SEQ_RFA_WL_WL_MEM_CH2_OFFSET 0x00014000 559 #define SEQ_RFA_WL_WL_MC_CH3_OFFSET 0x00018000 560 #define SEQ_RFA_WL_WL_RXBB_CH3_OFFSET 0x00018400 561 #define SEQ_RFA_WL_WL_TXBB_CH3_OFFSET 0x00018800 562 #define SEQ_RFA_WL_WL_RXFE2_CH3_OFFSET 0x00019000 563 #define SEQ_RFA_WL_WL_RXFE5_CH3_OFFSET 0x00019180 564 #define SEQ_RFA_WL_WL_TXFE2_CH3_OFFSET 0x00019300 565 #define SEQ_RFA_WL_WL_TXFE5_CH3_OFFSET 0x00019480 566 #define SEQ_RFA_WL_WL_LO_PAL_CH3_OFFSET 0x00019600 567 #define SEQ_RFA_WL_WL_LO_CH3_OFFSET 0x00019640 568 #define SEQ_RFA_WL_WL_TPC_CH3_OFFSET 0x0001a000 569 #define SEQ_RFA_WL_WL_MEM_CH3_OFFSET 0x0001c000 570 571 572 /////////////////////////////////////////////////////////////////////////////////////////////// 573 // Instance Relative Offsets from Block umac_top_reg 574 /////////////////////////////////////////////////////////////////////////////////////////////// 575 576 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_OFFSET 0x00000000 577 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00000000 578 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00001000 579 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00002000 580 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00003000 581 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00004000 582 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00005000 583 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00006000 584 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00007000 585 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00008000 586 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00009000 587 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x0000a000 588 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x0000b000 589 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x0000c000 590 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x0000d000 591 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x0000e000 592 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x0000f000 593 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00010000 594 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00011000 595 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00012000 596 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00013000 597 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00014000 598 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00015000 599 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00016000 600 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00017000 601 #define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET 0x00018000 602 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_OFFSET 0x00020000 603 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00020000 604 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00022000 605 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00024000 606 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00026000 607 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00028000 608 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0002a000 609 #define SEQ_UMAC_TOP_REG_MAC_TRACER_REG_OFFSET 0x00030000 610 #define SEQ_UMAC_TOP_REG_WBM_REG_OFFSET 0x00034000 611 #define SEQ_UMAC_TOP_REG_REO_REG_OFFSET 0x00038000 612 #define SEQ_UMAC_TOP_REG_TQM_REG_OFFSET 0x0003c000 613 #define SEQ_UMAC_TOP_REG_MAC_UMCMN_REG_OFFSET 0x00040000 614 #define SEQ_UMAC_TOP_REG_MAC_TCL_REG_OFFSET 0x00044000 615 #define SEQ_UMAC_TOP_REG_MAC_CMN_PARSER_REG_OFFSET 0x00047000 616 #define SEQ_UMAC_TOP_REG_MAC_CCE_TCL_REG_OFFSET 0x0004a000 617 618 619 /////////////////////////////////////////////////////////////////////////////////////////////// 620 // Instance Relative Offsets from Block wfss_ce_reg 621 /////////////////////////////////////////////////////////////////////////////////////////////// 622 623 #define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00000000 624 #define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00001000 625 #define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00002000 626 #define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00003000 627 #define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00004000 628 #define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00005000 629 #define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00006000 630 #define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00007000 631 #define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00008000 632 #define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00009000 633 #define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x0000a000 634 #define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x0000b000 635 #define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x0000c000 636 #define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x0000d000 637 #define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x0000e000 638 #define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x0000f000 639 #define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00010000 640 #define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00011000 641 #define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00012000 642 #define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00013000 643 #define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00014000 644 #define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00015000 645 #define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00016000 646 #define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00017000 647 #define SEQ_WFSS_CE_REG_WFSS_CE_COMMON_REG_OFFSET 0x00018000 648 649 650 /////////////////////////////////////////////////////////////////////////////////////////////// 651 // Instance Relative Offsets from Block cxc_top_reg 652 /////////////////////////////////////////////////////////////////////////////////////////////// 653 654 #define SEQ_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00000000 655 #define SEQ_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00002000 656 #define SEQ_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00004000 657 #define SEQ_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00006000 658 #define SEQ_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00008000 659 #define SEQ_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0000a000 660 661 662 /////////////////////////////////////////////////////////////////////////////////////////////// 663 // Instance Relative Offsets from Block wmac_top_reg 664 /////////////////////////////////////////////////////////////////////////////////////////////// 665 666 #define SEQ_WMAC_TOP_REG_MAC_PDG_REG_OFFSET 0x00000000 667 #define SEQ_WMAC_TOP_REG_MAC_TXDMA_REG_OFFSET 0x00003000 668 #define SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET 0x00006000 669 #define SEQ_WMAC_TOP_REG_MAC_MCMN_REG_OFFSET 0x00009000 670 #define SEQ_WMAC_TOP_REG_MAC_RXPCU_REG_OFFSET 0x0000c000 671 #define SEQ_WMAC_TOP_REG_MAC_TXPCU_REG_OFFSET 0x0000f000 672 #define SEQ_WMAC_TOP_REG_MAC_AMPI_REG_OFFSET 0x00012000 673 #define SEQ_WMAC_TOP_REG_MAC_RXOLE_REG_OFFSET 0x00015000 674 #define SEQ_WMAC_TOP_REG_MAC_RXOLE_PARSER_REG_OFFSET 0x00018000 675 #define SEQ_WMAC_TOP_REG_MAC_CCE_REG_OFFSET 0x0001b000 676 #define SEQ_WMAC_TOP_REG_MAC_TXOLE_REG_OFFSET 0x0001e000 677 #define SEQ_WMAC_TOP_REG_MAC_TXOLE_PARSER_REG_OFFSET 0x00021000 678 #define SEQ_WMAC_TOP_REG_MAC_RRI_REG_OFFSET 0x00024000 679 #define SEQ_WMAC_TOP_REG_MAC_CRYPTO_REG_OFFSET 0x00027000 680 #define SEQ_WMAC_TOP_REG_MAC_HWSCH_REG_OFFSET 0x0002a000 681 #define SEQ_WMAC_TOP_REG_MAC_MXI_REG_OFFSET 0x00030000 682 #define SEQ_WMAC_TOP_REG_MAC_SFM_REG_OFFSET 0x00033000 683 #define SEQ_WMAC_TOP_REG_MAC_RXDMA1_REG_OFFSET 0x00036000 684 #define SEQ_WMAC_TOP_REG_MAC_LPEC_REG_OFFSET 0x00039000 685 686 687 /////////////////////////////////////////////////////////////////////////////////////////////// 688 // Instance Relative Offsets from Block msip 689 /////////////////////////////////////////////////////////////////////////////////////////////// 690 691 #define SEQ_MSIP_PLL_OFFSET 0x00000000 692 #define SEQ_MSIP_BIASCLKS_OFFSET 0x00000100 693 #define SEQ_MSIP_XO_OFFSET 0x00004000 694 #define SEQ_MSIP_MSIP_OTP_OFFSET 0x00004140 695 #define SEQ_MSIP_RBIST_TX_BAREBONE_PHYA_CH0_OFFSET 0x0000c000 696 #define SEQ_MSIP_RBIST_RX_PHYA_CH0_OFFSET 0x0000c100 697 #define SEQ_MSIP_WL_DAC_PHYA_CH0_OFFSET 0x0000c180 698 #define SEQ_MSIP_WL_DAC_DIG_CORRECTION_PHYA_CH0_OFFSET 0x0000c1c0 699 #define SEQ_MSIP_WL_DAC_MISC_PHYA_CH0_OFFSET 0x0000c2c0 700 #define SEQ_MSIP_WL_ADC_PHYA_CH0_OFFSET 0x0000c340 701 #define SEQ_MSIP_WL_ADC_POSTPROC_I_EVEN_PHYA_CH0_OFFSET 0x0000c400 702 #define SEQ_MSIP_WL_ADC_POSTPROC_I_ODD_PHYA_CH0_OFFSET 0x0000c440 703 #define SEQ_MSIP_WL_ADC_POSTPROC_Q_EVEN_PHYA_CH0_OFFSET 0x0000c480 704 #define SEQ_MSIP_WL_ADC_POSTPROC_Q_ODD_PHYA_CH0_OFFSET 0x0000c4c0 705 #define SEQ_MSIP_WL_ADC_POSTPROC_RO_PHYA_CH0_OFFSET 0x0000c500 706 #define SEQ_MSIP_WL_BBCLKGEN_PHYA_CH0_OFFSET 0x0000c600 707 #define SEQ_MSIP_RBIST_TX_BAREBONE_PHYA_CH1_OFFSET 0x0000c800 708 #define SEQ_MSIP_RBIST_RX_PHYA_CH1_OFFSET 0x0000c900 709 #define SEQ_MSIP_WL_DAC_PHYA_CH1_OFFSET 0x0000c980 710 #define SEQ_MSIP_WL_DAC_DIG_CORRECTION_PHYA_CH1_OFFSET 0x0000c9c0 711 #define SEQ_MSIP_WL_DAC_MISC_PHYA_CH1_OFFSET 0x0000cac0 712 #define SEQ_MSIP_WL_ADC_PHYA_CH1_OFFSET 0x0000cb40 713 #define SEQ_MSIP_WL_ADC_POSTPROC_I_EVEN_PHYA_CH1_OFFSET 0x0000cc00 714 #define SEQ_MSIP_WL_ADC_POSTPROC_I_ODD_PHYA_CH1_OFFSET 0x0000cc40 715 #define SEQ_MSIP_WL_ADC_POSTPROC_Q_EVEN_PHYA_CH1_OFFSET 0x0000cc80 716 #define SEQ_MSIP_WL_ADC_POSTPROC_Q_ODD_PHYA_CH1_OFFSET 0x0000ccc0 717 #define SEQ_MSIP_WL_ADC_POSTPROC_RO_PHYA_CH1_OFFSET 0x0000cd00 718 #define SEQ_MSIP_WL_BBCLKGEN_PHYA_CH1_OFFSET 0x0000ce00 719 #define SEQ_MSIP_RBIST_TX_BAREBONE_PHYA_CH2_OFFSET 0x0000d000 720 #define SEQ_MSIP_RBIST_RX_PHYA_CH2_OFFSET 0x0000d100 721 #define SEQ_MSIP_WL_DAC_PHYA_CH2_OFFSET 0x0000d180 722 #define SEQ_MSIP_WL_DAC_DIG_CORRECTION_PHYA_CH2_OFFSET 0x0000d1c0 723 #define SEQ_MSIP_WL_DAC_MISC_PHYA_CH2_OFFSET 0x0000d2c0 724 #define SEQ_MSIP_WL_ADC_PHYA_CH2_OFFSET 0x0000d340 725 #define SEQ_MSIP_WL_ADC_POSTPROC_I_EVEN_PHYA_CH2_OFFSET 0x0000d400 726 #define SEQ_MSIP_WL_ADC_POSTPROC_I_ODD_PHYA_CH2_OFFSET 0x0000d440 727 #define SEQ_MSIP_WL_ADC_POSTPROC_Q_EVEN_PHYA_CH2_OFFSET 0x0000d480 728 #define SEQ_MSIP_WL_ADC_POSTPROC_Q_ODD_PHYA_CH2_OFFSET 0x0000d4c0 729 #define SEQ_MSIP_WL_ADC_POSTPROC_RO_PHYA_CH2_OFFSET 0x0000d500 730 #define SEQ_MSIP_WL_BBCLKGEN_PHYA_CH2_OFFSET 0x0000d600 731 #define SEQ_MSIP_RBIST_TX_BAREBONE_PHYA_CH3_OFFSET 0x0000d800 732 #define SEQ_MSIP_RBIST_RX_PHYA_CH3_OFFSET 0x0000d900 733 #define SEQ_MSIP_WL_DAC_PHYA_CH3_OFFSET 0x0000d980 734 #define SEQ_MSIP_WL_DAC_DIG_CORRECTION_PHYA_CH3_OFFSET 0x0000d9c0 735 #define SEQ_MSIP_WL_DAC_MISC_PHYA_CH3_OFFSET 0x0000dac0 736 #define SEQ_MSIP_WL_ADC_PHYA_CH3_OFFSET 0x0000db40 737 #define SEQ_MSIP_WL_ADC_POSTPROC_I_EVEN_PHYA_CH3_OFFSET 0x0000dc00 738 #define SEQ_MSIP_WL_ADC_POSTPROC_I_ODD_PHYA_CH3_OFFSET 0x0000dc40 739 #define SEQ_MSIP_WL_ADC_POSTPROC_Q_EVEN_PHYA_CH3_OFFSET 0x0000dc80 740 #define SEQ_MSIP_WL_ADC_POSTPROC_Q_ODD_PHYA_CH3_OFFSET 0x0000dcc0 741 #define SEQ_MSIP_WL_ADC_POSTPROC_RO_PHYA_CH3_OFFSET 0x0000dd00 742 #define SEQ_MSIP_WL_BBCLKGEN_PHYA_CH3_OFFSET 0x0000de00 743 744 745 /////////////////////////////////////////////////////////////////////////////////////////////// 746 // Instance Relative Offsets from Block wcssdbg 747 /////////////////////////////////////////////////////////////////////////////////////////////// 748 749 #define SEQ_WCSSDBG_ROM_WCSS_DBG_DAPROM_OFFSET 0x00000000 750 #define SEQ_WCSSDBG_CSR_WCSS_DBG_CSR_OFFSET 0x00001000 751 #define SEQ_WCSSDBG_TSGEN_CXTSGEN_OFFSET 0x00002000 752 #define SEQ_WCSSDBG_CTIDBG_QC_CTI_24T_8CH_OFFSET 0x00004000 753 #define SEQ_WCSSDBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00005000 754 #define SEQ_WCSSDBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00006000 755 #define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_OFFSET 0x00008000 756 #define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00008280 757 #define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00008000 758 #define SEQ_WCSSDBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_OFFSET 0x00009000 759 #define SEQ_WCSSDBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00009280 760 #define SEQ_WCSSDBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00009000 761 #define SEQ_WCSSDBG_TPDA_TPDA_S2_W64_D2_M64_CS4C2456A_OFFSET 0x0000a000 762 #define SEQ_WCSSDBG_FUN_CXATBFUNNEL_128W8SP_OFFSET 0x0000b000 763 #define SEQ_WCSSDBG_TMC_CXTMC_F128W8K_OFFSET 0x0000c000 764 #define SEQ_WCSSDBG_UMACDBG_UMAC_DBG_OFFSET 0x00010000 765 #define SEQ_WCSSDBG_UMACDBG_UMAC_DBG_UNOC_UMAC_NOC_OFFSET 0x00010000 766 #define SEQ_WCSSDBG_UMACDBG_UMAC_DBG_UDBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00018000 767 #define SEQ_WCSSDBG_UMACDBG_UMAC_DBG_UDBG_CTI_QC_CTI_15T_8CH_OFFSET 0x00019000 768 #define SEQ_WCSSDBG_UMACDBG_UMAC_DBG_UDBG_P0_MACDBG_CTRL_OFFSET 0x0001a000 769 #define SEQ_WCSSDBG_UMACDBG_UMAC_DBG_UDBG_P1_MACDBG_CTRL_OFFSET 0x0001b000 770 #define SEQ_WCSSDBG_UMACDBG_UMAC_DBG_UDBG_P2_MACDBG_CTRL_OFFSET 0x0001c000 771 #define SEQ_WCSSDBG_PHYA_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00028000 772 #define SEQ_WCSSDBG_PHYA_CTI_QC_CTI_10T_8CH_OFFSET 0x00029000 773 #define SEQ_WCSSDBG_PHYA_TRC_PHYTRC_CTRL_OFFSET 0x0002a000 774 #define SEQ_WCSSDBG_PHYB_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00038000 775 #define SEQ_WCSSDBG_PHYB_CTI_QC_CTI_10T_8CH_OFFSET 0x00039000 776 #define SEQ_WCSSDBG_PHYB_TRC_PHYTRC_CTRL_OFFSET 0x0003a000 777 #define SEQ_WCSSDBG_PHYB_NOC_PHYB_NOC_OFFSET 0x00030000 778 #define SEQ_WCSSDBG_PHYB_CPU0_M3_AHB_AP_OFFSET 0x0003e000 779 #define SEQ_WCSSDBG_UMAC_CPU_M3_AHB_AP_OFFSET 0x00068000 780 #define SEQ_WCSSDBG_BUS_TIMEOUT_OFFSET 0x00069000 781 782 783 /////////////////////////////////////////////////////////////////////////////////////////////// 784 // Instance Relative Offsets from Block tpdm_atb64_cmb40_dsb256_csbe6c04f7 785 /////////////////////////////////////////////////////////////////////////////////////////////// 786 787 #define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00000280 788 #define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00000000 789 790 791 /////////////////////////////////////////////////////////////////////////////////////////////// 792 // Instance Relative Offsets from Block tpdm_atb32_dsb64_csf49237bd 793 /////////////////////////////////////////////////////////////////////////////////////////////// 794 795 #define SEQ_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00000280 796 #define SEQ_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00000000 797 798 799 /////////////////////////////////////////////////////////////////////////////////////////////// 800 // Instance Relative Offsets from Block umac_dbg 801 /////////////////////////////////////////////////////////////////////////////////////////////// 802 803 #define SEQ_UMAC_DBG_UNOC_UMAC_NOC_OFFSET 0x00000000 804 #define SEQ_UMAC_DBG_UDBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00008000 805 #define SEQ_UMAC_DBG_UDBG_CTI_QC_CTI_15T_8CH_OFFSET 0x00009000 806 #define SEQ_UMAC_DBG_UDBG_P0_MACDBG_CTRL_OFFSET 0x0000a000 807 #define SEQ_UMAC_DBG_UDBG_P1_MACDBG_CTRL_OFFSET 0x0000b000 808 #define SEQ_UMAC_DBG_UDBG_P2_MACDBG_CTRL_OFFSET 0x0000c000 809 810 811 /////////////////////////////////////////////////////////////////////////////////////////////// 812 // Instance Relative Offsets from Block qdsp6v67ss_wlan 813 /////////////////////////////////////////////////////////////////////////////////////////////// 814 815 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_OFFSET 0x00000000 816 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET 0x00000000 817 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00000000 818 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_OFFSET 0x00080000 819 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00080000 820 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00090000 821 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x000a0000 822 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x000a1000 823 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x000a2000 824 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x000a3000 825 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x000b0000 826 #define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x000b0000 827 828 829 /////////////////////////////////////////////////////////////////////////////////////////////// 830 // Instance Relative Offsets from Block qdsp6v67ss 831 /////////////////////////////////////////////////////////////////////////////////////////////// 832 833 #define SEQ_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET 0x00000000 834 #define SEQ_QDSP6V67SS_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00000000 835 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_OFFSET 0x00080000 836 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00080000 837 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00090000 838 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x000a0000 839 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x000a1000 840 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x000a2000 841 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x000a3000 842 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x000b0000 843 #define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x000b0000 844 845 846 /////////////////////////////////////////////////////////////////////////////////////////////// 847 // Instance Relative Offsets from Block qdsp6v67ss_public 848 /////////////////////////////////////////////////////////////////////////////////////////////// 849 850 #define SEQ_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00000000 851 852 853 /////////////////////////////////////////////////////////////////////////////////////////////// 854 // Instance Relative Offsets from Block qdsp6v67ss_private 855 /////////////////////////////////////////////////////////////////////////////////////////////// 856 857 #define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00000000 858 #define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00010000 859 #define SEQ_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x00020000 860 #define SEQ_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x00021000 861 #define SEQ_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x00022000 862 #define SEQ_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x00023000 863 #define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x00030000 864 #define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x00030000 865 866 867 /////////////////////////////////////////////////////////////////////////////////////////////// 868 // Instance Relative Offsets from Block q6ss_rscc 869 /////////////////////////////////////////////////////////////////////////////////////////////// 870 871 #define SEQ_Q6SS_RSCC_RSCC_RSC_OFFSET 0x00000000 872 873 874 #endif 875 876