xref: /wlan-driver/fw-api/hw/qcc2072/v1/he_sig_b1_mu_info.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 
18 #ifndef _HE_SIG_B1_MU_INFO_H_
19 #define _HE_SIG_B1_MU_INFO_H_
20 
21 #define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1
22 
23 struct he_sig_b1_mu_info {
24 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
25              uint32_t ru_allocation                                           :  8,
26                       reserved_0                                              : 23,
27                       rx_integrity_check_passed                               :  1;
28 #else
29              uint32_t rx_integrity_check_passed                               :  1,
30                       reserved_0                                              : 23,
31                       ru_allocation                                           :  8;
32 #endif
33 };
34 
35 #define HE_SIG_B1_MU_INFO_RU_ALLOCATION_OFFSET                                      0x00000000
36 #define HE_SIG_B1_MU_INFO_RU_ALLOCATION_LSB                                         0
37 #define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MSB                                         7
38 #define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MASK                                        0x000000ff
39 
40 #define HE_SIG_B1_MU_INFO_RESERVED_0_OFFSET                                         0x00000000
41 #define HE_SIG_B1_MU_INFO_RESERVED_0_LSB                                            8
42 #define HE_SIG_B1_MU_INFO_RESERVED_0_MSB                                            30
43 #define HE_SIG_B1_MU_INFO_RESERVED_0_MASK                                           0x7fffff00
44 
45 #define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                          0x00000000
46 #define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                             31
47 #define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                             31
48 #define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                            0x80000000
49 
50 #endif
51