1 /* 2 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _REO_FLUSH_CACHE_STATUS_H_ 19 #define _REO_FLUSH_CACHE_STATUS_H_ 20 21 #include "uniform_reo_status_header.h" 22 #define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 27 23 24 struct reo_flush_cache_status { 25 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 26 uint32_t tlv32_ring_padding : 32; 27 struct uniform_reo_status_header status_header; 28 uint32_t error_detected : 1, 29 block_error_details : 2, 30 reserved_2a : 5, 31 cache_controller_flush_status_hit : 1, 32 cache_controller_flush_status_desc_type : 3, 33 cache_controller_flush_status_client_id : 4, 34 cache_controller_flush_status_error : 2, 35 cache_controller_flush_count : 8, 36 flush_queue_1k_desc : 1, 37 reserved_2b : 5; 38 uint32_t reserved_3a : 32; 39 uint32_t reserved_4a : 32; 40 uint32_t reserved_5a : 32; 41 uint32_t reserved_6a : 32; 42 uint32_t reserved_7a : 32; 43 uint32_t reserved_8a : 32; 44 uint32_t reserved_9a : 32; 45 uint32_t reserved_10a : 32; 46 uint32_t reserved_11a : 32; 47 uint32_t reserved_12a : 32; 48 uint32_t reserved_13a : 32; 49 uint32_t reserved_14a : 32; 50 uint32_t reserved_15a : 32; 51 uint32_t reserved_16a : 32; 52 uint32_t reserved_17a : 32; 53 uint32_t reserved_18a : 32; 54 uint32_t reserved_19a : 32; 55 uint32_t reserved_20a : 32; 56 uint32_t reserved_21a : 32; 57 uint32_t reserved_22a : 32; 58 uint32_t reserved_23a : 32; 59 uint32_t reserved_24a : 32; 60 uint32_t reserved_25a : 28, 61 looping_count : 4; 62 #else 63 uint32_t tlv32_ring_padding : 32; 64 struct uniform_reo_status_header status_header; 65 uint32_t reserved_2b : 5, 66 flush_queue_1k_desc : 1, 67 cache_controller_flush_count : 8, 68 cache_controller_flush_status_error : 2, 69 cache_controller_flush_status_client_id : 4, 70 cache_controller_flush_status_desc_type : 3, 71 cache_controller_flush_status_hit : 1, 72 reserved_2a : 5, 73 block_error_details : 2, 74 error_detected : 1; 75 uint32_t reserved_3a : 32; 76 uint32_t reserved_4a : 32; 77 uint32_t reserved_5a : 32; 78 uint32_t reserved_6a : 32; 79 uint32_t reserved_7a : 32; 80 uint32_t reserved_8a : 32; 81 uint32_t reserved_9a : 32; 82 uint32_t reserved_10a : 32; 83 uint32_t reserved_11a : 32; 84 uint32_t reserved_12a : 32; 85 uint32_t reserved_13a : 32; 86 uint32_t reserved_14a : 32; 87 uint32_t reserved_15a : 32; 88 uint32_t reserved_16a : 32; 89 uint32_t reserved_17a : 32; 90 uint32_t reserved_18a : 32; 91 uint32_t reserved_19a : 32; 92 uint32_t reserved_20a : 32; 93 uint32_t reserved_21a : 32; 94 uint32_t reserved_22a : 32; 95 uint32_t reserved_23a : 32; 96 uint32_t reserved_24a : 32; 97 uint32_t looping_count : 4, 98 reserved_25a : 28; 99 #endif 100 }; 101 102 #define REO_FLUSH_CACHE_STATUS_TLV32_RING_PADDING_OFFSET 0x00000000 103 #define REO_FLUSH_CACHE_STATUS_TLV32_RING_PADDING_LSB 0 104 #define REO_FLUSH_CACHE_STATUS_TLV32_RING_PADDING_MSB 31 105 #define REO_FLUSH_CACHE_STATUS_TLV32_RING_PADDING_MASK 0xffffffff 106 107 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000004 108 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 109 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 110 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff 111 112 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000004 113 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 114 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 115 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 116 117 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004 118 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 119 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 120 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 121 122 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000004 123 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 124 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 125 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 126 127 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000008 128 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 0 129 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 31 130 #define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff 131 132 #define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000c 133 #define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_LSB 0 134 #define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MSB 0 135 #define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MASK 0x00000001 136 137 #define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_OFFSET 0x0000000c 138 #define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_LSB 1 139 #define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MSB 2 140 #define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MASK 0x00000006 141 142 #define REO_FLUSH_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000c 143 #define REO_FLUSH_CACHE_STATUS_RESERVED_2A_LSB 3 144 #define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MSB 7 145 #define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MASK 0x000000f8 146 147 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET 0x0000000c 148 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB 8 149 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MSB 8 150 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK 0x00000100 151 152 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET 0x0000000c 153 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB 9 154 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MSB 11 155 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK 0x00000e00 156 157 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET 0x0000000c 158 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB 12 159 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MSB 15 160 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK 0x0000f000 161 162 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET 0x0000000c 163 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB 16 164 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MSB 17 165 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK 0x00030000 166 167 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET 0x0000000c 168 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_LSB 18 169 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MSB 25 170 #define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MASK 0x03fc0000 171 172 #define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000c 173 #define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_LSB 26 174 #define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MSB 26 175 #define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MASK 0x04000000 176 177 #define REO_FLUSH_CACHE_STATUS_RESERVED_2B_OFFSET 0x0000000c 178 #define REO_FLUSH_CACHE_STATUS_RESERVED_2B_LSB 27 179 #define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MSB 31 180 #define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MASK 0xf8000000 181 182 #define REO_FLUSH_CACHE_STATUS_RESERVED_3A_OFFSET 0x00000010 183 #define REO_FLUSH_CACHE_STATUS_RESERVED_3A_LSB 0 184 #define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MSB 31 185 #define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff 186 187 #define REO_FLUSH_CACHE_STATUS_RESERVED_4A_OFFSET 0x00000014 188 #define REO_FLUSH_CACHE_STATUS_RESERVED_4A_LSB 0 189 #define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MSB 31 190 #define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MASK 0xffffffff 191 192 #define REO_FLUSH_CACHE_STATUS_RESERVED_5A_OFFSET 0x00000018 193 #define REO_FLUSH_CACHE_STATUS_RESERVED_5A_LSB 0 194 #define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MSB 31 195 #define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff 196 197 #define REO_FLUSH_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000001c 198 #define REO_FLUSH_CACHE_STATUS_RESERVED_6A_LSB 0 199 #define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MSB 31 200 #define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MASK 0xffffffff 201 202 #define REO_FLUSH_CACHE_STATUS_RESERVED_7A_OFFSET 0x00000020 203 #define REO_FLUSH_CACHE_STATUS_RESERVED_7A_LSB 0 204 #define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MSB 31 205 #define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff 206 207 #define REO_FLUSH_CACHE_STATUS_RESERVED_8A_OFFSET 0x00000024 208 #define REO_FLUSH_CACHE_STATUS_RESERVED_8A_LSB 0 209 #define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MSB 31 210 #define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MASK 0xffffffff 211 212 #define REO_FLUSH_CACHE_STATUS_RESERVED_9A_OFFSET 0x00000028 213 #define REO_FLUSH_CACHE_STATUS_RESERVED_9A_LSB 0 214 #define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MSB 31 215 #define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff 216 217 #define REO_FLUSH_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000002c 218 #define REO_FLUSH_CACHE_STATUS_RESERVED_10A_LSB 0 219 #define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MSB 31 220 #define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MASK 0xffffffff 221 222 #define REO_FLUSH_CACHE_STATUS_RESERVED_11A_OFFSET 0x00000030 223 #define REO_FLUSH_CACHE_STATUS_RESERVED_11A_LSB 0 224 #define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MSB 31 225 #define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff 226 227 #define REO_FLUSH_CACHE_STATUS_RESERVED_12A_OFFSET 0x00000034 228 #define REO_FLUSH_CACHE_STATUS_RESERVED_12A_LSB 0 229 #define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MSB 31 230 #define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MASK 0xffffffff 231 232 #define REO_FLUSH_CACHE_STATUS_RESERVED_13A_OFFSET 0x00000038 233 #define REO_FLUSH_CACHE_STATUS_RESERVED_13A_LSB 0 234 #define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MSB 31 235 #define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff 236 237 #define REO_FLUSH_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000003c 238 #define REO_FLUSH_CACHE_STATUS_RESERVED_14A_LSB 0 239 #define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MSB 31 240 #define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MASK 0xffffffff 241 242 #define REO_FLUSH_CACHE_STATUS_RESERVED_15A_OFFSET 0x00000040 243 #define REO_FLUSH_CACHE_STATUS_RESERVED_15A_LSB 0 244 #define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MSB 31 245 #define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff 246 247 #define REO_FLUSH_CACHE_STATUS_RESERVED_16A_OFFSET 0x00000044 248 #define REO_FLUSH_CACHE_STATUS_RESERVED_16A_LSB 0 249 #define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MSB 31 250 #define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MASK 0xffffffff 251 252 #define REO_FLUSH_CACHE_STATUS_RESERVED_17A_OFFSET 0x00000048 253 #define REO_FLUSH_CACHE_STATUS_RESERVED_17A_LSB 0 254 #define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MSB 31 255 #define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff 256 257 #define REO_FLUSH_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000004c 258 #define REO_FLUSH_CACHE_STATUS_RESERVED_18A_LSB 0 259 #define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MSB 31 260 #define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MASK 0xffffffff 261 262 #define REO_FLUSH_CACHE_STATUS_RESERVED_19A_OFFSET 0x00000050 263 #define REO_FLUSH_CACHE_STATUS_RESERVED_19A_LSB 0 264 #define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MSB 31 265 #define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff 266 267 #define REO_FLUSH_CACHE_STATUS_RESERVED_20A_OFFSET 0x00000054 268 #define REO_FLUSH_CACHE_STATUS_RESERVED_20A_LSB 0 269 #define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MSB 31 270 #define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MASK 0xffffffff 271 272 #define REO_FLUSH_CACHE_STATUS_RESERVED_21A_OFFSET 0x00000058 273 #define REO_FLUSH_CACHE_STATUS_RESERVED_21A_LSB 0 274 #define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MSB 31 275 #define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff 276 277 #define REO_FLUSH_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000005c 278 #define REO_FLUSH_CACHE_STATUS_RESERVED_22A_LSB 0 279 #define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MSB 31 280 #define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MASK 0xffffffff 281 282 #define REO_FLUSH_CACHE_STATUS_RESERVED_23A_OFFSET 0x00000060 283 #define REO_FLUSH_CACHE_STATUS_RESERVED_23A_LSB 0 284 #define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MSB 31 285 #define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff 286 287 #define REO_FLUSH_CACHE_STATUS_RESERVED_24A_OFFSET 0x00000064 288 #define REO_FLUSH_CACHE_STATUS_RESERVED_24A_LSB 0 289 #define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MSB 31 290 #define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MASK 0xffffffff 291 292 #define REO_FLUSH_CACHE_STATUS_RESERVED_25A_OFFSET 0x00000068 293 #define REO_FLUSH_CACHE_STATUS_RESERVED_25A_LSB 0 294 #define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MSB 27 295 #define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff 296 297 #define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x00000068 298 #define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_LSB 28 299 #define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MSB 31 300 #define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MASK 0xf0000000 301 302 #endif 303