1 /* 2 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _RX_PPDU_END_USER_STATS_H_ 19 #define _RX_PPDU_END_USER_STATS_H_ 20 21 #include "rx_rxpcu_classification_overview.h" 22 #define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 30 23 24 struct rx_ppdu_end_user_stats { 25 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 26 struct rx_rxpcu_classification_overview rxpcu_classification_details; 27 uint32_t sta_full_aid : 13, 28 mcs : 4, 29 nss : 3, 30 expected_response_ack_or_ba : 1, 31 reserved_1a : 11; 32 uint32_t sw_peer_id : 16, 33 mpdu_cnt_fcs_err : 11, 34 sw2rxdma0_buf_source_used : 1, 35 fw2rxdma_pmac0_buf_source_used : 1, 36 sw2rxdma1_buf_source_used : 1, 37 sw2rxdma_exception_buf_source_used : 1, 38 fw2rxdma_pmac1_buf_source_used : 1; 39 uint32_t mpdu_cnt_fcs_ok : 11, 40 frame_control_info_valid : 1, 41 qos_control_info_valid : 1, 42 ht_control_info_valid : 1, 43 data_sequence_control_info_valid : 1, 44 ht_control_info_null_valid : 1, 45 rxdma2fw_pmac1_ring_used : 1, 46 rxdma2reo_ring_used : 1, 47 rxdma2fw_pmac0_ring_used : 1, 48 rxdma2sw_ring_used : 1, 49 rxdma_release_ring_used : 1, 50 ht_control_field_pkt_type : 4, 51 rxdma2reo_remote0_ring_used : 1, 52 rxdma2reo_remote1_ring_used : 1, 53 reserved_3b : 5; 54 uint32_t ast_index : 16, 55 frame_control_field : 16; 56 uint32_t first_data_seq_ctrl : 16, 57 qos_control_field : 16; 58 uint32_t ht_control_field : 32; 59 uint32_t fcs_ok_bitmap_31_0 : 32; 60 uint32_t fcs_ok_bitmap_63_32 : 32; 61 uint32_t udp_msdu_count : 16, 62 tcp_msdu_count : 16; 63 uint32_t other_msdu_count : 16, 64 tcp_ack_msdu_count : 16; 65 uint32_t sw_response_reference_ptr : 32; 66 uint32_t received_qos_data_tid_bitmap : 16, 67 received_qos_data_tid_eosp_bitmap : 16; 68 uint32_t qosctrl_15_8_tid0 : 8, 69 qosctrl_15_8_tid1 : 8, 70 qosctrl_15_8_tid2 : 8, 71 qosctrl_15_8_tid3 : 8; 72 uint32_t qosctrl_15_8_tid4 : 8, 73 qosctrl_15_8_tid5 : 8, 74 qosctrl_15_8_tid6 : 8, 75 qosctrl_15_8_tid7 : 8; 76 uint32_t qosctrl_15_8_tid8 : 8, 77 qosctrl_15_8_tid9 : 8, 78 qosctrl_15_8_tid10 : 8, 79 qosctrl_15_8_tid11 : 8; 80 uint32_t qosctrl_15_8_tid12 : 8, 81 qosctrl_15_8_tid13 : 8, 82 qosctrl_15_8_tid14 : 8, 83 qosctrl_15_8_tid15 : 8; 84 uint32_t mpdu_ok_byte_count : 25, 85 ampdu_delim_ok_count_6_0 : 7; 86 uint32_t ampdu_delim_err_count : 25, 87 ampdu_delim_ok_count_13_7 : 7; 88 uint32_t mpdu_err_byte_count : 25, 89 ampdu_delim_ok_count_20_14 : 7; 90 uint32_t non_consecutive_delimiter_err : 16, 91 retried_msdu_count : 16; 92 uint32_t ht_control_null_field : 32; 93 uint32_t sw_response_reference_ptr_ext : 32; 94 uint32_t corrupted_due_to_fifo_delay : 1, 95 frame_control_info_null_valid : 1, 96 frame_control_field_null : 16, 97 retried_mpdu_count : 11, 98 reserved_23a : 3; 99 uint32_t rxpcu_mpdu_filter_in_category : 2, 100 sw_frame_group_id : 7, 101 reserved_24a : 4, 102 frame_control_info_mgmt_ctrl_valid : 1, 103 mac_addr_ad2_valid : 1, 104 mcast_bcast : 1, 105 frame_control_field_mgmt_ctrl : 16; 106 uint32_t user_ppdu_len : 24, 107 reserved_25a : 8; 108 uint32_t mac_addr_ad2_31_0 : 32; 109 uint32_t mac_addr_ad2_47_32 : 16, 110 amsdu_msdu_count : 16; 111 uint32_t non_amsdu_msdu_count : 16, 112 ucast_msdu_count : 16; 113 uint32_t bcast_msdu_count : 16, 114 mcast_bcast_msdu_count : 16; 115 #else 116 struct rx_rxpcu_classification_overview rxpcu_classification_details; 117 uint32_t reserved_1a : 11, 118 expected_response_ack_or_ba : 1, 119 nss : 3, 120 mcs : 4, 121 sta_full_aid : 13; 122 uint32_t fw2rxdma_pmac1_buf_source_used : 1, 123 sw2rxdma_exception_buf_source_used : 1, 124 sw2rxdma1_buf_source_used : 1, 125 fw2rxdma_pmac0_buf_source_used : 1, 126 sw2rxdma0_buf_source_used : 1, 127 mpdu_cnt_fcs_err : 11, 128 sw_peer_id : 16; 129 uint32_t reserved_3b : 5, 130 rxdma2reo_remote1_ring_used : 1, 131 rxdma2reo_remote0_ring_used : 1, 132 ht_control_field_pkt_type : 4, 133 rxdma_release_ring_used : 1, 134 rxdma2sw_ring_used : 1, 135 rxdma2fw_pmac0_ring_used : 1, 136 rxdma2reo_ring_used : 1, 137 rxdma2fw_pmac1_ring_used : 1, 138 ht_control_info_null_valid : 1, 139 data_sequence_control_info_valid : 1, 140 ht_control_info_valid : 1, 141 qos_control_info_valid : 1, 142 frame_control_info_valid : 1, 143 mpdu_cnt_fcs_ok : 11; 144 uint32_t frame_control_field : 16, 145 ast_index : 16; 146 uint32_t qos_control_field : 16, 147 first_data_seq_ctrl : 16; 148 uint32_t ht_control_field : 32; 149 uint32_t fcs_ok_bitmap_31_0 : 32; 150 uint32_t fcs_ok_bitmap_63_32 : 32; 151 uint32_t tcp_msdu_count : 16, 152 udp_msdu_count : 16; 153 uint32_t tcp_ack_msdu_count : 16, 154 other_msdu_count : 16; 155 uint32_t sw_response_reference_ptr : 32; 156 uint32_t received_qos_data_tid_eosp_bitmap : 16, 157 received_qos_data_tid_bitmap : 16; 158 uint32_t qosctrl_15_8_tid3 : 8, 159 qosctrl_15_8_tid2 : 8, 160 qosctrl_15_8_tid1 : 8, 161 qosctrl_15_8_tid0 : 8; 162 uint32_t qosctrl_15_8_tid7 : 8, 163 qosctrl_15_8_tid6 : 8, 164 qosctrl_15_8_tid5 : 8, 165 qosctrl_15_8_tid4 : 8; 166 uint32_t qosctrl_15_8_tid11 : 8, 167 qosctrl_15_8_tid10 : 8, 168 qosctrl_15_8_tid9 : 8, 169 qosctrl_15_8_tid8 : 8; 170 uint32_t qosctrl_15_8_tid15 : 8, 171 qosctrl_15_8_tid14 : 8, 172 qosctrl_15_8_tid13 : 8, 173 qosctrl_15_8_tid12 : 8; 174 uint32_t ampdu_delim_ok_count_6_0 : 7, 175 mpdu_ok_byte_count : 25; 176 uint32_t ampdu_delim_ok_count_13_7 : 7, 177 ampdu_delim_err_count : 25; 178 uint32_t ampdu_delim_ok_count_20_14 : 7, 179 mpdu_err_byte_count : 25; 180 uint32_t retried_msdu_count : 16, 181 non_consecutive_delimiter_err : 16; 182 uint32_t ht_control_null_field : 32; 183 uint32_t sw_response_reference_ptr_ext : 32; 184 uint32_t reserved_23a : 3, 185 retried_mpdu_count : 11, 186 frame_control_field_null : 16, 187 frame_control_info_null_valid : 1, 188 corrupted_due_to_fifo_delay : 1; 189 uint32_t frame_control_field_mgmt_ctrl : 16, 190 mcast_bcast : 1, 191 mac_addr_ad2_valid : 1, 192 frame_control_info_mgmt_ctrl_valid : 1, 193 reserved_24a : 4, 194 sw_frame_group_id : 7, 195 rxpcu_mpdu_filter_in_category : 2; 196 uint32_t reserved_25a : 8, 197 user_ppdu_len : 24; 198 uint32_t mac_addr_ad2_31_0 : 32; 199 uint32_t amsdu_msdu_count : 16, 200 mac_addr_ad2_47_32 : 16; 201 uint32_t ucast_msdu_count : 16, 202 non_amsdu_msdu_count : 16; 203 uint32_t mcast_bcast_msdu_count : 16, 204 bcast_msdu_count : 16; 205 #endif 206 }; 207 208 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x00000000 209 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 210 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 211 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x00000001 212 213 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 214 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 215 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 216 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 217 218 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 219 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 220 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 221 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x00000004 222 223 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 224 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 225 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 226 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 227 228 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 229 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 230 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 231 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x00000010 232 233 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 234 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 235 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 236 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 237 238 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 239 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 240 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 241 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x00000040 242 243 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x00000000 244 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 245 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 246 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x00000080 247 248 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x00000000 249 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 250 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 251 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x00000100 252 253 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x00000000 254 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 255 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 256 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x0000fe00 257 258 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 259 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 260 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 261 #define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0xffff0000 262 263 #define RX_PPDU_END_USER_STATS_STA_FULL_AID_OFFSET 0x00000004 264 #define RX_PPDU_END_USER_STATS_STA_FULL_AID_LSB 0 265 #define RX_PPDU_END_USER_STATS_STA_FULL_AID_MSB 12 266 #define RX_PPDU_END_USER_STATS_STA_FULL_AID_MASK 0x00001fff 267 268 #define RX_PPDU_END_USER_STATS_MCS_OFFSET 0x00000004 269 #define RX_PPDU_END_USER_STATS_MCS_LSB 13 270 #define RX_PPDU_END_USER_STATS_MCS_MSB 16 271 #define RX_PPDU_END_USER_STATS_MCS_MASK 0x0001e000 272 273 #define RX_PPDU_END_USER_STATS_NSS_OFFSET 0x00000004 274 #define RX_PPDU_END_USER_STATS_NSS_LSB 17 275 #define RX_PPDU_END_USER_STATS_NSS_MSB 19 276 #define RX_PPDU_END_USER_STATS_NSS_MASK 0x000e0000 277 278 #define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_OFFSET 0x00000004 279 #define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_LSB 20 280 #define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MSB 20 281 #define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MASK 0x00100000 282 283 #define RX_PPDU_END_USER_STATS_RESERVED_1A_OFFSET 0x00000004 284 #define RX_PPDU_END_USER_STATS_RESERVED_1A_LSB 21 285 #define RX_PPDU_END_USER_STATS_RESERVED_1A_MSB 31 286 #define RX_PPDU_END_USER_STATS_RESERVED_1A_MASK 0xffe00000 287 288 #define RX_PPDU_END_USER_STATS_SW_PEER_ID_OFFSET 0x00000008 289 #define RX_PPDU_END_USER_STATS_SW_PEER_ID_LSB 0 290 #define RX_PPDU_END_USER_STATS_SW_PEER_ID_MSB 15 291 #define RX_PPDU_END_USER_STATS_SW_PEER_ID_MASK 0x0000ffff 292 293 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_OFFSET 0x00000008 294 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_LSB 16 295 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MSB 26 296 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MASK 0x07ff0000 297 298 #define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_OFFSET 0x00000008 299 #define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_LSB 27 300 #define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MSB 27 301 #define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MASK 0x08000000 302 303 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_OFFSET 0x00000008 304 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_LSB 28 305 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MSB 28 306 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MASK 0x10000000 307 308 #define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_OFFSET 0x00000008 309 #define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_LSB 29 310 #define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MSB 29 311 #define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MASK 0x20000000 312 313 #define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_OFFSET 0x00000008 314 #define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_LSB 30 315 #define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MSB 30 316 #define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MASK 0x40000000 317 318 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_OFFSET 0x00000008 319 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_LSB 31 320 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MSB 31 321 #define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MASK 0x80000000 322 323 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_OFFSET 0x0000000c 324 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_LSB 0 325 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MSB 10 326 #define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MASK 0x000007ff 327 328 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_OFFSET 0x0000000c 329 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_LSB 11 330 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MSB 11 331 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MASK 0x00000800 332 333 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_OFFSET 0x0000000c 334 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_LSB 12 335 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MSB 12 336 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MASK 0x00001000 337 338 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_OFFSET 0x0000000c 339 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_LSB 13 340 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MSB 13 341 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MASK 0x00002000 342 343 #define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET 0x0000000c 344 #define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB 14 345 #define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MSB 14 346 #define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK 0x00004000 347 348 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000c 349 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_LSB 15 350 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MSB 15 351 #define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MASK 0x00008000 352 353 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_OFFSET 0x0000000c 354 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_LSB 16 355 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MSB 16 356 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MASK 0x00010000 357 358 #define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_OFFSET 0x0000000c 359 #define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_LSB 17 360 #define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MSB 17 361 #define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MASK 0x00020000 362 363 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_OFFSET 0x0000000c 364 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_LSB 18 365 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MSB 18 366 #define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MASK 0x00040000 367 368 #define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_OFFSET 0x0000000c 369 #define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_LSB 19 370 #define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MSB 19 371 #define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MASK 0x00080000 372 373 #define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_OFFSET 0x0000000c 374 #define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_LSB 20 375 #define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MSB 20 376 #define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MASK 0x00100000 377 378 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_OFFSET 0x0000000c 379 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_LSB 21 380 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MSB 24 381 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MASK 0x01e00000 382 383 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_OFFSET 0x0000000c 384 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_LSB 25 385 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_MSB 25 386 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_MASK 0x02000000 387 388 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_OFFSET 0x0000000c 389 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_LSB 26 390 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_MSB 26 391 #define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_MASK 0x04000000 392 393 #define RX_PPDU_END_USER_STATS_RESERVED_3B_OFFSET 0x0000000c 394 #define RX_PPDU_END_USER_STATS_RESERVED_3B_LSB 27 395 #define RX_PPDU_END_USER_STATS_RESERVED_3B_MSB 31 396 #define RX_PPDU_END_USER_STATS_RESERVED_3B_MASK 0xf8000000 397 398 #define RX_PPDU_END_USER_STATS_AST_INDEX_OFFSET 0x00000010 399 #define RX_PPDU_END_USER_STATS_AST_INDEX_LSB 0 400 #define RX_PPDU_END_USER_STATS_AST_INDEX_MSB 15 401 #define RX_PPDU_END_USER_STATS_AST_INDEX_MASK 0x0000ffff 402 403 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_OFFSET 0x00000010 404 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_LSB 16 405 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MSB 31 406 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MASK 0xffff0000 407 408 #define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_OFFSET 0x00000014 409 #define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_LSB 0 410 #define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MSB 15 411 #define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MASK 0x0000ffff 412 413 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_OFFSET 0x00000014 414 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_LSB 16 415 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MSB 31 416 #define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MASK 0xffff0000 417 418 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_OFFSET 0x00000018 419 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_LSB 0 420 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MSB 31 421 #define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MASK 0xffffffff 422 423 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_OFFSET 0x0000001c 424 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_LSB 0 425 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MSB 31 426 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MASK 0xffffffff 427 428 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_OFFSET 0x00000020 429 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_LSB 0 430 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MSB 31 431 #define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MASK 0xffffffff 432 433 #define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_OFFSET 0x00000024 434 #define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_LSB 0 435 #define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MSB 15 436 #define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MASK 0x0000ffff 437 438 #define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_OFFSET 0x00000024 439 #define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_LSB 16 440 #define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MSB 31 441 #define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MASK 0xffff0000 442 443 #define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_OFFSET 0x00000028 444 #define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_LSB 0 445 #define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MSB 15 446 #define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MASK 0x0000ffff 447 448 #define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_OFFSET 0x00000028 449 #define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_LSB 16 450 #define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MSB 31 451 #define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MASK 0xffff0000 452 453 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_OFFSET 0x0000002c 454 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_LSB 0 455 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MSB 31 456 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MASK 0xffffffff 457 458 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET 0x00000030 459 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_LSB 0 460 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MSB 15 461 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MASK 0x0000ffff 462 463 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET 0x00000030 464 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB 16 465 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MSB 31 466 #define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK 0xffff0000 467 468 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_OFFSET 0x00000034 469 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_LSB 0 470 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MSB 7 471 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MASK 0x000000ff 472 473 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_OFFSET 0x00000034 474 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_LSB 8 475 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MSB 15 476 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MASK 0x0000ff00 477 478 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_OFFSET 0x00000034 479 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_LSB 16 480 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MSB 23 481 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MASK 0x00ff0000 482 483 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_OFFSET 0x00000034 484 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_LSB 24 485 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MSB 31 486 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MASK 0xff000000 487 488 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_OFFSET 0x00000038 489 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_LSB 0 490 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MSB 7 491 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MASK 0x000000ff 492 493 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_OFFSET 0x00000038 494 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_LSB 8 495 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MSB 15 496 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MASK 0x0000ff00 497 498 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_OFFSET 0x00000038 499 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_LSB 16 500 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MSB 23 501 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MASK 0x00ff0000 502 503 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_OFFSET 0x00000038 504 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_LSB 24 505 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MSB 31 506 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MASK 0xff000000 507 508 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_OFFSET 0x0000003c 509 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_LSB 0 510 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MSB 7 511 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MASK 0x000000ff 512 513 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_OFFSET 0x0000003c 514 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_LSB 8 515 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MSB 15 516 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MASK 0x0000ff00 517 518 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_OFFSET 0x0000003c 519 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_LSB 16 520 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MSB 23 521 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MASK 0x00ff0000 522 523 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_OFFSET 0x0000003c 524 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_LSB 24 525 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MSB 31 526 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MASK 0xff000000 527 528 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_OFFSET 0x00000040 529 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_LSB 0 530 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MSB 7 531 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MASK 0x000000ff 532 533 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_OFFSET 0x00000040 534 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_LSB 8 535 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MSB 15 536 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MASK 0x0000ff00 537 538 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_OFFSET 0x00000040 539 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_LSB 16 540 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MSB 23 541 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MASK 0x00ff0000 542 543 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_OFFSET 0x00000040 544 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_LSB 24 545 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MSB 31 546 #define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MASK 0xff000000 547 548 #define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_OFFSET 0x00000044 549 #define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_LSB 0 550 #define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MSB 24 551 #define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MASK 0x01ffffff 552 553 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_OFFSET 0x00000044 554 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_LSB 25 555 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MSB 31 556 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MASK 0xfe000000 557 558 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_OFFSET 0x00000048 559 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_LSB 0 560 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MSB 24 561 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MASK 0x01ffffff 562 563 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_OFFSET 0x00000048 564 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_LSB 25 565 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MSB 31 566 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MASK 0xfe000000 567 568 #define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_OFFSET 0x0000004c 569 #define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_LSB 0 570 #define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MSB 24 571 #define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MASK 0x01ffffff 572 573 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_OFFSET 0x0000004c 574 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_LSB 25 575 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MSB 31 576 #define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MASK 0xfe000000 577 578 #define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET 0x00000050 579 #define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_LSB 0 580 #define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MSB 15 581 #define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MASK 0x0000ffff 582 583 #define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_OFFSET 0x00000050 584 #define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_LSB 16 585 #define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MSB 31 586 #define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MASK 0xffff0000 587 588 #define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_OFFSET 0x00000054 589 #define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_LSB 0 590 #define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MSB 31 591 #define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MASK 0xffffffff 592 593 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET 0x00000058 594 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_LSB 0 595 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MSB 31 596 #define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MASK 0xffffffff 597 598 #define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000005c 599 #define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 0 600 #define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 0 601 #define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x00000001 602 603 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_OFFSET 0x0000005c 604 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_LSB 1 605 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MSB 1 606 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MASK 0x00000002 607 608 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_OFFSET 0x0000005c 609 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_LSB 2 610 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MSB 17 611 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MASK 0x0003fffc 612 613 #define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_OFFSET 0x0000005c 614 #define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_LSB 18 615 #define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MSB 28 616 #define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MASK 0x1ffc0000 617 618 #define RX_PPDU_END_USER_STATS_RESERVED_23A_OFFSET 0x0000005c 619 #define RX_PPDU_END_USER_STATS_RESERVED_23A_LSB 29 620 #define RX_PPDU_END_USER_STATS_RESERVED_23A_MSB 31 621 #define RX_PPDU_END_USER_STATS_RESERVED_23A_MASK 0xe0000000 622 623 #define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000060 624 #define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 625 #define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 626 #define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 627 628 #define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_OFFSET 0x00000060 629 #define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_LSB 2 630 #define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MSB 8 631 #define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MASK 0x000001fc 632 633 #define RX_PPDU_END_USER_STATS_RESERVED_24A_OFFSET 0x00000060 634 #define RX_PPDU_END_USER_STATS_RESERVED_24A_LSB 9 635 #define RX_PPDU_END_USER_STATS_RESERVED_24A_MSB 12 636 #define RX_PPDU_END_USER_STATS_RESERVED_24A_MASK 0x00001e00 637 638 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_OFFSET 0x00000060 639 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_LSB 13 640 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MSB 13 641 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MASK 0x00002000 642 643 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_OFFSET 0x00000060 644 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_LSB 14 645 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MSB 14 646 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MASK 0x00004000 647 648 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_OFFSET 0x00000060 649 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_LSB 15 650 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSB 15 651 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_MASK 0x00008000 652 653 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_OFFSET 0x00000060 654 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_LSB 16 655 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MSB 31 656 #define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MASK 0xffff0000 657 658 #define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_OFFSET 0x00000064 659 #define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_LSB 0 660 #define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MSB 23 661 #define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MASK 0x00ffffff 662 663 #define RX_PPDU_END_USER_STATS_RESERVED_25A_OFFSET 0x00000064 664 #define RX_PPDU_END_USER_STATS_RESERVED_25A_LSB 24 665 #define RX_PPDU_END_USER_STATS_RESERVED_25A_MSB 31 666 #define RX_PPDU_END_USER_STATS_RESERVED_25A_MASK 0xff000000 667 668 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_OFFSET 0x00000068 669 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_LSB 0 670 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MSB 31 671 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MASK 0xffffffff 672 673 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_OFFSET 0x0000006c 674 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_LSB 0 675 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MSB 15 676 #define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MASK 0x0000ffff 677 678 #define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_OFFSET 0x0000006c 679 #define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_LSB 16 680 #define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MSB 31 681 #define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MASK 0xffff0000 682 683 #define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_OFFSET 0x00000070 684 #define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_LSB 0 685 #define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MSB 15 686 #define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MASK 0x0000ffff 687 688 #define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_OFFSET 0x00000070 689 #define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_LSB 16 690 #define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MSB 31 691 #define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MASK 0xffff0000 692 693 #define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_OFFSET 0x00000074 694 #define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_LSB 0 695 #define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MSB 15 696 #define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MASK 0x0000ffff 697 698 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_OFFSET 0x00000074 699 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_LSB 16 700 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MSB 31 701 #define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MASK 0xffff0000 702 703 #endif 704