1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any 5*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above 6*5113495bSYour Name * copyright notice and this permission notice appear in all copies. 7*5113495bSYour Name * 8*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*5113495bSYour Name */ 16*5113495bSYour Name 17*5113495bSYour Name 18*5113495bSYour Name #ifndef _RX_PPDU_START_H_ 19*5113495bSYour Name #define _RX_PPDU_START_H_ 20*5113495bSYour Name 21*5113495bSYour Name #define NUM_OF_DWORDS_RX_PPDU_START 5 22*5113495bSYour Name 23*5113495bSYour Name struct rx_ppdu_start { 24*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 25*5113495bSYour Name uint32_t phy_ppdu_id : 16, 26*5113495bSYour Name preamble_time_to_rxframe : 8, 27*5113495bSYour Name reserved_0a : 8; 28*5113495bSYour Name uint32_t sw_phy_meta_data : 32; 29*5113495bSYour Name uint32_t ppdu_start_timestamp_31_0 : 32; 30*5113495bSYour Name uint32_t ppdu_start_timestamp_63_32 : 32; 31*5113495bSYour Name uint32_t rxframe_assert_timestamp : 32; 32*5113495bSYour Name #else 33*5113495bSYour Name uint32_t reserved_0a : 8, 34*5113495bSYour Name preamble_time_to_rxframe : 8, 35*5113495bSYour Name phy_ppdu_id : 16; 36*5113495bSYour Name uint32_t sw_phy_meta_data : 32; 37*5113495bSYour Name uint32_t ppdu_start_timestamp_31_0 : 32; 38*5113495bSYour Name uint32_t ppdu_start_timestamp_63_32 : 32; 39*5113495bSYour Name uint32_t rxframe_assert_timestamp : 32; 40*5113495bSYour Name #endif 41*5113495bSYour Name }; 42*5113495bSYour Name 43*5113495bSYour Name #define RX_PPDU_START_PHY_PPDU_ID_OFFSET 0x00000000 44*5113495bSYour Name #define RX_PPDU_START_PHY_PPDU_ID_LSB 0 45*5113495bSYour Name #define RX_PPDU_START_PHY_PPDU_ID_MSB 15 46*5113495bSYour Name #define RX_PPDU_START_PHY_PPDU_ID_MASK 0x0000ffff 47*5113495bSYour Name 48*5113495bSYour Name #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x00000000 49*5113495bSYour Name #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_LSB 16 50*5113495bSYour Name #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MSB 23 51*5113495bSYour Name #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MASK 0x00ff0000 52*5113495bSYour Name 53*5113495bSYour Name #define RX_PPDU_START_RESERVED_0A_OFFSET 0x00000000 54*5113495bSYour Name #define RX_PPDU_START_RESERVED_0A_LSB 24 55*5113495bSYour Name #define RX_PPDU_START_RESERVED_0A_MSB 31 56*5113495bSYour Name #define RX_PPDU_START_RESERVED_0A_MASK 0xff000000 57*5113495bSYour Name 58*5113495bSYour Name #define RX_PPDU_START_SW_PHY_META_DATA_OFFSET 0x00000004 59*5113495bSYour Name #define RX_PPDU_START_SW_PHY_META_DATA_LSB 0 60*5113495bSYour Name #define RX_PPDU_START_SW_PHY_META_DATA_MSB 31 61*5113495bSYour Name #define RX_PPDU_START_SW_PHY_META_DATA_MASK 0xffffffff 62*5113495bSYour Name 63*5113495bSYour Name #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000008 64*5113495bSYour Name #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 65*5113495bSYour Name #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 66*5113495bSYour Name #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff 67*5113495bSYour Name 68*5113495bSYour Name #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000c 69*5113495bSYour Name #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_LSB 0 70*5113495bSYour Name #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MSB 31 71*5113495bSYour Name #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff 72*5113495bSYour Name 73*5113495bSYour Name #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_OFFSET 0x00000010 74*5113495bSYour Name #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_LSB 0 75*5113495bSYour Name #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MSB 31 76*5113495bSYour Name #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MASK 0xffffffff 77*5113495bSYour Name 78*5113495bSYour Name #endif 79