1 /* 2 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _RX_PPDU_START_H_ 19 #define _RX_PPDU_START_H_ 20 21 #define NUM_OF_DWORDS_RX_PPDU_START 5 22 23 struct rx_ppdu_start { 24 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 25 uint32_t phy_ppdu_id : 16, 26 preamble_time_to_rxframe : 8, 27 reserved_0a : 8; 28 uint32_t sw_phy_meta_data : 32; 29 uint32_t ppdu_start_timestamp_31_0 : 32; 30 uint32_t ppdu_start_timestamp_63_32 : 32; 31 uint32_t rxframe_assert_timestamp : 32; 32 #else 33 uint32_t reserved_0a : 8, 34 preamble_time_to_rxframe : 8, 35 phy_ppdu_id : 16; 36 uint32_t sw_phy_meta_data : 32; 37 uint32_t ppdu_start_timestamp_31_0 : 32; 38 uint32_t ppdu_start_timestamp_63_32 : 32; 39 uint32_t rxframe_assert_timestamp : 32; 40 #endif 41 }; 42 43 #define RX_PPDU_START_PHY_PPDU_ID_OFFSET 0x00000000 44 #define RX_PPDU_START_PHY_PPDU_ID_LSB 0 45 #define RX_PPDU_START_PHY_PPDU_ID_MSB 15 46 #define RX_PPDU_START_PHY_PPDU_ID_MASK 0x0000ffff 47 48 #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x00000000 49 #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_LSB 16 50 #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MSB 23 51 #define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MASK 0x00ff0000 52 53 #define RX_PPDU_START_RESERVED_0A_OFFSET 0x00000000 54 #define RX_PPDU_START_RESERVED_0A_LSB 24 55 #define RX_PPDU_START_RESERVED_0A_MSB 31 56 #define RX_PPDU_START_RESERVED_0A_MASK 0xff000000 57 58 #define RX_PPDU_START_SW_PHY_META_DATA_OFFSET 0x00000004 59 #define RX_PPDU_START_SW_PHY_META_DATA_LSB 0 60 #define RX_PPDU_START_SW_PHY_META_DATA_MSB 31 61 #define RX_PPDU_START_SW_PHY_META_DATA_MASK 0xffffffff 62 63 #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000008 64 #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 65 #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 66 #define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff 67 68 #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000c 69 #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_LSB 0 70 #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MSB 31 71 #define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff 72 73 #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_OFFSET 0x00000010 74 #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_LSB 0 75 #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MSB 31 76 #define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MASK 0xffffffff 77 78 #endif 79