1 /* 2 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _RX_REO_QUEUE_1K_H_ 19 #define _RX_REO_QUEUE_1K_H_ 20 21 #include "uniform_descriptor_header.h" 22 #define NUM_OF_DWORDS_RX_REO_QUEUE_1K 32 23 24 struct rx_reo_queue_1k { 25 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 26 struct uniform_descriptor_header descriptor_header; 27 uint32_t rx_bitmap_319_288 : 32; 28 uint32_t rx_bitmap_351_320 : 32; 29 uint32_t rx_bitmap_383_352 : 32; 30 uint32_t rx_bitmap_415_384 : 32; 31 uint32_t rx_bitmap_447_416 : 32; 32 uint32_t rx_bitmap_479_448 : 32; 33 uint32_t rx_bitmap_511_480 : 32; 34 uint32_t rx_bitmap_543_512 : 32; 35 uint32_t rx_bitmap_575_544 : 32; 36 uint32_t rx_bitmap_607_576 : 32; 37 uint32_t rx_bitmap_639_608 : 32; 38 uint32_t rx_bitmap_671_640 : 32; 39 uint32_t rx_bitmap_703_672 : 32; 40 uint32_t rx_bitmap_735_704 : 32; 41 uint32_t rx_bitmap_767_736 : 32; 42 uint32_t rx_bitmap_799_768 : 32; 43 uint32_t rx_bitmap_831_800 : 32; 44 uint32_t rx_bitmap_863_832 : 32; 45 uint32_t rx_bitmap_895_864 : 32; 46 uint32_t rx_bitmap_927_896 : 32; 47 uint32_t rx_bitmap_959_928 : 32; 48 uint32_t rx_bitmap_991_960 : 32; 49 uint32_t rx_bitmap_1023_992 : 32; 50 uint32_t reserved_24 : 32; 51 uint32_t reserved_25 : 32; 52 uint32_t reserved_26 : 32; 53 uint32_t reserved_27 : 32; 54 uint32_t reserved_28 : 32; 55 uint32_t reserved_29 : 32; 56 uint32_t reserved_30 : 32; 57 uint32_t reserved_31 : 32; 58 #else 59 struct uniform_descriptor_header descriptor_header; 60 uint32_t rx_bitmap_319_288 : 32; 61 uint32_t rx_bitmap_351_320 : 32; 62 uint32_t rx_bitmap_383_352 : 32; 63 uint32_t rx_bitmap_415_384 : 32; 64 uint32_t rx_bitmap_447_416 : 32; 65 uint32_t rx_bitmap_479_448 : 32; 66 uint32_t rx_bitmap_511_480 : 32; 67 uint32_t rx_bitmap_543_512 : 32; 68 uint32_t rx_bitmap_575_544 : 32; 69 uint32_t rx_bitmap_607_576 : 32; 70 uint32_t rx_bitmap_639_608 : 32; 71 uint32_t rx_bitmap_671_640 : 32; 72 uint32_t rx_bitmap_703_672 : 32; 73 uint32_t rx_bitmap_735_704 : 32; 74 uint32_t rx_bitmap_767_736 : 32; 75 uint32_t rx_bitmap_799_768 : 32; 76 uint32_t rx_bitmap_831_800 : 32; 77 uint32_t rx_bitmap_863_832 : 32; 78 uint32_t rx_bitmap_895_864 : 32; 79 uint32_t rx_bitmap_927_896 : 32; 80 uint32_t rx_bitmap_959_928 : 32; 81 uint32_t rx_bitmap_991_960 : 32; 82 uint32_t rx_bitmap_1023_992 : 32; 83 uint32_t reserved_24 : 32; 84 uint32_t reserved_25 : 32; 85 uint32_t reserved_26 : 32; 86 uint32_t reserved_27 : 32; 87 uint32_t reserved_28 : 32; 88 uint32_t reserved_29 : 32; 89 uint32_t reserved_30 : 32; 90 uint32_t reserved_31 : 32; 91 #endif 92 }; 93 94 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 95 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_LSB 0 96 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MSB 3 97 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 98 99 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 100 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 101 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 102 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 103 104 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 105 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 106 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 107 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 108 109 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 110 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 111 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 112 #define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 113 114 #define RX_REO_QUEUE_1K_RX_BITMAP_319_288_OFFSET 0x00000004 115 #define RX_REO_QUEUE_1K_RX_BITMAP_319_288_LSB 0 116 #define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MSB 31 117 #define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MASK 0xffffffff 118 119 #define RX_REO_QUEUE_1K_RX_BITMAP_351_320_OFFSET 0x00000008 120 #define RX_REO_QUEUE_1K_RX_BITMAP_351_320_LSB 0 121 #define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MSB 31 122 #define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MASK 0xffffffff 123 124 #define RX_REO_QUEUE_1K_RX_BITMAP_383_352_OFFSET 0x0000000c 125 #define RX_REO_QUEUE_1K_RX_BITMAP_383_352_LSB 0 126 #define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MSB 31 127 #define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MASK 0xffffffff 128 129 #define RX_REO_QUEUE_1K_RX_BITMAP_415_384_OFFSET 0x00000010 130 #define RX_REO_QUEUE_1K_RX_BITMAP_415_384_LSB 0 131 #define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MSB 31 132 #define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MASK 0xffffffff 133 134 #define RX_REO_QUEUE_1K_RX_BITMAP_447_416_OFFSET 0x00000014 135 #define RX_REO_QUEUE_1K_RX_BITMAP_447_416_LSB 0 136 #define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MSB 31 137 #define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MASK 0xffffffff 138 139 #define RX_REO_QUEUE_1K_RX_BITMAP_479_448_OFFSET 0x00000018 140 #define RX_REO_QUEUE_1K_RX_BITMAP_479_448_LSB 0 141 #define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MSB 31 142 #define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MASK 0xffffffff 143 144 #define RX_REO_QUEUE_1K_RX_BITMAP_511_480_OFFSET 0x0000001c 145 #define RX_REO_QUEUE_1K_RX_BITMAP_511_480_LSB 0 146 #define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MSB 31 147 #define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MASK 0xffffffff 148 149 #define RX_REO_QUEUE_1K_RX_BITMAP_543_512_OFFSET 0x00000020 150 #define RX_REO_QUEUE_1K_RX_BITMAP_543_512_LSB 0 151 #define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MSB 31 152 #define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MASK 0xffffffff 153 154 #define RX_REO_QUEUE_1K_RX_BITMAP_575_544_OFFSET 0x00000024 155 #define RX_REO_QUEUE_1K_RX_BITMAP_575_544_LSB 0 156 #define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MSB 31 157 #define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MASK 0xffffffff 158 159 #define RX_REO_QUEUE_1K_RX_BITMAP_607_576_OFFSET 0x00000028 160 #define RX_REO_QUEUE_1K_RX_BITMAP_607_576_LSB 0 161 #define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MSB 31 162 #define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MASK 0xffffffff 163 164 #define RX_REO_QUEUE_1K_RX_BITMAP_639_608_OFFSET 0x0000002c 165 #define RX_REO_QUEUE_1K_RX_BITMAP_639_608_LSB 0 166 #define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MSB 31 167 #define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MASK 0xffffffff 168 169 #define RX_REO_QUEUE_1K_RX_BITMAP_671_640_OFFSET 0x00000030 170 #define RX_REO_QUEUE_1K_RX_BITMAP_671_640_LSB 0 171 #define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MSB 31 172 #define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MASK 0xffffffff 173 174 #define RX_REO_QUEUE_1K_RX_BITMAP_703_672_OFFSET 0x00000034 175 #define RX_REO_QUEUE_1K_RX_BITMAP_703_672_LSB 0 176 #define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MSB 31 177 #define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MASK 0xffffffff 178 179 #define RX_REO_QUEUE_1K_RX_BITMAP_735_704_OFFSET 0x00000038 180 #define RX_REO_QUEUE_1K_RX_BITMAP_735_704_LSB 0 181 #define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MSB 31 182 #define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MASK 0xffffffff 183 184 #define RX_REO_QUEUE_1K_RX_BITMAP_767_736_OFFSET 0x0000003c 185 #define RX_REO_QUEUE_1K_RX_BITMAP_767_736_LSB 0 186 #define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MSB 31 187 #define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MASK 0xffffffff 188 189 #define RX_REO_QUEUE_1K_RX_BITMAP_799_768_OFFSET 0x00000040 190 #define RX_REO_QUEUE_1K_RX_BITMAP_799_768_LSB 0 191 #define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MSB 31 192 #define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MASK 0xffffffff 193 194 #define RX_REO_QUEUE_1K_RX_BITMAP_831_800_OFFSET 0x00000044 195 #define RX_REO_QUEUE_1K_RX_BITMAP_831_800_LSB 0 196 #define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MSB 31 197 #define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MASK 0xffffffff 198 199 #define RX_REO_QUEUE_1K_RX_BITMAP_863_832_OFFSET 0x00000048 200 #define RX_REO_QUEUE_1K_RX_BITMAP_863_832_LSB 0 201 #define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MSB 31 202 #define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MASK 0xffffffff 203 204 #define RX_REO_QUEUE_1K_RX_BITMAP_895_864_OFFSET 0x0000004c 205 #define RX_REO_QUEUE_1K_RX_BITMAP_895_864_LSB 0 206 #define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MSB 31 207 #define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MASK 0xffffffff 208 209 #define RX_REO_QUEUE_1K_RX_BITMAP_927_896_OFFSET 0x00000050 210 #define RX_REO_QUEUE_1K_RX_BITMAP_927_896_LSB 0 211 #define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MSB 31 212 #define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MASK 0xffffffff 213 214 #define RX_REO_QUEUE_1K_RX_BITMAP_959_928_OFFSET 0x00000054 215 #define RX_REO_QUEUE_1K_RX_BITMAP_959_928_LSB 0 216 #define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MSB 31 217 #define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MASK 0xffffffff 218 219 #define RX_REO_QUEUE_1K_RX_BITMAP_991_960_OFFSET 0x00000058 220 #define RX_REO_QUEUE_1K_RX_BITMAP_991_960_LSB 0 221 #define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MSB 31 222 #define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MASK 0xffffffff 223 224 #define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_OFFSET 0x0000005c 225 #define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_LSB 0 226 #define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MSB 31 227 #define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MASK 0xffffffff 228 229 #define RX_REO_QUEUE_1K_RESERVED_24_OFFSET 0x00000060 230 #define RX_REO_QUEUE_1K_RESERVED_24_LSB 0 231 #define RX_REO_QUEUE_1K_RESERVED_24_MSB 31 232 #define RX_REO_QUEUE_1K_RESERVED_24_MASK 0xffffffff 233 234 #define RX_REO_QUEUE_1K_RESERVED_25_OFFSET 0x00000064 235 #define RX_REO_QUEUE_1K_RESERVED_25_LSB 0 236 #define RX_REO_QUEUE_1K_RESERVED_25_MSB 31 237 #define RX_REO_QUEUE_1K_RESERVED_25_MASK 0xffffffff 238 239 #define RX_REO_QUEUE_1K_RESERVED_26_OFFSET 0x00000068 240 #define RX_REO_QUEUE_1K_RESERVED_26_LSB 0 241 #define RX_REO_QUEUE_1K_RESERVED_26_MSB 31 242 #define RX_REO_QUEUE_1K_RESERVED_26_MASK 0xffffffff 243 244 #define RX_REO_QUEUE_1K_RESERVED_27_OFFSET 0x0000006c 245 #define RX_REO_QUEUE_1K_RESERVED_27_LSB 0 246 #define RX_REO_QUEUE_1K_RESERVED_27_MSB 31 247 #define RX_REO_QUEUE_1K_RESERVED_27_MASK 0xffffffff 248 249 #define RX_REO_QUEUE_1K_RESERVED_28_OFFSET 0x00000070 250 #define RX_REO_QUEUE_1K_RESERVED_28_LSB 0 251 #define RX_REO_QUEUE_1K_RESERVED_28_MSB 31 252 #define RX_REO_QUEUE_1K_RESERVED_28_MASK 0xffffffff 253 254 #define RX_REO_QUEUE_1K_RESERVED_29_OFFSET 0x00000074 255 #define RX_REO_QUEUE_1K_RESERVED_29_LSB 0 256 #define RX_REO_QUEUE_1K_RESERVED_29_MSB 31 257 #define RX_REO_QUEUE_1K_RESERVED_29_MASK 0xffffffff 258 259 #define RX_REO_QUEUE_1K_RESERVED_30_OFFSET 0x00000078 260 #define RX_REO_QUEUE_1K_RESERVED_30_LSB 0 261 #define RX_REO_QUEUE_1K_RESERVED_30_MSB 31 262 #define RX_REO_QUEUE_1K_RESERVED_30_MASK 0xffffffff 263 264 #define RX_REO_QUEUE_1K_RESERVED_31_OFFSET 0x0000007c 265 #define RX_REO_QUEUE_1K_RESERVED_31_LSB 0 266 #define RX_REO_QUEUE_1K_RESERVED_31_MSB 31 267 #define RX_REO_QUEUE_1K_RESERVED_31_MASK 0xffffffff 268 269 #endif 270