1 /* 2 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _WBM2SW_COMPLETION_RING_TX_H_ 19 #define _WBM2SW_COMPLETION_RING_TX_H_ 20 21 #include "tx_rate_stats_info.h" 22 #define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_TX 8 23 24 struct wbm2sw_completion_ring_tx { 25 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 26 uint32_t buffer_virt_addr_31_0 : 32; 27 uint32_t buffer_virt_addr_63_32 : 32; 28 uint32_t release_source_module : 3, 29 cache_id : 1, 30 reserved_2a : 2, 31 buffer_or_desc_type : 3, 32 return_buffer_manager : 4, 33 tqm_release_reason : 4, 34 rbm_override_valid : 1, 35 sw_buffer_cookie_11_0 : 12, 36 cookie_conversion_status : 1, 37 wbm_internal_error : 1; 38 uint32_t tqm_status_number : 24, 39 transmit_count : 7, 40 sw_release_details_valid : 1; 41 uint32_t ack_frame_rssi : 8, 42 first_msdu : 1, 43 last_msdu : 1, 44 fw_tx_notify_frame : 3, 45 buffer_timestamp : 19; 46 struct tx_rate_stats_info tx_rate_stats; 47 uint32_t sw_peer_id : 16, 48 tid : 4, 49 sw_buffer_cookie_19_12 : 8, 50 looping_count : 4; 51 #else 52 uint32_t buffer_virt_addr_31_0 : 32; 53 uint32_t buffer_virt_addr_63_32 : 32; 54 uint32_t wbm_internal_error : 1, 55 cookie_conversion_status : 1, 56 sw_buffer_cookie_11_0 : 12, 57 rbm_override_valid : 1, 58 tqm_release_reason : 4, 59 return_buffer_manager : 4, 60 buffer_or_desc_type : 3, 61 reserved_2a : 2, 62 cache_id : 1, 63 release_source_module : 3; 64 uint32_t sw_release_details_valid : 1, 65 transmit_count : 7, 66 tqm_status_number : 24; 67 uint32_t buffer_timestamp : 19, 68 fw_tx_notify_frame : 3, 69 last_msdu : 1, 70 first_msdu : 1, 71 ack_frame_rssi : 8; 72 struct tx_rate_stats_info tx_rate_stats; 73 uint32_t looping_count : 4, 74 sw_buffer_cookie_19_12 : 8, 75 tid : 4, 76 sw_peer_id : 16; 77 #endif 78 }; 79 80 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 81 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_LSB 0 82 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MSB 31 83 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff 84 85 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 86 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_LSB 0 87 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MSB 31 88 #define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff 89 90 #define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 91 #define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_LSB 0 92 #define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MSB 2 93 #define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007 94 95 #define WBM2SW_COMPLETION_RING_TX_CACHE_ID_OFFSET 0x00000008 96 #define WBM2SW_COMPLETION_RING_TX_CACHE_ID_LSB 3 97 #define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MSB 3 98 #define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MASK 0x00000008 99 100 #define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_OFFSET 0x00000008 101 #define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_LSB 4 102 #define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MSB 5 103 #define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MASK 0x00000030 104 105 #define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 106 #define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_LSB 6 107 #define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MSB 8 108 #define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 109 110 #define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 111 #define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_LSB 9 112 #define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MSB 12 113 #define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 114 115 #define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_OFFSET 0x00000008 116 #define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_LSB 13 117 #define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MSB 16 118 #define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MASK 0x0001e000 119 120 #define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_OFFSET 0x00000008 121 #define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_LSB 17 122 #define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MSB 17 123 #define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MASK 0x00020000 124 125 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_OFFSET 0x00000008 126 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_LSB 18 127 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MSB 29 128 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MASK 0x3ffc0000 129 130 #define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 131 #define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_LSB 30 132 #define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MSB 30 133 #define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MASK 0x40000000 134 135 #define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 136 #define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_LSB 31 137 #define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MSB 31 138 #define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MASK 0x80000000 139 140 #define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c 141 #define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_LSB 0 142 #define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MSB 23 143 #define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MASK 0x00ffffff 144 145 #define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_OFFSET 0x0000000c 146 #define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_LSB 24 147 #define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MSB 30 148 #define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MASK 0x7f000000 149 150 #define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c 151 #define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_LSB 31 152 #define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MSB 31 153 #define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MASK 0x80000000 154 155 #define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_OFFSET 0x00000010 156 #define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_LSB 0 157 #define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MSB 7 158 #define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MASK 0x000000ff 159 160 #define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_OFFSET 0x00000010 161 #define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_LSB 8 162 #define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MSB 8 163 #define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MASK 0x00000100 164 165 #define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_OFFSET 0x00000010 166 #define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_LSB 9 167 #define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MSB 9 168 #define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MASK 0x00000200 169 170 #define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 171 #define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_LSB 10 172 #define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MSB 12 173 #define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MASK 0x00001c00 174 175 #define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_OFFSET 0x00000010 176 #define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_LSB 13 177 #define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MSB 31 178 #define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MASK 0xffffe000 179 180 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 181 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 182 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0 183 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 184 185 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 186 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB 1 187 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB 3 188 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e 189 190 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 191 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4 192 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7 193 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0 194 195 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 196 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB 8 197 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB 8 198 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100 199 200 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 201 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9 202 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9 203 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200 204 205 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 206 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB 10 207 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB 11 208 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00 209 210 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 211 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB 12 212 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB 15 213 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0000f000 214 215 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 216 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 16 217 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 16 218 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00010000 219 220 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 221 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB 17 222 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB 28 223 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK 0x1ffe0000 224 225 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_OFFSET 0x00000014 226 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_LSB 29 227 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MSB 31 228 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MASK 0xe0000000 229 230 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 231 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 232 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31 233 #define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff 234 235 #define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_OFFSET 0x0000001c 236 #define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_LSB 0 237 #define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MSB 15 238 #define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MASK 0x0000ffff 239 240 #define WBM2SW_COMPLETION_RING_TX_TID_OFFSET 0x0000001c 241 #define WBM2SW_COMPLETION_RING_TX_TID_LSB 16 242 #define WBM2SW_COMPLETION_RING_TX_TID_MSB 19 243 #define WBM2SW_COMPLETION_RING_TX_TID_MASK 0x000f0000 244 245 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_OFFSET 0x0000001c 246 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_LSB 20 247 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MSB 27 248 #define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MASK 0x0ff00000 249 250 #define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_OFFSET 0x0000001c 251 #define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_LSB 28 252 #define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MSB 31 253 #define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MASK 0xf0000000 254 255 #endif 256