xref: /wlan-driver/fw-api/hw/qcc2072/v1/wbm_release_ring_tx.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 
18 #ifndef _WBM_RELEASE_RING_TX_H_
19 #define _WBM_RELEASE_RING_TX_H_
20 
21 #include "tx_rate_stats_info.h"
22 #include "buffer_addr_info.h"
23 #define NUM_OF_DWORDS_WBM_RELEASE_RING_TX 8
24 
25 struct wbm_release_ring_tx {
26 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
27              struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
28              uint32_t release_source_module                                   :  3,
29                       bm_action                                               :  3,
30                       buffer_or_desc_type                                     :  3,
31                       first_msdu_index                                        :  4,
32                       tqm_release_reason                                      :  4,
33                       rbm_override_valid                                      :  1,
34                       rbm_override                                            :  4,
35                       reserved_2a                                             :  7,
36                       cache_id                                                :  1,
37                       cookie_conversion_status                                :  1,
38                       wbm_internal_error                                      :  1;
39              uint32_t tqm_status_number                                       : 24,
40                       transmit_count                                          :  7,
41                       sw_release_details_valid                                :  1;
42              uint32_t ack_frame_rssi                                          :  8,
43                       first_msdu                                              :  1,
44                       last_msdu                                               :  1,
45                       fw_tx_notify_frame                                      :  3,
46                       buffer_timestamp                                        : 19;
47              struct   tx_rate_stats_info                                        tx_rate_stats;
48              uint32_t sw_peer_id                                              : 16,
49                       tid                                                     :  4,
50                       tqm_status_number_31_24                                 :  8,
51                       looping_count                                           :  4;
52 #else
53              struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
54              uint32_t wbm_internal_error                                      :  1,
55                       cookie_conversion_status                                :  1,
56                       cache_id                                                :  1,
57                       reserved_2a                                             :  7,
58                       rbm_override                                            :  4,
59                       rbm_override_valid                                      :  1,
60                       tqm_release_reason                                      :  4,
61                       first_msdu_index                                        :  4,
62                       buffer_or_desc_type                                     :  3,
63                       bm_action                                               :  3,
64                       release_source_module                                   :  3;
65              uint32_t sw_release_details_valid                                :  1,
66                       transmit_count                                          :  7,
67                       tqm_status_number                                       : 24;
68              uint32_t buffer_timestamp                                        : 19,
69                       fw_tx_notify_frame                                      :  3,
70                       last_msdu                                               :  1,
71                       first_msdu                                              :  1,
72                       ack_frame_rssi                                          :  8;
73              struct   tx_rate_stats_info                                        tx_rate_stats;
74              uint32_t looping_count                                           :  4,
75                       tqm_status_number_31_24                                 :  8,
76                       tid                                                     :  4,
77                       sw_peer_id                                              : 16;
78 #endif
79 };
80 
81 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
82 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB    0
83 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB    31
84 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK   0xffffffff
85 
86 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
87 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB   0
88 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB   7
89 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK  0x000000ff
90 
91 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
92 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
93 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
94 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
95 
96 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
97 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB    12
98 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB    31
99 #define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK   0xfffff000
100 
101 #define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_OFFSET                            0x00000008
102 #define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_LSB                               0
103 #define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MSB                               2
104 #define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MASK                              0x00000007
105 
106 #define WBM_RELEASE_RING_TX_BM_ACTION_OFFSET                                        0x00000008
107 #define WBM_RELEASE_RING_TX_BM_ACTION_LSB                                           3
108 #define WBM_RELEASE_RING_TX_BM_ACTION_MSB                                           5
109 #define WBM_RELEASE_RING_TX_BM_ACTION_MASK                                          0x00000038
110 
111 #define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET                              0x00000008
112 #define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_LSB                                 6
113 #define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MSB                                 8
114 #define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MASK                                0x000001c0
115 
116 #define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_OFFSET                                 0x00000008
117 #define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_LSB                                    9
118 #define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_MSB                                    12
119 #define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_MASK                                   0x00001e00
120 
121 #define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_OFFSET                               0x00000008
122 #define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_LSB                                  13
123 #define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_MSB                                  16
124 #define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_MASK                                 0x0001e000
125 
126 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_OFFSET                               0x00000008
127 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_LSB                                  17
128 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_MSB                                  17
129 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_MASK                                 0x00020000
130 
131 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_OFFSET                                     0x00000008
132 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_LSB                                        18
133 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_MSB                                        21
134 #define WBM_RELEASE_RING_TX_RBM_OVERRIDE_MASK                                       0x003c0000
135 
136 #define WBM_RELEASE_RING_TX_RESERVED_2A_OFFSET                                      0x00000008
137 #define WBM_RELEASE_RING_TX_RESERVED_2A_LSB                                         22
138 #define WBM_RELEASE_RING_TX_RESERVED_2A_MSB                                         28
139 #define WBM_RELEASE_RING_TX_RESERVED_2A_MASK                                        0x1fc00000
140 
141 #define WBM_RELEASE_RING_TX_CACHE_ID_OFFSET                                         0x00000008
142 #define WBM_RELEASE_RING_TX_CACHE_ID_LSB                                            29
143 #define WBM_RELEASE_RING_TX_CACHE_ID_MSB                                            29
144 #define WBM_RELEASE_RING_TX_CACHE_ID_MASK                                           0x20000000
145 
146 #define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET                         0x00000008
147 #define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_LSB                            30
148 #define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_MSB                            30
149 #define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_MASK                           0x40000000
150 
151 #define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_OFFSET                               0x00000008
152 #define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_LSB                                  31
153 #define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_MSB                                  31
154 #define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_MASK                                 0x80000000
155 
156 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_OFFSET                                0x0000000c
157 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_LSB                                   0
158 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MSB                                   23
159 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MASK                                  0x00ffffff
160 
161 #define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_OFFSET                                   0x0000000c
162 #define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_LSB                                      24
163 #define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_MSB                                      30
164 #define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_MASK                                     0x7f000000
165 
166 #define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET                         0x0000000c
167 #define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_LSB                            31
168 #define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_MSB                            31
169 #define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_MASK                           0x80000000
170 
171 #define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_OFFSET                                   0x00000010
172 #define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_LSB                                      0
173 #define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_MSB                                      7
174 #define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_MASK                                     0x000000ff
175 
176 #define WBM_RELEASE_RING_TX_FIRST_MSDU_OFFSET                                       0x00000010
177 #define WBM_RELEASE_RING_TX_FIRST_MSDU_LSB                                          8
178 #define WBM_RELEASE_RING_TX_FIRST_MSDU_MSB                                          8
179 #define WBM_RELEASE_RING_TX_FIRST_MSDU_MASK                                         0x00000100
180 
181 #define WBM_RELEASE_RING_TX_LAST_MSDU_OFFSET                                        0x00000010
182 #define WBM_RELEASE_RING_TX_LAST_MSDU_LSB                                           9
183 #define WBM_RELEASE_RING_TX_LAST_MSDU_MSB                                           9
184 #define WBM_RELEASE_RING_TX_LAST_MSDU_MASK                                          0x00000200
185 
186 #define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET                               0x00000010
187 #define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_LSB                                  10
188 #define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_MSB                                  12
189 #define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_MASK                                 0x00001c00
190 
191 #define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_OFFSET                                 0x00000010
192 #define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_LSB                                    13
193 #define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_MSB                                    31
194 #define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_MASK                                   0xffffe000
195 
196 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET           0x00000014
197 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB              0
198 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB              0
199 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK             0x00000001
200 
201 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET                        0x00000014
202 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB                           1
203 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB                           3
204 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK                          0x0000000e
205 
206 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET                  0x00000014
207 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB                     4
208 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB                     7
209 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK                    0x000000f0
210 
211 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET                      0x00000014
212 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB                         8
213 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB                         8
214 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK                        0x00000100
215 
216 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET                      0x00000014
217 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB                         9
218 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB                         9
219 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK                        0x00000200
220 
221 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET                       0x00000014
222 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB                          10
223 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB                          11
224 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK                         0x00000c00
225 
226 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET                       0x00000014
227 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB                          12
228 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB                          15
229 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK                         0x0000f000
230 
231 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET                 0x00000014
232 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB                    16
233 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB                    16
234 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK                   0x00010000
235 
236 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET                        0x00000014
237 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB                           17
238 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB                           28
239 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK                          0x1ffe0000
240 
241 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_OFFSET                       0x00000014
242 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_LSB                          29
243 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MSB                          31
244 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MASK                         0xe0000000
245 
246 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET              0x00000018
247 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB                 0
248 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB                 31
249 #define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK                0xffffffff
250 
251 #define WBM_RELEASE_RING_TX_SW_PEER_ID_OFFSET                                       0x0000001c
252 #define WBM_RELEASE_RING_TX_SW_PEER_ID_LSB                                          0
253 #define WBM_RELEASE_RING_TX_SW_PEER_ID_MSB                                          15
254 #define WBM_RELEASE_RING_TX_SW_PEER_ID_MASK                                         0x0000ffff
255 
256 #define WBM_RELEASE_RING_TX_TID_OFFSET                                              0x0000001c
257 #define WBM_RELEASE_RING_TX_TID_LSB                                                 16
258 #define WBM_RELEASE_RING_TX_TID_MSB                                                 19
259 #define WBM_RELEASE_RING_TX_TID_MASK                                                0x000f0000
260 
261 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_OFFSET                          0x0000001c
262 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_LSB                             20
263 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_MSB                             27
264 #define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_MASK                            0x0ff00000
265 
266 #define WBM_RELEASE_RING_TX_LOOPING_COUNT_OFFSET                                    0x0000001c
267 #define WBM_RELEASE_RING_TX_LOOPING_COUNT_LSB                                       28
268 #define WBM_RELEASE_RING_TX_LOOPING_COUNT_MSB                                       31
269 #define WBM_RELEASE_RING_TX_LOOPING_COUNT_MASK                                      0xf0000000
270 
271 #endif
272