1 /* 2 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _BUFFER_ADDR_INFO_H_ 18 #define _BUFFER_ADDR_INFO_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 23 // ################ START SUMMARY ################# 24 // 25 // Dword Fields 26 // 0 buffer_addr_31_0[31:0] 27 // 1 buffer_addr_39_32[7:0], return_buffer_manager[10:8], sw_buffer_cookie[31:11] 28 // 29 // ################ END SUMMARY ################# 30 31 #define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2 32 33 struct buffer_addr_info { 34 uint32_t buffer_addr_31_0 : 32; //[31:0] 35 uint32_t buffer_addr_39_32 : 8, //[7:0] 36 return_buffer_manager : 3, //[10:8] 37 sw_buffer_cookie : 21; //[31:11] 38 }; 39 40 /* 41 42 buffer_addr_31_0 43 44 Address (lower 32 bits) of the MSDU buffer OR 45 MSDU_EXTENSION descriptor OR Link Descriptor 46 47 48 49 In case of 'NULL' pointer, this field is set to 0 50 51 <legal all> 52 53 buffer_addr_39_32 54 55 Address (upper 8 bits) of the MSDU buffer OR 56 MSDU_EXTENSION descriptor OR Link Descriptor 57 58 59 60 In case of 'NULL' pointer, this field is set to 0 61 62 <legal all> 63 64 return_buffer_manager 65 66 Consumer: WBM 67 68 Producer: SW/FW 69 70 71 72 In case of 'NULL' pointer, this field is set to 0 73 74 75 76 Indicates to which buffer manager the buffer OR 77 MSDU_EXTENSION descriptor OR link descriptor that is being 78 pointed to shall be returned after the frame has been 79 processed. It is used by WBM for routing purposes. 80 81 82 83 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 84 to the WMB buffer idle list 85 86 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 87 returned to the WMB idle link descriptor idle list 88 89 <enum 2 FW_BM> This buffer shall be returned to the FW 90 91 <enum 3 SW0_BM> This buffer shall be returned to the SW, 92 ring 0 93 94 <enum 4 SW1_BM> This buffer shall be returned to the SW, 95 ring 1 96 97 <enum 5 SW2_BM> This buffer shall be returned to the SW, 98 ring 2 99 100 <enum 6 SW3_BM> This buffer shall be returned to the SW, 101 ring 3 102 103 <enum 7 SW4_BM> This buffer shall be returned to the SW, 104 ring 4 105 106 107 108 <legal all> 109 110 sw_buffer_cookie 111 112 Cookie field exclusively used by SW. 113 114 115 116 In case of 'NULL' pointer, this field is set to 0 117 118 119 120 HW ignores the contents, accept that it passes the 121 programmed value on to other descriptors together with the 122 physical address 123 124 125 126 Field can be used by SW to for example associate the 127 buffers physical address with the virtual address 128 129 The bit definitions as used by SW are within SW HLD 130 specification 131 132 133 134 NOTE1: 135 136 The three most significant bits can have a special 137 meaning in case this struct is embedded in a TX_MPDU_DETAILS 138 STRUCT, and field transmit_bw_restriction is set 139 140 141 142 In case of NON punctured transmission: 143 144 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 145 146 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 147 148 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 149 150 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 151 152 153 154 In case of punctured transmission: 155 156 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 157 158 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 159 160 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 161 162 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 163 164 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 165 166 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 167 168 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 169 170 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 171 172 173 174 Note: a punctured transmission is indicated by the 175 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 176 TLV 177 178 179 180 NOTE 2:The five most significant bits can have a special 181 meaning in case this struct is embedded in an 182 RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is 183 configured for passing on the additional info 184 from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV 185 (FR56821). This is not supported in HastingsPrime, Pine or 186 Moselle. 187 188 189 190 Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS 191 control field 192 193 194 195 Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 196 indicates MPDUs with a QoS control field. 197 198 199 200 201 202 <legal all> 203 */ 204 205 206 /* Description BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0 207 208 Address (lower 32 bits) of the MSDU buffer OR 209 MSDU_EXTENSION descriptor OR Link Descriptor 210 211 212 213 In case of 'NULL' pointer, this field is set to 0 214 215 <legal all> 216 */ 217 #define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET 0x00000000 218 #define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 0 219 #define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 0xffffffff 220 221 /* Description BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32 222 223 Address (upper 8 bits) of the MSDU buffer OR 224 MSDU_EXTENSION descriptor OR Link Descriptor 225 226 227 228 In case of 'NULL' pointer, this field is set to 0 229 230 <legal all> 231 */ 232 #define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET 0x00000004 233 #define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 0 234 #define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 0x000000ff 235 236 /* Description BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER 237 238 Consumer: WBM 239 240 Producer: SW/FW 241 242 243 244 In case of 'NULL' pointer, this field is set to 0 245 246 247 248 Indicates to which buffer manager the buffer OR 249 MSDU_EXTENSION descriptor OR link descriptor that is being 250 pointed to shall be returned after the frame has been 251 processed. It is used by WBM for routing purposes. 252 253 254 255 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 256 to the WMB buffer idle list 257 258 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 259 returned to the WMB idle link descriptor idle list 260 261 <enum 2 FW_BM> This buffer shall be returned to the FW 262 263 <enum 3 SW0_BM> This buffer shall be returned to the SW, 264 ring 0 265 266 <enum 4 SW1_BM> This buffer shall be returned to the SW, 267 ring 1 268 269 <enum 5 SW2_BM> This buffer shall be returned to the SW, 270 ring 2 271 272 <enum 6 SW3_BM> This buffer shall be returned to the SW, 273 ring 3 274 275 <enum 7 SW4_BM> This buffer shall be returned to the SW, 276 ring 4 277 278 279 280 <legal all> 281 */ 282 #define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 283 #define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 8 284 #define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 0x00000700 285 286 /* Description BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE 287 288 Cookie field exclusively used by SW. 289 290 291 292 In case of 'NULL' pointer, this field is set to 0 293 294 295 296 HW ignores the contents, accept that it passes the 297 programmed value on to other descriptors together with the 298 physical address 299 300 301 302 Field can be used by SW to for example associate the 303 buffers physical address with the virtual address 304 305 The bit definitions as used by SW are within SW HLD 306 specification 307 308 309 310 NOTE1: 311 312 The three most significant bits can have a special 313 meaning in case this struct is embedded in a TX_MPDU_DETAILS 314 STRUCT, and field transmit_bw_restriction is set 315 316 317 318 In case of NON punctured transmission: 319 320 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 321 322 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 323 324 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 325 326 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 327 328 329 330 In case of punctured transmission: 331 332 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 333 334 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 335 336 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 337 338 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 339 340 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 341 342 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 343 344 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 345 346 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 347 348 349 350 Note: a punctured transmission is indicated by the 351 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 352 TLV 353 354 355 356 NOTE 2:The five most significant bits can have a special 357 meaning in case this struct is embedded in an 358 RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is 359 configured for passing on the additional info 360 from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV 361 (FR56821). This is not supported in HastingsPrime, Pine or 362 Moselle. 363 364 365 366 Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS 367 control field 368 369 370 371 Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 372 indicates MPDUs with a QoS control field. 373 374 375 376 377 378 <legal all> 379 */ 380 #define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET 0x00000004 381 #define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 11 382 #define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 0xfffff800 383 384 385 #endif // _BUFFER_ADDR_INFO_H_ 386