xref: /wlan-driver/fw-api/hw/qcn6122/reo_flush_queue_status.h (revision 5113495b16420b49004c444715d2daae2066e7dc)
1 /*
2  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #ifndef _REO_FLUSH_QUEUE_STATUS_H_
18 #define _REO_FLUSH_QUEUE_STATUS_H_
19 #if !defined(__ASSEMBLER__)
20 #endif
21 
22 #include "uniform_reo_status_header.h"
23 
24 // ################ START SUMMARY #################
25 //
26 //	Dword	Fields
27 //	0-1	struct uniform_reo_status_header status_header;
28 //	2	error_detected[0], reserved_2a[31:1]
29 //	3	reserved_3a[31:0]
30 //	4	reserved_4a[31:0]
31 //	5	reserved_5a[31:0]
32 //	6	reserved_6a[31:0]
33 //	7	reserved_7a[31:0]
34 //	8	reserved_8a[31:0]
35 //	9	reserved_9a[31:0]
36 //	10	reserved_10a[31:0]
37 //	11	reserved_11a[31:0]
38 //	12	reserved_12a[31:0]
39 //	13	reserved_13a[31:0]
40 //	14	reserved_14a[31:0]
41 //	15	reserved_15a[31:0]
42 //	16	reserved_16a[31:0]
43 //	17	reserved_17a[31:0]
44 //	18	reserved_18a[31:0]
45 //	19	reserved_19a[31:0]
46 //	20	reserved_20a[31:0]
47 //	21	reserved_21a[31:0]
48 //	22	reserved_22a[31:0]
49 //	23	reserved_23a[31:0]
50 //	24	reserved_24a[27:0], looping_count[31:28]
51 //
52 // ################ END SUMMARY #################
53 
54 #define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 25
55 
56 struct reo_flush_queue_status {
57     struct            uniform_reo_status_header                       status_header;
58              uint32_t error_detected                  :  1, //[0]
59                       reserved_2a                     : 31; //[31:1]
60              uint32_t reserved_3a                     : 32; //[31:0]
61              uint32_t reserved_4a                     : 32; //[31:0]
62              uint32_t reserved_5a                     : 32; //[31:0]
63              uint32_t reserved_6a                     : 32; //[31:0]
64              uint32_t reserved_7a                     : 32; //[31:0]
65              uint32_t reserved_8a                     : 32; //[31:0]
66              uint32_t reserved_9a                     : 32; //[31:0]
67              uint32_t reserved_10a                    : 32; //[31:0]
68              uint32_t reserved_11a                    : 32; //[31:0]
69              uint32_t reserved_12a                    : 32; //[31:0]
70              uint32_t reserved_13a                    : 32; //[31:0]
71              uint32_t reserved_14a                    : 32; //[31:0]
72              uint32_t reserved_15a                    : 32; //[31:0]
73              uint32_t reserved_16a                    : 32; //[31:0]
74              uint32_t reserved_17a                    : 32; //[31:0]
75              uint32_t reserved_18a                    : 32; //[31:0]
76              uint32_t reserved_19a                    : 32; //[31:0]
77              uint32_t reserved_20a                    : 32; //[31:0]
78              uint32_t reserved_21a                    : 32; //[31:0]
79              uint32_t reserved_22a                    : 32; //[31:0]
80              uint32_t reserved_23a                    : 32; //[31:0]
81              uint32_t reserved_24a                    : 28, //[27:0]
82                       looping_count                   :  4; //[31:28]
83 };
84 
85 /*
86 
87 struct uniform_reo_status_header status_header
88 
89 			Consumer: SW
90 
91 			Producer: REO
92 
93 
94 
95 			Details that can link this status with the original
96 			command. It also contains info on how long REO took to
97 			execute this command.
98 
99 error_detected
100 
101 			Status of the blocking resource
102 
103 			0: No error has been detected while executing this
104 			command
105 
106 			1: Error detected: The resource to be used for blocking
107 			was already in use.
108 
109 reserved_2a
110 
111 			<legal 0>
112 
113 reserved_3a
114 
115 			<legal 0>
116 
117 reserved_4a
118 
119 			<legal 0>
120 
121 reserved_5a
122 
123 			<legal 0>
124 
125 reserved_6a
126 
127 			<legal 0>
128 
129 reserved_7a
130 
131 			<legal 0>
132 
133 reserved_8a
134 
135 			<legal 0>
136 
137 reserved_9a
138 
139 			<legal 0>
140 
141 reserved_10a
142 
143 			<legal 0>
144 
145 reserved_11a
146 
147 			<legal 0>
148 
149 reserved_12a
150 
151 			<legal 0>
152 
153 reserved_13a
154 
155 			<legal 0>
156 
157 reserved_14a
158 
159 			<legal 0>
160 
161 reserved_15a
162 
163 			<legal 0>
164 
165 reserved_16a
166 
167 			<legal 0>
168 
169 reserved_17a
170 
171 			<legal 0>
172 
173 reserved_18a
174 
175 			<legal 0>
176 
177 reserved_19a
178 
179 			<legal 0>
180 
181 reserved_20a
182 
183 			<legal 0>
184 
185 reserved_21a
186 
187 			<legal 0>
188 
189 reserved_22a
190 
191 			<legal 0>
192 
193 reserved_23a
194 
195 			<legal 0>
196 
197 reserved_24a
198 
199 			<legal 0>
200 
201 looping_count
202 
203 			A count value that indicates the number of times the
204 			producer of entries into this Ring has looped around the
205 			ring.
206 
207 			At initialization time, this value is set to 0. On the
208 			first loop, this value is set to 1. After the max value is
209 			reached allowed by the number of bits for this field, the
210 			count value continues with 0 again.
211 
212 
213 
214 			In case SW is the consumer of the ring entries, it can
215 			use this field to figure out up to where the producer of
216 			entries has created new entries. This eliminates the need to
217 			check where the head pointer' of the ring is located once
218 			the SW starts processing an interrupt indicating that new
219 			entries have been put into this ring...
220 
221 
222 
223 			Also note that SW if it wants only needs to look at the
224 			LSB bit of this count value.
225 
226 			<legal all>
227 */
228 
229 
230  /* EXTERNAL REFERENCE : struct uniform_reo_status_header status_header */
231 
232 
233 /* Description		REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER
234 
235 			Consumer: SW , DEBUG
236 
237 			Producer: REO
238 
239 
240 
241 			The value in this field is equal to value of the
242 			'REO_CMD_Number' field the REO command
243 
244 
245 
246 			This field helps to correlate the statuses with the REO
247 			commands.
248 
249 
250 
251 			<legal all>
252 */
253 #define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
254 #define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
255 #define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
256 
257 /* Description		REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME
258 
259 			Consumer: DEBUG
260 
261 			Producer: REO
262 
263 
264 
265 			The amount of time REO took to excecute the command.
266 			Note that this time does not include the duration of the
267 			command waiting in the command ring, before the execution
268 			started.
269 
270 
271 
272 			In us.
273 
274 
275 
276 			<legal all>
277 */
278 #define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
279 #define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
280 #define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
281 
282 /* Description		REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS
283 
284 			Consumer: DEBUG
285 
286 			Producer: REO
287 
288 
289 
290 			Execution status of the command.
291 
292 
293 
294 			<enum 0 reo_successful_execution> Command has
295 			successfully be executed
296 
297 			<enum 1 reo_blocked_execution> Command could not be
298 			executed as the queue or cache was blocked
299 
300 			<enum 2 reo_failed_execution> Command has encountered
301 			problems when executing, like the queue descriptor not being
302 			valid. None of the status fields in the entire STATUS TLV
303 			are valid.
304 
305 			<enum 3 reo_resource_blocked> Command is NOT  executed
306 			because one or more descriptors were blocked. This is SW
307 			programming mistake.
308 
309 			None of the status fields in the entire STATUS TLV are
310 			valid.
311 
312 
313 
314 			<legal  0-3>
315 */
316 #define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
317 #define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
318 #define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
319 
320 /* Description		REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A
321 
322 			<legal 0>
323 */
324 #define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET    0x00000000
325 #define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB       28
326 #define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK      0xf0000000
327 
328 /* Description		REO_FLUSH_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP
329 
330 			Timestamp at the moment that this status report is
331 			written.
332 
333 
334 
335 			<legal all>
336 */
337 #define REO_FLUSH_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET      0x00000004
338 #define REO_FLUSH_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB         0
339 #define REO_FLUSH_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK        0xffffffff
340 
341 /* Description		REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED
342 
343 			Status of the blocking resource
344 
345 			0: No error has been detected while executing this
346 			command
347 
348 			1: Error detected: The resource to be used for blocking
349 			was already in use.
350 */
351 #define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_OFFSET               0x00000008
352 #define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_LSB                  0
353 #define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_MASK                 0x00000001
354 
355 /* Description		REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A
356 
357 			<legal 0>
358 */
359 #define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_OFFSET                  0x00000008
360 #define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_LSB                     1
361 #define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_MASK                    0xfffffffe
362 
363 /* Description		REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A
364 
365 			<legal 0>
366 */
367 #define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_OFFSET                  0x0000000c
368 #define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_LSB                     0
369 #define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_MASK                    0xffffffff
370 
371 /* Description		REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A
372 
373 			<legal 0>
374 */
375 #define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_OFFSET                  0x00000010
376 #define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_LSB                     0
377 #define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_MASK                    0xffffffff
378 
379 /* Description		REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A
380 
381 			<legal 0>
382 */
383 #define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_OFFSET                  0x00000014
384 #define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_LSB                     0
385 #define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_MASK                    0xffffffff
386 
387 /* Description		REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A
388 
389 			<legal 0>
390 */
391 #define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_OFFSET                  0x00000018
392 #define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_LSB                     0
393 #define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_MASK                    0xffffffff
394 
395 /* Description		REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A
396 
397 			<legal 0>
398 */
399 #define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_OFFSET                  0x0000001c
400 #define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_LSB                     0
401 #define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_MASK                    0xffffffff
402 
403 /* Description		REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A
404 
405 			<legal 0>
406 */
407 #define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_OFFSET                  0x00000020
408 #define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_LSB                     0
409 #define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_MASK                    0xffffffff
410 
411 /* Description		REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A
412 
413 			<legal 0>
414 */
415 #define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_OFFSET                  0x00000024
416 #define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_LSB                     0
417 #define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_MASK                    0xffffffff
418 
419 /* Description		REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A
420 
421 			<legal 0>
422 */
423 #define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_OFFSET                0x00000028
424 #define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_LSB                   0
425 #define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_MASK                  0xffffffff
426 
427 /* Description		REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A
428 
429 			<legal 0>
430 */
431 #define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_OFFSET                0x0000002c
432 #define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_LSB                   0
433 #define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_MASK                  0xffffffff
434 
435 /* Description		REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A
436 
437 			<legal 0>
438 */
439 #define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_OFFSET                0x00000030
440 #define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_LSB                   0
441 #define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_MASK                  0xffffffff
442 
443 /* Description		REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A
444 
445 			<legal 0>
446 */
447 #define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_OFFSET                0x00000034
448 #define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_LSB                   0
449 #define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_MASK                  0xffffffff
450 
451 /* Description		REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A
452 
453 			<legal 0>
454 */
455 #define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_OFFSET                0x00000038
456 #define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_LSB                   0
457 #define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_MASK                  0xffffffff
458 
459 /* Description		REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A
460 
461 			<legal 0>
462 */
463 #define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_OFFSET                0x0000003c
464 #define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_LSB                   0
465 #define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_MASK                  0xffffffff
466 
467 /* Description		REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A
468 
469 			<legal 0>
470 */
471 #define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_OFFSET                0x00000040
472 #define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_LSB                   0
473 #define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_MASK                  0xffffffff
474 
475 /* Description		REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A
476 
477 			<legal 0>
478 */
479 #define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_OFFSET                0x00000044
480 #define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_LSB                   0
481 #define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_MASK                  0xffffffff
482 
483 /* Description		REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A
484 
485 			<legal 0>
486 */
487 #define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_OFFSET                0x00000048
488 #define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_LSB                   0
489 #define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_MASK                  0xffffffff
490 
491 /* Description		REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A
492 
493 			<legal 0>
494 */
495 #define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_OFFSET                0x0000004c
496 #define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_LSB                   0
497 #define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_MASK                  0xffffffff
498 
499 /* Description		REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A
500 
501 			<legal 0>
502 */
503 #define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_OFFSET                0x00000050
504 #define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_LSB                   0
505 #define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_MASK                  0xffffffff
506 
507 /* Description		REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A
508 
509 			<legal 0>
510 */
511 #define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_OFFSET                0x00000054
512 #define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_LSB                   0
513 #define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_MASK                  0xffffffff
514 
515 /* Description		REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A
516 
517 			<legal 0>
518 */
519 #define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_OFFSET                0x00000058
520 #define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_LSB                   0
521 #define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_MASK                  0xffffffff
522 
523 /* Description		REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A
524 
525 			<legal 0>
526 */
527 #define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_OFFSET                0x0000005c
528 #define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_LSB                   0
529 #define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_MASK                  0xffffffff
530 
531 /* Description		REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A
532 
533 			<legal 0>
534 */
535 #define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_OFFSET                0x00000060
536 #define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_LSB                   0
537 #define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_MASK                  0x0fffffff
538 
539 /* Description		REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT
540 
541 			A count value that indicates the number of times the
542 			producer of entries into this Ring has looped around the
543 			ring.
544 
545 			At initialization time, this value is set to 0. On the
546 			first loop, this value is set to 1. After the max value is
547 			reached allowed by the number of bits for this field, the
548 			count value continues with 0 again.
549 
550 
551 
552 			In case SW is the consumer of the ring entries, it can
553 			use this field to figure out up to where the producer of
554 			entries has created new entries. This eliminates the need to
555 			check where the head pointer' of the ring is located once
556 			the SW starts processing an interrupt indicating that new
557 			entries have been put into this ring...
558 
559 
560 
561 			Also note that SW if it wants only needs to look at the
562 			LSB bit of this count value.
563 
564 			<legal all>
565 */
566 #define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_OFFSET               0x00000060
567 #define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_LSB                  28
568 #define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_MASK                 0xf0000000
569 
570 
571 #endif // _REO_FLUSH_QUEUE_STATUS_H_
572