1 /* 2 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_MPDU_DETAILS_H_ 18 #define _RX_MPDU_DETAILS_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "buffer_addr_info.h" 23 #include "rx_mpdu_desc_info.h" 24 25 // ################ START SUMMARY ################# 26 // 27 // Dword Fields 28 // 0-1 struct buffer_addr_info msdu_link_desc_addr_info; 29 // 2-3 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 30 // 31 // ################ END SUMMARY ################# 32 33 #define NUM_OF_DWORDS_RX_MPDU_DETAILS 4 34 35 struct rx_mpdu_details { 36 struct buffer_addr_info msdu_link_desc_addr_info; 37 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; 38 }; 39 40 /* 41 42 struct buffer_addr_info msdu_link_desc_addr_info 43 44 Consumer: REO/SW/FW 45 46 Producer: RXDMA 47 48 49 50 Details of the physical address of the MSDU link 51 descriptor that contains pointers to MSDUs related to this 52 MPDU 53 54 struct rx_mpdu_desc_info rx_mpdu_desc_info_details 55 56 Consumer: REO/SW/FW 57 58 Producer: RXDMA 59 60 61 62 General information related to the MPDU that should be 63 */ 64 65 66 /* EXTERNAL REFERENCE : struct buffer_addr_info msdu_link_desc_addr_info */ 67 68 69 /* Description RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 70 71 Address (lower 32 bits) of the MSDU buffer OR 72 MSDU_EXTENSION descriptor OR Link Descriptor 73 74 75 76 In case of 'NULL' pointer, this field is set to 0 77 78 <legal all> 79 */ 80 #define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 81 #define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 82 #define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 83 84 /* Description RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 85 86 Address (upper 8 bits) of the MSDU buffer OR 87 MSDU_EXTENSION descriptor OR Link Descriptor 88 89 90 91 In case of 'NULL' pointer, this field is set to 0 92 93 <legal all> 94 */ 95 #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 96 #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 97 #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 98 99 /* Description RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 100 101 Consumer: WBM 102 103 Producer: SW/FW 104 105 106 107 In case of 'NULL' pointer, this field is set to 0 108 109 110 111 Indicates to which buffer manager the buffer OR 112 MSDU_EXTENSION descriptor OR link descriptor that is being 113 pointed to shall be returned after the frame has been 114 processed. It is used by WBM for routing purposes. 115 116 117 118 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 119 to the WMB buffer idle list 120 121 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 122 returned to the WMB idle link descriptor idle list 123 124 <enum 2 FW_BM> This buffer shall be returned to the FW 125 126 <enum 3 SW0_BM> This buffer shall be returned to the SW, 127 ring 0 128 129 <enum 4 SW1_BM> This buffer shall be returned to the SW, 130 ring 1 131 132 <enum 5 SW2_BM> This buffer shall be returned to the SW, 133 ring 2 134 135 <enum 6 SW3_BM> This buffer shall be returned to the SW, 136 ring 3 137 138 <enum 7 SW4_BM> This buffer shall be returned to the SW, 139 ring 4 140 141 142 143 <legal all> 144 */ 145 #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 146 #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 147 #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 148 149 /* Description RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 150 151 Cookie field exclusively used by SW. 152 153 154 155 In case of 'NULL' pointer, this field is set to 0 156 157 158 159 HW ignores the contents, accept that it passes the 160 programmed value on to other descriptors together with the 161 physical address 162 163 164 165 Field can be used by SW to for example associate the 166 buffers physical address with the virtual address 167 168 The bit definitions as used by SW are within SW HLD 169 specification 170 171 172 173 NOTE1: 174 175 The three most significant bits can have a special 176 meaning in case this struct is embedded in a TX_MPDU_DETAILS 177 STRUCT, and field transmit_bw_restriction is set 178 179 180 181 In case of NON punctured transmission: 182 183 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 184 185 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 186 187 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 188 189 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 190 191 192 193 In case of punctured transmission: 194 195 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 196 197 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 198 199 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 200 201 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 202 203 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 204 205 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 206 207 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 208 209 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 210 211 212 213 Note: a punctured transmission is indicated by the 214 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 215 TLV 216 217 218 219 NOTE 2:The five most significant bits can have a special 220 meaning in case this struct is embedded in an 221 RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is 222 configured for passing on the additional info 223 from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV 224 (FR56821). This is not supported in HastingsPrime, Pine or 225 Moselle. 226 227 228 229 Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS 230 control field 231 232 233 234 Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 235 indicates MPDUs with a QoS control field. 236 237 238 239 240 241 <legal all> 242 */ 243 #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 244 #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 245 #define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 246 247 /* EXTERNAL REFERENCE : struct rx_mpdu_desc_info rx_mpdu_desc_info_details */ 248 249 250 /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT 251 252 Consumer: REO/SW/FW 253 254 Producer: RXDMA 255 256 257 258 The number of MSDUs within the MPDU 259 260 <legal all> 261 */ 262 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 263 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 264 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff 265 266 /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER 267 268 Consumer: REO/SW/FW 269 270 Producer: RXDMA 271 272 273 274 The field can have two different meanings based on the 275 setting of field 'BAR_frame': 276 277 278 279 'BAR_frame' is NOT set: 280 281 The MPDU sequence number of the received frame. 282 283 284 285 'BAR_frame' is set. 286 287 The MPDU Start sequence number from the BAR frame 288 289 <legal all> 290 */ 291 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 292 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8 293 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00 294 295 /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG 296 297 Consumer: REO/SW/FW 298 299 Producer: RXDMA 300 301 302 303 When set, this MPDU is a fragment and REO should forward 304 this fragment MPDU to the REO destination ring without any 305 reorder checks, pn checks or bitmap update. This implies 306 that REO is forwarding the pointer to the MSDU link 307 descriptor. The destination ring is coming from a 308 programmable register setting in REO 309 310 311 312 <legal all> 313 */ 314 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 315 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20 316 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000 317 318 /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT 319 320 Consumer: REO/SW/FW 321 322 Producer: RXDMA 323 324 325 326 The retry bit setting from the MPDU header of the 327 received frame 328 329 <legal all> 330 */ 331 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 332 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21 333 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000 334 335 /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG 336 337 Consumer: REO/SW/FW 338 339 Producer: RXDMA 340 341 342 343 When set, the MPDU was received as part of an A-MPDU. 344 345 <legal all> 346 */ 347 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 348 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22 349 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000 350 351 /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME 352 353 Consumer: REO/SW/FW 354 355 Producer: RXDMA 356 357 358 359 When set, the received frame is a BAR frame. After 360 processing, this frame shall be pushed to SW or deleted. 361 362 <legal all> 363 */ 364 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 365 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23 366 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000 367 368 /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO 369 370 Consumer: REO/SW/FW 371 372 Producer: RXDMA 373 374 375 376 Copied here by RXDMA from RX_MPDU_END 377 378 When not set, REO will Not perform a PN sequence number 379 check 380 */ 381 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 382 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24 383 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000 384 385 /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID 386 387 When set, OLE found a valid SA entry for all MSDUs in 388 this MPDU 389 390 <legal all> 391 */ 392 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 393 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25 394 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000 395 396 /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 397 398 When set, at least 1 MSDU within the MPDU has an 399 unsuccessful MAC source address search due to the expiration 400 of the search timer. 401 402 <legal all> 403 */ 404 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 405 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26 406 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000 407 408 /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID 409 410 When set, OLE found a valid DA entry for all MSDUs in 411 this MPDU 412 413 <legal all> 414 */ 415 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 416 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27 417 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000 418 419 /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC 420 421 Field Only valid if da_is_valid is set 422 423 424 425 When set, at least one of the DA addresses is a 426 Multicast or Broadcast address. 427 428 <legal all> 429 */ 430 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 431 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28 432 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000 433 434 /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 435 436 When set, at least 1 MSDU within the MPDU has an 437 unsuccessful MAC destination address search due to the 438 expiration of the search timer. 439 440 <legal all> 441 */ 442 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 443 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29 444 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000 445 446 /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU 447 448 Field only valid when first_msdu_in_mpdu_flag is set. 449 450 451 452 When set, the contents in the MSDU buffer contains a 453 'RAW' MPDU. This 'RAW' MPDU might be spread out over 454 multiple MSDU buffers. 455 456 <legal all> 457 */ 458 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 459 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30 460 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 461 462 /* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG 463 464 The More Fragment bit setting from the MPDU header of 465 the received frame 466 467 468 469 <legal all> 470 */ 471 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 472 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31 473 #define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000 474 475 /* Description RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA 476 477 Meta data that SW has programmed in the Peer table entry 478 of the transmitting STA. 479 480 <legal all> 481 */ 482 #define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c 483 #define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 484 #define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff 485 486 487 #endif // _RX_MPDU_DETAILS_H_ 488