1 /* 2 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_MSDU_DETAILS_H_ 18 #define _RX_MSDU_DETAILS_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "buffer_addr_info.h" 23 #include "rx_msdu_desc_info.h" 24 25 // ################ START SUMMARY ################# 26 // 27 // Dword Fields 28 // 0-1 struct buffer_addr_info buffer_addr_info_details; 29 // 2-3 struct rx_msdu_desc_info rx_msdu_desc_info_details; 30 // 31 // ################ END SUMMARY ################# 32 33 #define NUM_OF_DWORDS_RX_MSDU_DETAILS 4 34 35 struct rx_msdu_details { 36 struct buffer_addr_info buffer_addr_info_details; 37 struct rx_msdu_desc_info rx_msdu_desc_info_details; 38 }; 39 40 /* 41 42 struct buffer_addr_info buffer_addr_info_details 43 44 Consumer: REO/SW 45 46 Producer: RXDMA 47 48 49 50 Details of the physical address of the buffer containing 51 an MSDU (or entire MPDU) 52 53 struct rx_msdu_desc_info rx_msdu_desc_info_details 54 55 Consumer: REO/SW 56 57 Producer: RXDMA 58 59 60 61 General information related to the MSDU that should be 62 passed on from RXDMA all the way to to the REO destination 63 ring. 64 */ 65 66 67 /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ 68 69 70 /* Description RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 71 72 Address (lower 32 bits) of the MSDU buffer OR 73 MSDU_EXTENSION descriptor OR Link Descriptor 74 75 76 77 In case of 'NULL' pointer, this field is set to 0 78 79 <legal all> 80 */ 81 #define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 82 #define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 83 #define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 84 85 /* Description RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 86 87 Address (upper 8 bits) of the MSDU buffer OR 88 MSDU_EXTENSION descriptor OR Link Descriptor 89 90 91 92 In case of 'NULL' pointer, this field is set to 0 93 94 <legal all> 95 */ 96 #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 97 #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 98 #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 99 100 /* Description RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER 101 102 Consumer: WBM 103 104 Producer: SW/FW 105 106 107 108 In case of 'NULL' pointer, this field is set to 0 109 110 111 112 Indicates to which buffer manager the buffer OR 113 MSDU_EXTENSION descriptor OR link descriptor that is being 114 pointed to shall be returned after the frame has been 115 processed. It is used by WBM for routing purposes. 116 117 118 119 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 120 to the WMB buffer idle list 121 122 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 123 returned to the WMB idle link descriptor idle list 124 125 <enum 2 FW_BM> This buffer shall be returned to the FW 126 127 <enum 3 SW0_BM> This buffer shall be returned to the SW, 128 ring 0 129 130 <enum 4 SW1_BM> This buffer shall be returned to the SW, 131 ring 1 132 133 <enum 5 SW2_BM> This buffer shall be returned to the SW, 134 ring 2 135 136 <enum 6 SW3_BM> This buffer shall be returned to the SW, 137 ring 3 138 139 <enum 7 SW4_BM> This buffer shall be returned to the SW, 140 ring 4 141 142 143 144 <legal all> 145 */ 146 #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 147 #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 148 #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 149 150 /* Description RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE 151 152 Cookie field exclusively used by SW. 153 154 155 156 In case of 'NULL' pointer, this field is set to 0 157 158 159 160 HW ignores the contents, accept that it passes the 161 programmed value on to other descriptors together with the 162 physical address 163 164 165 166 Field can be used by SW to for example associate the 167 buffers physical address with the virtual address 168 169 The bit definitions as used by SW are within SW HLD 170 specification 171 172 173 174 NOTE1: 175 176 The three most significant bits can have a special 177 meaning in case this struct is embedded in a TX_MPDU_DETAILS 178 STRUCT, and field transmit_bw_restriction is set 179 180 181 182 In case of NON punctured transmission: 183 184 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 185 186 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 187 188 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 189 190 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 191 192 193 194 In case of punctured transmission: 195 196 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 197 198 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 199 200 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 201 202 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 203 204 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 205 206 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 207 208 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 209 210 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 211 212 213 214 Note: a punctured transmission is indicated by the 215 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 216 TLV 217 218 219 220 NOTE 2:The five most significant bits can have a special 221 meaning in case this struct is embedded in an 222 RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is 223 configured for passing on the additional info 224 from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV 225 (FR56821). This is not supported in HastingsPrime, Pine or 226 Moselle. 227 228 229 230 Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS 231 control field 232 233 234 235 Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 236 indicates MPDUs with a QoS control field. 237 238 239 240 241 242 <legal all> 243 */ 244 #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 245 #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 246 #define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 247 248 /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ 249 250 251 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG 252 253 Parsed from RX_MSDU_END TLV . In the case MSDU spans 254 over multiple buffers, this field will be valid in the Last 255 buffer used by the MSDU 256 257 258 259 <enum 0 Not_first_msdu> This is not the first MSDU in 260 the MPDU. 261 262 <enum 1 first_msdu> This MSDU is the first one in the 263 MPDU. 264 265 266 267 <legal all> 268 */ 269 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 270 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 271 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 272 273 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG 274 275 Consumer: WBM/REO/SW/FW 276 277 Producer: RXDMA 278 279 280 281 Parsed from RX_MSDU_END TLV . In the case MSDU spans 282 over multiple buffers, this field will be valid in the Last 283 buffer used by the MSDU 284 285 286 287 <enum 0 Not_last_msdu> There are more MSDUs linked to 288 this MSDU that belongs to this MPDU 289 290 <enum 1 Last_msdu> this MSDU is the last one in the 291 MPDU. This setting is only allowed in combination with 292 'Msdu_continuation' set to 0. This implies that when an msdu 293 is spread out over multiple buffers and thus 294 msdu_continuation is set, only for the very last buffer of 295 the msdu, can the 'last_msdu_in_mpdu_flag' be set. 296 297 298 299 When both first_msdu_in_mpdu_flag and 300 last_msdu_in_mpdu_flag are set, the MPDU that this MSDU 301 belongs to only contains a single MSDU. 302 303 304 305 306 307 <legal all> 308 */ 309 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 310 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 311 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 312 313 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION 314 315 When set, this MSDU buffer was not able to hold the 316 entire MSDU. The next buffer will therefor contain 317 additional information related to this MSDU. 318 319 320 321 <legal all> 322 */ 323 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008 324 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 325 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 326 327 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH 328 329 Parsed from RX_MSDU_START TLV . In the case MSDU spans 330 over multiple buffers, this field will be valid in the First 331 buffer used by MSDU. 332 333 334 335 Full MSDU length in bytes after decapsulation. 336 337 338 339 This field is still valid for MPDU frames without 340 A-MSDU. It still represents MSDU length after decapsulation 341 342 343 344 Or in case of RAW MPDUs, it indicates the length of the 345 entire MPDU (without FCS field) 346 347 <legal all> 348 */ 349 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008 350 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 351 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 352 353 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION 354 355 Parsed from RX_MSDU_END TLV . In the case MSDU spans 356 over multiple buffers, this field will be valid in the Last 357 buffer used by the MSDU 358 359 360 361 The ID of the REO exit ring where the MSDU frame shall 362 push after (MPDU level) reordering has finished. 363 364 365 366 <enum 0 reo_destination_tcl> Reo will push the frame 367 into the REO2TCL ring 368 369 <enum 1 reo_destination_sw1> Reo will push the frame 370 into the REO2SW1 ring 371 372 <enum 2 reo_destination_sw2> Reo will push the frame 373 into the REO2SW2 ring 374 375 <enum 3 reo_destination_sw3> Reo will push the frame 376 into the REO2SW3 ring 377 378 <enum 4 reo_destination_sw4> Reo will push the frame 379 into the REO2SW4 ring 380 381 <enum 5 reo_destination_release> Reo will push the frame 382 into the REO_release ring 383 384 <enum 6 reo_destination_fw> Reo will push the frame into 385 the REO2FW ring 386 387 <enum 7 reo_destination_sw5> Reo will push the frame 388 into the REO2SW5 ring (REO remaps this in chips without 389 REO2SW5 ring, e.g. Pine) 390 391 <enum 8 reo_destination_sw6> Reo will push the frame 392 into the REO2SW6 ring (REO remaps this in chips without 393 REO2SW6 ring, e.g. Pine) 394 395 <enum 9 reo_destination_9> REO remaps this <enum 10 396 reo_destination_10> REO remaps this 397 398 <enum 11 reo_destination_11> REO remaps this 399 400 <enum 12 reo_destination_12> REO remaps this <enum 13 401 reo_destination_13> REO remaps this 402 403 <enum 14 reo_destination_14> REO remaps this 404 405 <enum 15 reo_destination_15> REO remaps this 406 407 <enum 16 reo_destination_16> REO remaps this 408 409 <enum 17 reo_destination_17> REO remaps this 410 411 <enum 18 reo_destination_18> REO remaps this 412 413 <enum 19 reo_destination_19> REO remaps this 414 415 <enum 20 reo_destination_20> REO remaps this 416 417 <enum 21 reo_destination_21> REO remaps this 418 419 <enum 22 reo_destination_22> REO remaps this 420 421 <enum 23 reo_destination_23> REO remaps this 422 423 <enum 24 reo_destination_24> REO remaps this 424 425 <enum 25 reo_destination_25> REO remaps this 426 427 <enum 26 reo_destination_26> REO remaps this 428 429 <enum 27 reo_destination_27> REO remaps this 430 431 <enum 28 reo_destination_28> REO remaps this 432 433 <enum 29 reo_destination_29> REO remaps this 434 435 <enum 30 reo_destination_30> REO remaps this 436 437 <enum 31 reo_destination_31> REO remaps this 438 439 440 441 <legal all> 442 */ 443 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000008 444 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 445 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 446 447 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP 448 449 Parsed from RX_MSDU_END TLV . In the case MSDU spans 450 over multiple buffers, this field will be valid in the Last 451 buffer used by the MSDU 452 453 454 455 When set, REO shall drop this MSDU and not forward it to 456 any other ring... 457 458 <legal all> 459 */ 460 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008 461 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 462 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 463 464 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID 465 466 Parsed from RX_MSDU_END TLV . In the case MSDU spans 467 over multiple buffers, this field will be valid in the Last 468 buffer used by the MSDU 469 470 471 472 Indicates that OLE found a valid SA entry for this MSDU 473 474 <legal all> 475 */ 476 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 477 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 478 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 479 480 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 481 482 Parsed from RX_MSDU_END TLV . In the case MSDU spans 483 over multiple buffers, this field will be valid in the Last 484 buffer used by the MSDU 485 486 487 488 Indicates an unsuccessful MAC source address search due 489 to the expiring of the search timer for this MSDU 490 491 <legal all> 492 */ 493 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 494 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 495 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 496 497 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID 498 499 Parsed from RX_MSDU_END TLV . In the case MSDU spans 500 over multiple buffers, this field will be valid in the Last 501 buffer used by the MSDU 502 503 504 505 Indicates that OLE found a valid DA entry for this MSDU 506 507 <legal all> 508 */ 509 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 510 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 511 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 512 513 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC 514 515 Field Only valid if da_is_valid is set 516 517 518 519 Indicates the DA address was a Multicast of Broadcast 520 address for this MSDU 521 522 <legal all> 523 */ 524 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 525 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 526 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 527 528 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 529 530 Parsed from RX_MSDU_END TLV . In the case MSDU spans 531 over multiple buffers, this field will be valid in the Last 532 buffer used by the MSDU 533 534 535 536 Indicates an unsuccessful MAC destination address search 537 due to the expiring of the search timer for this MSDU 538 539 <legal all> 540 */ 541 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 542 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 543 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 544 545 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB 546 547 Passed on from 'RX_MSDU_END' TLV (only the MSB is 548 reported as the LSB is always zero) 549 550 Number of bytes padded to make sure that the L3 header 551 will always start of a Dword boundary 552 553 <legal all> 554 */ 555 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000008 556 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 557 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 558 559 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL 560 561 Passed on from 'RX_ATTENTION' TLV 562 563 Indicates that the computed checksum did not match the 564 checksum in the TCP/UDP header. 565 566 <legal all> 567 */ 568 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000008 569 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 570 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 571 572 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL 573 574 Passed on from 'RX_ATTENTION' TLV 575 576 Indicates that the computed checksum did not match the 577 checksum in the IP header. 578 579 <legal all> 580 */ 581 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000008 582 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 583 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 584 585 /* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU 586 587 Passed on from 'RX_MPDU_INFO' structure in 588 'RX_MPDU_START' TLV 589 590 Set to 1 by RXOLE when it has not performed any 802.11 591 to Ethernet/Natvie WiFi header conversion on this MPDU. 592 593 <legal all> 594 */ 595 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 596 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 597 #define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 598 599 /* Description RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0 600 601 Passed on from 'RX_MSDU_END' TLV (one MSB is omitted) 602 603 Based on a register configuration in RXDMA, this field 604 will contain: 605 606 The offset in the address search table which matches the 607 MAC source address 608 609 OR 610 611 612 613 'sw_peer_id' from the address search entry corresponding 614 to the source address of the MSDU 615 616 <legal all> 617 */ 618 #define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000000c 619 #define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 620 #define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff 621 622 /* Description RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0 623 624 Passed on from 'RX_MPDU_INFO' structure in 625 'RX_MPDU_START' TLV (one MSB is omitted) 626 627 628 629 Based on a register configuration in RXDMA, this field 630 will contain: 631 632 The index of the address search entry corresponding to 633 this MPDU (a value of 0xFFFF indicates an invalid AST index, 634 meaning that no AST entry was found or no AST search was 635 performed) 636 637 638 639 OR: 640 641 642 643 'sw_peer_id' from the address search entry corresponding 644 to this MPDU (in case of ndp or phy_err or 645 AST_based_lookup_valid == 0, this field will be set to 0) 646 647 <legal all> 648 */ 649 #define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000000c 650 #define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 651 #define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 652 653 /* Description RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS 654 655 Passed on from 'RX_MPDU_INFO' structure in 656 'RX_MPDU_START' TLV 657 658 Set if the 'from DS' bit is set in the frame control. 659 660 <legal all> 661 */ 662 #define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000000c 663 #define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 664 #define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 665 666 /* Description RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS 667 668 Passed on from 'RX_MPDU_INFO' structure in 669 'RX_MPDU_START' TLV 670 671 Set if the 'to DS' bit is set in the frame control. 672 673 <legal all> 674 */ 675 #define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000000c 676 #define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 677 #define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 678 679 680 #endif // _RX_MSDU_DETAILS_H_ 681