1 /* 2 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_MSDU_LINK_H_ 18 #define _RX_MSDU_LINK_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "uniform_descriptor_header.h" 23 #include "buffer_addr_info.h" 24 #include "rx_msdu_details.h" 25 26 // ################ START SUMMARY ################# 27 // 28 // Dword Fields 29 // 0 struct uniform_descriptor_header descriptor_header; 30 // 1-2 struct buffer_addr_info next_msdu_link_desc_addr_info; 31 // 3 receive_queue_number[15:0], first_rx_msdu_link_struct[16], reserved_3a[31:17] 32 // 4 pn_31_0[31:0] 33 // 5 pn_63_32[31:0] 34 // 6 pn_95_64[31:0] 35 // 7 pn_127_96[31:0] 36 // 8-11 struct rx_msdu_details msdu_0; 37 // 12-15 struct rx_msdu_details msdu_1; 38 // 16-19 struct rx_msdu_details msdu_2; 39 // 20-23 struct rx_msdu_details msdu_3; 40 // 24-27 struct rx_msdu_details msdu_4; 41 // 28-31 struct rx_msdu_details msdu_5; 42 // 43 // ################ END SUMMARY ################# 44 45 #define NUM_OF_DWORDS_RX_MSDU_LINK 32 46 47 struct rx_msdu_link { 48 struct uniform_descriptor_header descriptor_header; 49 struct buffer_addr_info next_msdu_link_desc_addr_info; 50 uint32_t receive_queue_number : 16, //[15:0] 51 first_rx_msdu_link_struct : 1, //[16] 52 reserved_3a : 15; //[31:17] 53 uint32_t pn_31_0 : 32; //[31:0] 54 uint32_t pn_63_32 : 32; //[31:0] 55 uint32_t pn_95_64 : 32; //[31:0] 56 uint32_t pn_127_96 : 32; //[31:0] 57 struct rx_msdu_details msdu_0; 58 struct rx_msdu_details msdu_1; 59 struct rx_msdu_details msdu_2; 60 struct rx_msdu_details msdu_3; 61 struct rx_msdu_details msdu_4; 62 struct rx_msdu_details msdu_5; 63 }; 64 65 /* 66 67 struct uniform_descriptor_header descriptor_header 68 69 Details about which module owns this struct. 70 71 Note that sub field Buffer_type shall be set to 72 Receive_MSDU_Link_descriptor 73 74 struct buffer_addr_info next_msdu_link_desc_addr_info 75 76 Details of the physical address of the next MSDU link 77 descriptor that contains info about additional MSDUs that 78 are part of this MPDU. 79 80 receive_queue_number 81 82 Indicates the Receive queue to which this MPDU 83 descriptor belongs 84 85 Used for tracking, finding bugs and debugging. 86 87 <legal all> 88 89 first_rx_msdu_link_struct 90 91 When set, this RX_MSDU_link descriptor is the first one 92 in the MSDU link list. Field MSDU_0 points to the very first 93 MSDU buffer descriptor in the MPDU 94 95 <legal all> 96 97 reserved_3a 98 99 <legal 0> 100 101 pn_31_0 102 103 104 105 106 31-0 bits of the 256-bit packet number bitmap. 107 108 <legal all> 109 110 pn_63_32 111 112 113 114 115 63-32 bits of the 256-bit packet number bitmap. 116 117 <legal all> 118 119 pn_95_64 120 121 122 123 124 95-64 bits of the 256-bit packet number bitmap. 125 126 <legal all> 127 128 pn_127_96 129 130 131 132 133 127-96 bits of the 256-bit packet number bitmap. 134 135 <legal all> 136 137 struct rx_msdu_details msdu_0 138 139 When First_RX_MSDU_link_struct is set, this MSDU is the 140 first in the MPDU 141 142 143 144 When First_RX_MSDU_link_struct is NOT set, this MSDU 145 follows the last MSDU in the previous RX_MSDU_link data 146 structure 147 148 struct rx_msdu_details msdu_1 149 150 Details of next MSDU in this (MSDU flow) linked list 151 152 struct rx_msdu_details msdu_2 153 154 Details of next MSDU in this (MSDU flow) linked list 155 156 struct rx_msdu_details msdu_3 157 158 Details of next MSDU in this (MSDU flow) linked list 159 160 struct rx_msdu_details msdu_4 161 162 Details of next MSDU in this (MSDU flow) linked list 163 164 struct rx_msdu_details msdu_5 165 166 Details of next MSDU in this (MSDU flow) linked list 167 */ 168 169 170 /* EXTERNAL REFERENCE : struct uniform_descriptor_header descriptor_header */ 171 172 173 /* Description RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER 174 175 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 176 177 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 178 179 180 181 The owner of this data structure: 182 183 <enum 0 WBM_owned> Buffer Manager currently owns this 184 data structure. 185 186 <enum 1 SW_OR_FW_owned> Software of FW currently owns 187 this data structure. 188 189 <enum 2 TQM_owned> Transmit Queue Manager currently owns 190 this data structure. 191 192 <enum 3 RXDMA_owned> Receive DMA currently owns this 193 data structure. 194 195 <enum 4 REO_owned> Reorder currently owns this data 196 structure. 197 198 <enum 5 SWITCH_owned> SWITCH currently owns this data 199 structure. 200 201 202 203 <legal 0-5> 204 */ 205 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 206 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_LSB 0 207 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 208 209 /* Description RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE 210 211 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 212 213 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 214 215 216 217 Field describing what contents format is of this 218 descriptor 219 220 221 222 <enum 0 Transmit_MSDU_Link_descriptor > 223 224 <enum 1 Transmit_MPDU_Link_descriptor > 225 226 <enum 2 Transmit_MPDU_Queue_head_descriptor> 227 228 <enum 3 Transmit_MPDU_Queue_ext_descriptor> 229 230 <enum 4 Transmit_flow_descriptor> 231 232 <enum 5 Transmit_buffer > NOT TO BE USED: 233 234 235 236 <enum 6 Receive_MSDU_Link_descriptor > 237 238 <enum 7 Receive_MPDU_Link_descriptor > 239 240 <enum 8 Receive_REO_queue_descriptor > 241 242 <enum 9 Receive_REO_queue_ext_descriptor > 243 244 245 246 <enum 10 Receive_buffer > 247 248 249 250 <enum 11 Idle_link_list_entry> 251 252 253 254 <legal 0-11> 255 */ 256 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 257 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 258 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 259 260 /* Description RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A 261 262 <legal 0> 263 */ 264 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 265 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 266 #define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 267 268 /* EXTERNAL REFERENCE : struct buffer_addr_info next_msdu_link_desc_addr_info */ 269 270 271 /* Description RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 272 273 Address (lower 32 bits) of the MSDU buffer OR 274 MSDU_EXTENSION descriptor OR Link Descriptor 275 276 277 278 In case of 'NULL' pointer, this field is set to 0 279 280 <legal all> 281 */ 282 #define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000004 283 #define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 284 #define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 285 286 /* Description RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 287 288 Address (upper 8 bits) of the MSDU buffer OR 289 MSDU_EXTENSION descriptor OR Link Descriptor 290 291 292 293 In case of 'NULL' pointer, this field is set to 0 294 295 <legal all> 296 */ 297 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000008 298 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 299 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 300 301 /* Description RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 302 303 Consumer: WBM 304 305 Producer: SW/FW 306 307 308 309 In case of 'NULL' pointer, this field is set to 0 310 311 312 313 Indicates to which buffer manager the buffer OR 314 MSDU_EXTENSION descriptor OR link descriptor that is being 315 pointed to shall be returned after the frame has been 316 processed. It is used by WBM for routing purposes. 317 318 319 320 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 321 to the WMB buffer idle list 322 323 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 324 returned to the WMB idle link descriptor idle list 325 326 <enum 2 FW_BM> This buffer shall be returned to the FW 327 328 <enum 3 SW0_BM> This buffer shall be returned to the SW, 329 ring 0 330 331 <enum 4 SW1_BM> This buffer shall be returned to the SW, 332 ring 1 333 334 <enum 5 SW2_BM> This buffer shall be returned to the SW, 335 ring 2 336 337 <enum 6 SW3_BM> This buffer shall be returned to the SW, 338 ring 3 339 340 <enum 7 SW4_BM> This buffer shall be returned to the SW, 341 ring 4 342 343 344 345 <legal all> 346 */ 347 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 348 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 349 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 350 351 /* Description RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 352 353 Cookie field exclusively used by SW. 354 355 356 357 In case of 'NULL' pointer, this field is set to 0 358 359 360 361 HW ignores the contents, accept that it passes the 362 programmed value on to other descriptors together with the 363 physical address 364 365 366 367 Field can be used by SW to for example associate the 368 buffers physical address with the virtual address 369 370 The bit definitions as used by SW are within SW HLD 371 specification 372 373 374 375 NOTE1: 376 377 The three most significant bits can have a special 378 meaning in case this struct is embedded in a TX_MPDU_DETAILS 379 STRUCT, and field transmit_bw_restriction is set 380 381 382 383 In case of NON punctured transmission: 384 385 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 386 387 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 388 389 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 390 391 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 392 393 394 395 In case of punctured transmission: 396 397 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 398 399 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 400 401 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 402 403 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 404 405 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 406 407 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 408 409 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 410 411 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 412 413 414 415 Note: a punctured transmission is indicated by the 416 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 417 TLV 418 419 420 421 NOTE 2:The five most significant bits can have a special 422 meaning in case this struct is embedded in an 423 RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is 424 configured for passing on the additional info 425 from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV 426 (FR56821). This is not supported in HastingsPrime, Pine or 427 Moselle. 428 429 430 431 Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS 432 control field 433 434 435 436 Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 437 indicates MPDUs with a QoS control field. 438 439 440 441 442 443 <legal all> 444 */ 445 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000008 446 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 447 #define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 448 449 /* Description RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER 450 451 Indicates the Receive queue to which this MPDU 452 descriptor belongs 453 454 Used for tracking, finding bugs and debugging. 455 456 <legal all> 457 */ 458 #define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c 459 #define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_LSB 0 460 #define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff 461 462 /* Description RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT 463 464 When set, this RX_MSDU_link descriptor is the first one 465 in the MSDU link list. Field MSDU_0 points to the very first 466 MSDU buffer descriptor in the MPDU 467 468 <legal all> 469 */ 470 #define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_OFFSET 0x0000000c 471 #define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_LSB 16 472 #define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_MASK 0x00010000 473 474 /* Description RX_MSDU_LINK_3_RESERVED_3A 475 476 <legal 0> 477 */ 478 #define RX_MSDU_LINK_3_RESERVED_3A_OFFSET 0x0000000c 479 #define RX_MSDU_LINK_3_RESERVED_3A_LSB 17 480 #define RX_MSDU_LINK_3_RESERVED_3A_MASK 0xfffe0000 481 482 /* Description RX_MSDU_LINK_4_PN_31_0 483 484 485 486 487 31-0 bits of the 256-bit packet number bitmap. 488 489 <legal all> 490 */ 491 #define RX_MSDU_LINK_4_PN_31_0_OFFSET 0x00000010 492 #define RX_MSDU_LINK_4_PN_31_0_LSB 0 493 #define RX_MSDU_LINK_4_PN_31_0_MASK 0xffffffff 494 495 /* Description RX_MSDU_LINK_5_PN_63_32 496 497 498 499 500 63-32 bits of the 256-bit packet number bitmap. 501 502 <legal all> 503 */ 504 #define RX_MSDU_LINK_5_PN_63_32_OFFSET 0x00000014 505 #define RX_MSDU_LINK_5_PN_63_32_LSB 0 506 #define RX_MSDU_LINK_5_PN_63_32_MASK 0xffffffff 507 508 /* Description RX_MSDU_LINK_6_PN_95_64 509 510 511 512 513 95-64 bits of the 256-bit packet number bitmap. 514 515 <legal all> 516 */ 517 #define RX_MSDU_LINK_6_PN_95_64_OFFSET 0x00000018 518 #define RX_MSDU_LINK_6_PN_95_64_LSB 0 519 #define RX_MSDU_LINK_6_PN_95_64_MASK 0xffffffff 520 521 /* Description RX_MSDU_LINK_7_PN_127_96 522 523 524 525 526 127-96 bits of the 256-bit packet number bitmap. 527 528 <legal all> 529 */ 530 #define RX_MSDU_LINK_7_PN_127_96_OFFSET 0x0000001c 531 #define RX_MSDU_LINK_7_PN_127_96_LSB 0 532 #define RX_MSDU_LINK_7_PN_127_96_MASK 0xffffffff 533 534 /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_0 */ 535 536 537 /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ 538 539 540 /* Description RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 541 542 Address (lower 32 bits) of the MSDU buffer OR 543 MSDU_EXTENSION descriptor OR Link Descriptor 544 545 546 547 In case of 'NULL' pointer, this field is set to 0 548 549 <legal all> 550 */ 551 #define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000020 552 #define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 553 #define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 554 555 /* Description RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 556 557 Address (upper 8 bits) of the MSDU buffer OR 558 MSDU_EXTENSION descriptor OR Link Descriptor 559 560 561 562 In case of 'NULL' pointer, this field is set to 0 563 564 <legal all> 565 */ 566 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000024 567 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 568 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 569 570 /* Description RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER 571 572 Consumer: WBM 573 574 Producer: SW/FW 575 576 577 578 In case of 'NULL' pointer, this field is set to 0 579 580 581 582 Indicates to which buffer manager the buffer OR 583 MSDU_EXTENSION descriptor OR link descriptor that is being 584 pointed to shall be returned after the frame has been 585 processed. It is used by WBM for routing purposes. 586 587 588 589 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 590 to the WMB buffer idle list 591 592 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 593 returned to the WMB idle link descriptor idle list 594 595 <enum 2 FW_BM> This buffer shall be returned to the FW 596 597 <enum 3 SW0_BM> This buffer shall be returned to the SW, 598 ring 0 599 600 <enum 4 SW1_BM> This buffer shall be returned to the SW, 601 ring 1 602 603 <enum 5 SW2_BM> This buffer shall be returned to the SW, 604 ring 2 605 606 <enum 6 SW3_BM> This buffer shall be returned to the SW, 607 ring 3 608 609 <enum 7 SW4_BM> This buffer shall be returned to the SW, 610 ring 4 611 612 613 614 <legal all> 615 */ 616 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 617 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 618 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 619 620 /* Description RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE 621 622 Cookie field exclusively used by SW. 623 624 625 626 In case of 'NULL' pointer, this field is set to 0 627 628 629 630 HW ignores the contents, accept that it passes the 631 programmed value on to other descriptors together with the 632 physical address 633 634 635 636 Field can be used by SW to for example associate the 637 buffers physical address with the virtual address 638 639 The bit definitions as used by SW are within SW HLD 640 specification 641 642 643 644 NOTE1: 645 646 The three most significant bits can have a special 647 meaning in case this struct is embedded in a TX_MPDU_DETAILS 648 STRUCT, and field transmit_bw_restriction is set 649 650 651 652 In case of NON punctured transmission: 653 654 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 655 656 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 657 658 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 659 660 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 661 662 663 664 In case of punctured transmission: 665 666 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 667 668 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 669 670 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 671 672 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 673 674 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 675 676 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 677 678 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 679 680 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 681 682 683 684 Note: a punctured transmission is indicated by the 685 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 686 TLV 687 688 689 690 NOTE 2:The five most significant bits can have a special 691 meaning in case this struct is embedded in an 692 RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is 693 configured for passing on the additional info 694 from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV 695 (FR56821). This is not supported in HastingsPrime, Pine or 696 Moselle. 697 698 699 700 Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS 701 control field 702 703 704 705 Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 706 indicates MPDUs with a QoS control field. 707 708 709 710 711 712 <legal all> 713 */ 714 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000024 715 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 716 #define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 717 718 /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ 719 720 721 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG 722 723 Parsed from RX_MSDU_END TLV . In the case MSDU spans 724 over multiple buffers, this field will be valid in the Last 725 buffer used by the MSDU 726 727 728 729 <enum 0 Not_first_msdu> This is not the first MSDU in 730 the MPDU. 731 732 <enum 1 first_msdu> This MSDU is the first one in the 733 MPDU. 734 735 736 737 <legal all> 738 */ 739 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 740 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 741 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 742 743 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG 744 745 Consumer: WBM/REO/SW/FW 746 747 Producer: RXDMA 748 749 750 751 Parsed from RX_MSDU_END TLV . In the case MSDU spans 752 over multiple buffers, this field will be valid in the Last 753 buffer used by the MSDU 754 755 756 757 <enum 0 Not_last_msdu> There are more MSDUs linked to 758 this MSDU that belongs to this MPDU 759 760 <enum 1 Last_msdu> this MSDU is the last one in the 761 MPDU. This setting is only allowed in combination with 762 'Msdu_continuation' set to 0. This implies that when an msdu 763 is spread out over multiple buffers and thus 764 msdu_continuation is set, only for the very last buffer of 765 the msdu, can the 'last_msdu_in_mpdu_flag' be set. 766 767 768 769 When both first_msdu_in_mpdu_flag and 770 last_msdu_in_mpdu_flag are set, the MPDU that this MSDU 771 belongs to only contains a single MSDU. 772 773 774 775 776 777 <legal all> 778 */ 779 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 780 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 781 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 782 783 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION 784 785 When set, this MSDU buffer was not able to hold the 786 entire MSDU. The next buffer will therefor contain 787 additional information related to this MSDU. 788 789 790 791 <legal all> 792 */ 793 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000028 794 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 795 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 796 797 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH 798 799 Parsed from RX_MSDU_START TLV . In the case MSDU spans 800 over multiple buffers, this field will be valid in the First 801 buffer used by MSDU. 802 803 804 805 Full MSDU length in bytes after decapsulation. 806 807 808 809 This field is still valid for MPDU frames without 810 A-MSDU. It still represents MSDU length after decapsulation 811 812 813 814 Or in case of RAW MPDUs, it indicates the length of the 815 entire MPDU (without FCS field) 816 817 <legal all> 818 */ 819 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000028 820 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 821 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 822 823 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION 824 825 Parsed from RX_MSDU_END TLV . In the case MSDU spans 826 over multiple buffers, this field will be valid in the Last 827 buffer used by the MSDU 828 829 830 831 The ID of the REO exit ring where the MSDU frame shall 832 push after (MPDU level) reordering has finished. 833 834 835 836 <enum 0 reo_destination_tcl> Reo will push the frame 837 into the REO2TCL ring 838 839 <enum 1 reo_destination_sw1> Reo will push the frame 840 into the REO2SW1 ring 841 842 <enum 2 reo_destination_sw2> Reo will push the frame 843 into the REO2SW2 ring 844 845 <enum 3 reo_destination_sw3> Reo will push the frame 846 into the REO2SW3 ring 847 848 <enum 4 reo_destination_sw4> Reo will push the frame 849 into the REO2SW4 ring 850 851 <enum 5 reo_destination_release> Reo will push the frame 852 into the REO_release ring 853 854 <enum 6 reo_destination_fw> Reo will push the frame into 855 the REO2FW ring 856 857 <enum 7 reo_destination_sw5> Reo will push the frame 858 into the REO2SW5 ring (REO remaps this in chips without 859 REO2SW5 ring, e.g. Pine) 860 861 <enum 8 reo_destination_sw6> Reo will push the frame 862 into the REO2SW6 ring (REO remaps this in chips without 863 REO2SW6 ring, e.g. Pine) 864 865 <enum 9 reo_destination_9> REO remaps this <enum 10 866 reo_destination_10> REO remaps this 867 868 <enum 11 reo_destination_11> REO remaps this 869 870 <enum 12 reo_destination_12> REO remaps this <enum 13 871 reo_destination_13> REO remaps this 872 873 <enum 14 reo_destination_14> REO remaps this 874 875 <enum 15 reo_destination_15> REO remaps this 876 877 <enum 16 reo_destination_16> REO remaps this 878 879 <enum 17 reo_destination_17> REO remaps this 880 881 <enum 18 reo_destination_18> REO remaps this 882 883 <enum 19 reo_destination_19> REO remaps this 884 885 <enum 20 reo_destination_20> REO remaps this 886 887 <enum 21 reo_destination_21> REO remaps this 888 889 <enum 22 reo_destination_22> REO remaps this 890 891 <enum 23 reo_destination_23> REO remaps this 892 893 <enum 24 reo_destination_24> REO remaps this 894 895 <enum 25 reo_destination_25> REO remaps this 896 897 <enum 26 reo_destination_26> REO remaps this 898 899 <enum 27 reo_destination_27> REO remaps this 900 901 <enum 28 reo_destination_28> REO remaps this 902 903 <enum 29 reo_destination_29> REO remaps this 904 905 <enum 30 reo_destination_30> REO remaps this 906 907 <enum 31 reo_destination_31> REO remaps this 908 909 910 911 <legal all> 912 */ 913 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000028 914 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 915 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 916 917 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP 918 919 Parsed from RX_MSDU_END TLV . In the case MSDU spans 920 over multiple buffers, this field will be valid in the Last 921 buffer used by the MSDU 922 923 924 925 When set, REO shall drop this MSDU and not forward it to 926 any other ring... 927 928 <legal all> 929 */ 930 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000028 931 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 932 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 933 934 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID 935 936 Parsed from RX_MSDU_END TLV . In the case MSDU spans 937 over multiple buffers, this field will be valid in the Last 938 buffer used by the MSDU 939 940 941 942 Indicates that OLE found a valid SA entry for this MSDU 943 944 <legal all> 945 */ 946 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000028 947 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 948 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 949 950 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 951 952 Parsed from RX_MSDU_END TLV . In the case MSDU spans 953 over multiple buffers, this field will be valid in the Last 954 buffer used by the MSDU 955 956 957 958 Indicates an unsuccessful MAC source address search due 959 to the expiring of the search timer for this MSDU 960 961 <legal all> 962 */ 963 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000028 964 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 965 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 966 967 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID 968 969 Parsed from RX_MSDU_END TLV . In the case MSDU spans 970 over multiple buffers, this field will be valid in the Last 971 buffer used by the MSDU 972 973 974 975 Indicates that OLE found a valid DA entry for this MSDU 976 977 <legal all> 978 */ 979 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000028 980 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 981 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 982 983 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC 984 985 Field Only valid if da_is_valid is set 986 987 988 989 Indicates the DA address was a Multicast of Broadcast 990 address for this MSDU 991 992 <legal all> 993 */ 994 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000028 995 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 996 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 997 998 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 999 1000 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1001 over multiple buffers, this field will be valid in the Last 1002 buffer used by the MSDU 1003 1004 1005 1006 Indicates an unsuccessful MAC destination address search 1007 due to the expiring of the search timer for this MSDU 1008 1009 <legal all> 1010 */ 1011 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000028 1012 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 1013 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 1014 1015 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB 1016 1017 Passed on from 'RX_MSDU_END' TLV (only the MSB is 1018 reported as the LSB is always zero) 1019 1020 Number of bytes padded to make sure that the L3 header 1021 will always start of a Dword boundary 1022 1023 <legal all> 1024 */ 1025 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000028 1026 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 1027 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 1028 1029 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL 1030 1031 Passed on from 'RX_ATTENTION' TLV 1032 1033 Indicates that the computed checksum did not match the 1034 checksum in the TCP/UDP header. 1035 1036 <legal all> 1037 */ 1038 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028 1039 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 1040 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 1041 1042 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL 1043 1044 Passed on from 'RX_ATTENTION' TLV 1045 1046 Indicates that the computed checksum did not match the 1047 checksum in the IP header. 1048 1049 <legal all> 1050 */ 1051 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000028 1052 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 1053 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 1054 1055 /* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU 1056 1057 Passed on from 'RX_MPDU_INFO' structure in 1058 'RX_MPDU_START' TLV 1059 1060 Set to 1 by RXOLE when it has not performed any 802.11 1061 to Ethernet/Natvie WiFi header conversion on this MPDU. 1062 1063 <legal all> 1064 */ 1065 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000028 1066 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 1067 #define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 1068 1069 /* Description RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0 1070 1071 Passed on from 'RX_MSDU_END' TLV (one MSB is omitted) 1072 1073 Based on a register configuration in RXDMA, this field 1074 will contain: 1075 1076 The offset in the address search table which matches the 1077 MAC source address 1078 1079 OR 1080 1081 1082 1083 'sw_peer_id' from the address search entry corresponding 1084 to the source address of the MSDU 1085 1086 <legal all> 1087 */ 1088 #define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000002c 1089 #define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 1090 #define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff 1091 1092 /* Description RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0 1093 1094 Passed on from 'RX_MPDU_INFO' structure in 1095 'RX_MPDU_START' TLV (one MSB is omitted) 1096 1097 1098 1099 Based on a register configuration in RXDMA, this field 1100 will contain: 1101 1102 The index of the address search entry corresponding to 1103 this MPDU (a value of 0xFFFF indicates an invalid AST index, 1104 meaning that no AST entry was found or no AST search was 1105 performed) 1106 1107 1108 1109 OR: 1110 1111 1112 1113 'sw_peer_id' from the address search entry corresponding 1114 to this MPDU (in case of ndp or phy_err or 1115 AST_based_lookup_valid == 0, this field will be set to 0) 1116 1117 <legal all> 1118 */ 1119 #define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000002c 1120 #define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 1121 #define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 1122 1123 /* Description RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS 1124 1125 Passed on from 'RX_MPDU_INFO' structure in 1126 'RX_MPDU_START' TLV 1127 1128 Set if the 'from DS' bit is set in the frame control. 1129 1130 <legal all> 1131 */ 1132 #define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000002c 1133 #define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 1134 #define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 1135 1136 /* Description RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS 1137 1138 Passed on from 'RX_MPDU_INFO' structure in 1139 'RX_MPDU_START' TLV 1140 1141 Set if the 'to DS' bit is set in the frame control. 1142 1143 <legal all> 1144 */ 1145 #define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000002c 1146 #define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 1147 #define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 1148 1149 /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_1 */ 1150 1151 1152 /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ 1153 1154 1155 /* Description RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 1156 1157 Address (lower 32 bits) of the MSDU buffer OR 1158 MSDU_EXTENSION descriptor OR Link Descriptor 1159 1160 1161 1162 In case of 'NULL' pointer, this field is set to 0 1163 1164 <legal all> 1165 */ 1166 #define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000030 1167 #define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 1168 #define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 1169 1170 /* Description RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 1171 1172 Address (upper 8 bits) of the MSDU buffer OR 1173 MSDU_EXTENSION descriptor OR Link Descriptor 1174 1175 1176 1177 In case of 'NULL' pointer, this field is set to 0 1178 1179 <legal all> 1180 */ 1181 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000034 1182 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 1183 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 1184 1185 /* Description RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER 1186 1187 Consumer: WBM 1188 1189 Producer: SW/FW 1190 1191 1192 1193 In case of 'NULL' pointer, this field is set to 0 1194 1195 1196 1197 Indicates to which buffer manager the buffer OR 1198 MSDU_EXTENSION descriptor OR link descriptor that is being 1199 pointed to shall be returned after the frame has been 1200 processed. It is used by WBM for routing purposes. 1201 1202 1203 1204 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1205 to the WMB buffer idle list 1206 1207 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1208 returned to the WMB idle link descriptor idle list 1209 1210 <enum 2 FW_BM> This buffer shall be returned to the FW 1211 1212 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1213 ring 0 1214 1215 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1216 ring 1 1217 1218 <enum 5 SW2_BM> This buffer shall be returned to the SW, 1219 ring 2 1220 1221 <enum 6 SW3_BM> This buffer shall be returned to the SW, 1222 ring 3 1223 1224 <enum 7 SW4_BM> This buffer shall be returned to the SW, 1225 ring 4 1226 1227 1228 1229 <legal all> 1230 */ 1231 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 1232 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 1233 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 1234 1235 /* Description RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE 1236 1237 Cookie field exclusively used by SW. 1238 1239 1240 1241 In case of 'NULL' pointer, this field is set to 0 1242 1243 1244 1245 HW ignores the contents, accept that it passes the 1246 programmed value on to other descriptors together with the 1247 physical address 1248 1249 1250 1251 Field can be used by SW to for example associate the 1252 buffers physical address with the virtual address 1253 1254 The bit definitions as used by SW are within SW HLD 1255 specification 1256 1257 1258 1259 NOTE1: 1260 1261 The three most significant bits can have a special 1262 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1263 STRUCT, and field transmit_bw_restriction is set 1264 1265 1266 1267 In case of NON punctured transmission: 1268 1269 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1270 1271 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1272 1273 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1274 1275 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1276 1277 1278 1279 In case of punctured transmission: 1280 1281 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1282 1283 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1284 1285 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1286 1287 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1288 1289 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1290 1291 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1292 1293 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1294 1295 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1296 1297 1298 1299 Note: a punctured transmission is indicated by the 1300 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1301 TLV 1302 1303 1304 1305 NOTE 2:The five most significant bits can have a special 1306 meaning in case this struct is embedded in an 1307 RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is 1308 configured for passing on the additional info 1309 from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV 1310 (FR56821). This is not supported in HastingsPrime, Pine or 1311 Moselle. 1312 1313 1314 1315 Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS 1316 control field 1317 1318 1319 1320 Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 1321 indicates MPDUs with a QoS control field. 1322 1323 1324 1325 1326 1327 <legal all> 1328 */ 1329 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000034 1330 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 1331 #define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 1332 1333 /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ 1334 1335 1336 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG 1337 1338 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1339 over multiple buffers, this field will be valid in the Last 1340 buffer used by the MSDU 1341 1342 1343 1344 <enum 0 Not_first_msdu> This is not the first MSDU in 1345 the MPDU. 1346 1347 <enum 1 first_msdu> This MSDU is the first one in the 1348 MPDU. 1349 1350 1351 1352 <legal all> 1353 */ 1354 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 1355 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 1356 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 1357 1358 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG 1359 1360 Consumer: WBM/REO/SW/FW 1361 1362 Producer: RXDMA 1363 1364 1365 1366 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1367 over multiple buffers, this field will be valid in the Last 1368 buffer used by the MSDU 1369 1370 1371 1372 <enum 0 Not_last_msdu> There are more MSDUs linked to 1373 this MSDU that belongs to this MPDU 1374 1375 <enum 1 Last_msdu> this MSDU is the last one in the 1376 MPDU. This setting is only allowed in combination with 1377 'Msdu_continuation' set to 0. This implies that when an msdu 1378 is spread out over multiple buffers and thus 1379 msdu_continuation is set, only for the very last buffer of 1380 the msdu, can the 'last_msdu_in_mpdu_flag' be set. 1381 1382 1383 1384 When both first_msdu_in_mpdu_flag and 1385 last_msdu_in_mpdu_flag are set, the MPDU that this MSDU 1386 belongs to only contains a single MSDU. 1387 1388 1389 1390 1391 1392 <legal all> 1393 */ 1394 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 1395 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 1396 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 1397 1398 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION 1399 1400 When set, this MSDU buffer was not able to hold the 1401 entire MSDU. The next buffer will therefor contain 1402 additional information related to this MSDU. 1403 1404 1405 1406 <legal all> 1407 */ 1408 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000038 1409 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 1410 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 1411 1412 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH 1413 1414 Parsed from RX_MSDU_START TLV . In the case MSDU spans 1415 over multiple buffers, this field will be valid in the First 1416 buffer used by MSDU. 1417 1418 1419 1420 Full MSDU length in bytes after decapsulation. 1421 1422 1423 1424 This field is still valid for MPDU frames without 1425 A-MSDU. It still represents MSDU length after decapsulation 1426 1427 1428 1429 Or in case of RAW MPDUs, it indicates the length of the 1430 entire MPDU (without FCS field) 1431 1432 <legal all> 1433 */ 1434 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000038 1435 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 1436 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 1437 1438 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION 1439 1440 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1441 over multiple buffers, this field will be valid in the Last 1442 buffer used by the MSDU 1443 1444 1445 1446 The ID of the REO exit ring where the MSDU frame shall 1447 push after (MPDU level) reordering has finished. 1448 1449 1450 1451 <enum 0 reo_destination_tcl> Reo will push the frame 1452 into the REO2TCL ring 1453 1454 <enum 1 reo_destination_sw1> Reo will push the frame 1455 into the REO2SW1 ring 1456 1457 <enum 2 reo_destination_sw2> Reo will push the frame 1458 into the REO2SW2 ring 1459 1460 <enum 3 reo_destination_sw3> Reo will push the frame 1461 into the REO2SW3 ring 1462 1463 <enum 4 reo_destination_sw4> Reo will push the frame 1464 into the REO2SW4 ring 1465 1466 <enum 5 reo_destination_release> Reo will push the frame 1467 into the REO_release ring 1468 1469 <enum 6 reo_destination_fw> Reo will push the frame into 1470 the REO2FW ring 1471 1472 <enum 7 reo_destination_sw5> Reo will push the frame 1473 into the REO2SW5 ring (REO remaps this in chips without 1474 REO2SW5 ring, e.g. Pine) 1475 1476 <enum 8 reo_destination_sw6> Reo will push the frame 1477 into the REO2SW6 ring (REO remaps this in chips without 1478 REO2SW6 ring, e.g. Pine) 1479 1480 <enum 9 reo_destination_9> REO remaps this <enum 10 1481 reo_destination_10> REO remaps this 1482 1483 <enum 11 reo_destination_11> REO remaps this 1484 1485 <enum 12 reo_destination_12> REO remaps this <enum 13 1486 reo_destination_13> REO remaps this 1487 1488 <enum 14 reo_destination_14> REO remaps this 1489 1490 <enum 15 reo_destination_15> REO remaps this 1491 1492 <enum 16 reo_destination_16> REO remaps this 1493 1494 <enum 17 reo_destination_17> REO remaps this 1495 1496 <enum 18 reo_destination_18> REO remaps this 1497 1498 <enum 19 reo_destination_19> REO remaps this 1499 1500 <enum 20 reo_destination_20> REO remaps this 1501 1502 <enum 21 reo_destination_21> REO remaps this 1503 1504 <enum 22 reo_destination_22> REO remaps this 1505 1506 <enum 23 reo_destination_23> REO remaps this 1507 1508 <enum 24 reo_destination_24> REO remaps this 1509 1510 <enum 25 reo_destination_25> REO remaps this 1511 1512 <enum 26 reo_destination_26> REO remaps this 1513 1514 <enum 27 reo_destination_27> REO remaps this 1515 1516 <enum 28 reo_destination_28> REO remaps this 1517 1518 <enum 29 reo_destination_29> REO remaps this 1519 1520 <enum 30 reo_destination_30> REO remaps this 1521 1522 <enum 31 reo_destination_31> REO remaps this 1523 1524 1525 1526 <legal all> 1527 */ 1528 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000038 1529 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 1530 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 1531 1532 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP 1533 1534 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1535 over multiple buffers, this field will be valid in the Last 1536 buffer used by the MSDU 1537 1538 1539 1540 When set, REO shall drop this MSDU and not forward it to 1541 any other ring... 1542 1543 <legal all> 1544 */ 1545 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000038 1546 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 1547 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 1548 1549 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID 1550 1551 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1552 over multiple buffers, this field will be valid in the Last 1553 buffer used by the MSDU 1554 1555 1556 1557 Indicates that OLE found a valid SA entry for this MSDU 1558 1559 <legal all> 1560 */ 1561 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000038 1562 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 1563 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 1564 1565 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 1566 1567 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1568 over multiple buffers, this field will be valid in the Last 1569 buffer used by the MSDU 1570 1571 1572 1573 Indicates an unsuccessful MAC source address search due 1574 to the expiring of the search timer for this MSDU 1575 1576 <legal all> 1577 */ 1578 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000038 1579 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 1580 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 1581 1582 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID 1583 1584 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1585 over multiple buffers, this field will be valid in the Last 1586 buffer used by the MSDU 1587 1588 1589 1590 Indicates that OLE found a valid DA entry for this MSDU 1591 1592 <legal all> 1593 */ 1594 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000038 1595 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 1596 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 1597 1598 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC 1599 1600 Field Only valid if da_is_valid is set 1601 1602 1603 1604 Indicates the DA address was a Multicast of Broadcast 1605 address for this MSDU 1606 1607 <legal all> 1608 */ 1609 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000038 1610 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 1611 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 1612 1613 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 1614 1615 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1616 over multiple buffers, this field will be valid in the Last 1617 buffer used by the MSDU 1618 1619 1620 1621 Indicates an unsuccessful MAC destination address search 1622 due to the expiring of the search timer for this MSDU 1623 1624 <legal all> 1625 */ 1626 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000038 1627 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 1628 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 1629 1630 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB 1631 1632 Passed on from 'RX_MSDU_END' TLV (only the MSB is 1633 reported as the LSB is always zero) 1634 1635 Number of bytes padded to make sure that the L3 header 1636 will always start of a Dword boundary 1637 1638 <legal all> 1639 */ 1640 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000038 1641 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 1642 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 1643 1644 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL 1645 1646 Passed on from 'RX_ATTENTION' TLV 1647 1648 Indicates that the computed checksum did not match the 1649 checksum in the TCP/UDP header. 1650 1651 <legal all> 1652 */ 1653 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000038 1654 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 1655 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 1656 1657 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL 1658 1659 Passed on from 'RX_ATTENTION' TLV 1660 1661 Indicates that the computed checksum did not match the 1662 checksum in the IP header. 1663 1664 <legal all> 1665 */ 1666 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000038 1667 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 1668 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 1669 1670 /* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU 1671 1672 Passed on from 'RX_MPDU_INFO' structure in 1673 'RX_MPDU_START' TLV 1674 1675 Set to 1 by RXOLE when it has not performed any 802.11 1676 to Ethernet/Natvie WiFi header conversion on this MPDU. 1677 1678 <legal all> 1679 */ 1680 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000038 1681 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 1682 #define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 1683 1684 /* Description RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0 1685 1686 Passed on from 'RX_MSDU_END' TLV (one MSB is omitted) 1687 1688 Based on a register configuration in RXDMA, this field 1689 will contain: 1690 1691 The offset in the address search table which matches the 1692 MAC source address 1693 1694 OR 1695 1696 1697 1698 'sw_peer_id' from the address search entry corresponding 1699 to the source address of the MSDU 1700 1701 <legal all> 1702 */ 1703 #define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000003c 1704 #define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 1705 #define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff 1706 1707 /* Description RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0 1708 1709 Passed on from 'RX_MPDU_INFO' structure in 1710 'RX_MPDU_START' TLV (one MSB is omitted) 1711 1712 1713 1714 Based on a register configuration in RXDMA, this field 1715 will contain: 1716 1717 The index of the address search entry corresponding to 1718 this MPDU (a value of 0xFFFF indicates an invalid AST index, 1719 meaning that no AST entry was found or no AST search was 1720 performed) 1721 1722 1723 1724 OR: 1725 1726 1727 1728 'sw_peer_id' from the address search entry corresponding 1729 to this MPDU (in case of ndp or phy_err or 1730 AST_based_lookup_valid == 0, this field will be set to 0) 1731 1732 <legal all> 1733 */ 1734 #define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000003c 1735 #define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 1736 #define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 1737 1738 /* Description RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS 1739 1740 Passed on from 'RX_MPDU_INFO' structure in 1741 'RX_MPDU_START' TLV 1742 1743 Set if the 'from DS' bit is set in the frame control. 1744 1745 <legal all> 1746 */ 1747 #define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000003c 1748 #define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 1749 #define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 1750 1751 /* Description RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS 1752 1753 Passed on from 'RX_MPDU_INFO' structure in 1754 'RX_MPDU_START' TLV 1755 1756 Set if the 'to DS' bit is set in the frame control. 1757 1758 <legal all> 1759 */ 1760 #define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000003c 1761 #define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 1762 #define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 1763 1764 /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_2 */ 1765 1766 1767 /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ 1768 1769 1770 /* Description RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 1771 1772 Address (lower 32 bits) of the MSDU buffer OR 1773 MSDU_EXTENSION descriptor OR Link Descriptor 1774 1775 1776 1777 In case of 'NULL' pointer, this field is set to 0 1778 1779 <legal all> 1780 */ 1781 #define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000040 1782 #define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 1783 #define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 1784 1785 /* Description RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 1786 1787 Address (upper 8 bits) of the MSDU buffer OR 1788 MSDU_EXTENSION descriptor OR Link Descriptor 1789 1790 1791 1792 In case of 'NULL' pointer, this field is set to 0 1793 1794 <legal all> 1795 */ 1796 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000044 1797 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 1798 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 1799 1800 /* Description RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER 1801 1802 Consumer: WBM 1803 1804 Producer: SW/FW 1805 1806 1807 1808 In case of 'NULL' pointer, this field is set to 0 1809 1810 1811 1812 Indicates to which buffer manager the buffer OR 1813 MSDU_EXTENSION descriptor OR link descriptor that is being 1814 pointed to shall be returned after the frame has been 1815 processed. It is used by WBM for routing purposes. 1816 1817 1818 1819 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1820 to the WMB buffer idle list 1821 1822 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1823 returned to the WMB idle link descriptor idle list 1824 1825 <enum 2 FW_BM> This buffer shall be returned to the FW 1826 1827 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1828 ring 0 1829 1830 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1831 ring 1 1832 1833 <enum 5 SW2_BM> This buffer shall be returned to the SW, 1834 ring 2 1835 1836 <enum 6 SW3_BM> This buffer shall be returned to the SW, 1837 ring 3 1838 1839 <enum 7 SW4_BM> This buffer shall be returned to the SW, 1840 ring 4 1841 1842 1843 1844 <legal all> 1845 */ 1846 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 1847 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 1848 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 1849 1850 /* Description RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE 1851 1852 Cookie field exclusively used by SW. 1853 1854 1855 1856 In case of 'NULL' pointer, this field is set to 0 1857 1858 1859 1860 HW ignores the contents, accept that it passes the 1861 programmed value on to other descriptors together with the 1862 physical address 1863 1864 1865 1866 Field can be used by SW to for example associate the 1867 buffers physical address with the virtual address 1868 1869 The bit definitions as used by SW are within SW HLD 1870 specification 1871 1872 1873 1874 NOTE1: 1875 1876 The three most significant bits can have a special 1877 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1878 STRUCT, and field transmit_bw_restriction is set 1879 1880 1881 1882 In case of NON punctured transmission: 1883 1884 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1885 1886 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1887 1888 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1889 1890 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1891 1892 1893 1894 In case of punctured transmission: 1895 1896 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1897 1898 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1899 1900 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1901 1902 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1903 1904 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1905 1906 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1907 1908 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1909 1910 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1911 1912 1913 1914 Note: a punctured transmission is indicated by the 1915 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1916 TLV 1917 1918 1919 1920 NOTE 2:The five most significant bits can have a special 1921 meaning in case this struct is embedded in an 1922 RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is 1923 configured for passing on the additional info 1924 from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV 1925 (FR56821). This is not supported in HastingsPrime, Pine or 1926 Moselle. 1927 1928 1929 1930 Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS 1931 control field 1932 1933 1934 1935 Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 1936 indicates MPDUs with a QoS control field. 1937 1938 1939 1940 1941 1942 <legal all> 1943 */ 1944 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000044 1945 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 1946 #define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 1947 1948 /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ 1949 1950 1951 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG 1952 1953 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1954 over multiple buffers, this field will be valid in the Last 1955 buffer used by the MSDU 1956 1957 1958 1959 <enum 0 Not_first_msdu> This is not the first MSDU in 1960 the MPDU. 1961 1962 <enum 1 first_msdu> This MSDU is the first one in the 1963 MPDU. 1964 1965 1966 1967 <legal all> 1968 */ 1969 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 1970 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 1971 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 1972 1973 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG 1974 1975 Consumer: WBM/REO/SW/FW 1976 1977 Producer: RXDMA 1978 1979 1980 1981 Parsed from RX_MSDU_END TLV . In the case MSDU spans 1982 over multiple buffers, this field will be valid in the Last 1983 buffer used by the MSDU 1984 1985 1986 1987 <enum 0 Not_last_msdu> There are more MSDUs linked to 1988 this MSDU that belongs to this MPDU 1989 1990 <enum 1 Last_msdu> this MSDU is the last one in the 1991 MPDU. This setting is only allowed in combination with 1992 'Msdu_continuation' set to 0. This implies that when an msdu 1993 is spread out over multiple buffers and thus 1994 msdu_continuation is set, only for the very last buffer of 1995 the msdu, can the 'last_msdu_in_mpdu_flag' be set. 1996 1997 1998 1999 When both first_msdu_in_mpdu_flag and 2000 last_msdu_in_mpdu_flag are set, the MPDU that this MSDU 2001 belongs to only contains a single MSDU. 2002 2003 2004 2005 2006 2007 <legal all> 2008 */ 2009 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 2010 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 2011 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 2012 2013 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION 2014 2015 When set, this MSDU buffer was not able to hold the 2016 entire MSDU. The next buffer will therefor contain 2017 additional information related to this MSDU. 2018 2019 2020 2021 <legal all> 2022 */ 2023 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000048 2024 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 2025 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 2026 2027 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH 2028 2029 Parsed from RX_MSDU_START TLV . In the case MSDU spans 2030 over multiple buffers, this field will be valid in the First 2031 buffer used by MSDU. 2032 2033 2034 2035 Full MSDU length in bytes after decapsulation. 2036 2037 2038 2039 This field is still valid for MPDU frames without 2040 A-MSDU. It still represents MSDU length after decapsulation 2041 2042 2043 2044 Or in case of RAW MPDUs, it indicates the length of the 2045 entire MPDU (without FCS field) 2046 2047 <legal all> 2048 */ 2049 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000048 2050 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 2051 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 2052 2053 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION 2054 2055 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2056 over multiple buffers, this field will be valid in the Last 2057 buffer used by the MSDU 2058 2059 2060 2061 The ID of the REO exit ring where the MSDU frame shall 2062 push after (MPDU level) reordering has finished. 2063 2064 2065 2066 <enum 0 reo_destination_tcl> Reo will push the frame 2067 into the REO2TCL ring 2068 2069 <enum 1 reo_destination_sw1> Reo will push the frame 2070 into the REO2SW1 ring 2071 2072 <enum 2 reo_destination_sw2> Reo will push the frame 2073 into the REO2SW2 ring 2074 2075 <enum 3 reo_destination_sw3> Reo will push the frame 2076 into the REO2SW3 ring 2077 2078 <enum 4 reo_destination_sw4> Reo will push the frame 2079 into the REO2SW4 ring 2080 2081 <enum 5 reo_destination_release> Reo will push the frame 2082 into the REO_release ring 2083 2084 <enum 6 reo_destination_fw> Reo will push the frame into 2085 the REO2FW ring 2086 2087 <enum 7 reo_destination_sw5> Reo will push the frame 2088 into the REO2SW5 ring (REO remaps this in chips without 2089 REO2SW5 ring, e.g. Pine) 2090 2091 <enum 8 reo_destination_sw6> Reo will push the frame 2092 into the REO2SW6 ring (REO remaps this in chips without 2093 REO2SW6 ring, e.g. Pine) 2094 2095 <enum 9 reo_destination_9> REO remaps this <enum 10 2096 reo_destination_10> REO remaps this 2097 2098 <enum 11 reo_destination_11> REO remaps this 2099 2100 <enum 12 reo_destination_12> REO remaps this <enum 13 2101 reo_destination_13> REO remaps this 2102 2103 <enum 14 reo_destination_14> REO remaps this 2104 2105 <enum 15 reo_destination_15> REO remaps this 2106 2107 <enum 16 reo_destination_16> REO remaps this 2108 2109 <enum 17 reo_destination_17> REO remaps this 2110 2111 <enum 18 reo_destination_18> REO remaps this 2112 2113 <enum 19 reo_destination_19> REO remaps this 2114 2115 <enum 20 reo_destination_20> REO remaps this 2116 2117 <enum 21 reo_destination_21> REO remaps this 2118 2119 <enum 22 reo_destination_22> REO remaps this 2120 2121 <enum 23 reo_destination_23> REO remaps this 2122 2123 <enum 24 reo_destination_24> REO remaps this 2124 2125 <enum 25 reo_destination_25> REO remaps this 2126 2127 <enum 26 reo_destination_26> REO remaps this 2128 2129 <enum 27 reo_destination_27> REO remaps this 2130 2131 <enum 28 reo_destination_28> REO remaps this 2132 2133 <enum 29 reo_destination_29> REO remaps this 2134 2135 <enum 30 reo_destination_30> REO remaps this 2136 2137 <enum 31 reo_destination_31> REO remaps this 2138 2139 2140 2141 <legal all> 2142 */ 2143 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000048 2144 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 2145 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 2146 2147 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP 2148 2149 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2150 over multiple buffers, this field will be valid in the Last 2151 buffer used by the MSDU 2152 2153 2154 2155 When set, REO shall drop this MSDU and not forward it to 2156 any other ring... 2157 2158 <legal all> 2159 */ 2160 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000048 2161 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 2162 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 2163 2164 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID 2165 2166 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2167 over multiple buffers, this field will be valid in the Last 2168 buffer used by the MSDU 2169 2170 2171 2172 Indicates that OLE found a valid SA entry for this MSDU 2173 2174 <legal all> 2175 */ 2176 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000048 2177 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 2178 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 2179 2180 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 2181 2182 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2183 over multiple buffers, this field will be valid in the Last 2184 buffer used by the MSDU 2185 2186 2187 2188 Indicates an unsuccessful MAC source address search due 2189 to the expiring of the search timer for this MSDU 2190 2191 <legal all> 2192 */ 2193 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000048 2194 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 2195 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 2196 2197 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID 2198 2199 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2200 over multiple buffers, this field will be valid in the Last 2201 buffer used by the MSDU 2202 2203 2204 2205 Indicates that OLE found a valid DA entry for this MSDU 2206 2207 <legal all> 2208 */ 2209 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000048 2210 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 2211 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 2212 2213 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC 2214 2215 Field Only valid if da_is_valid is set 2216 2217 2218 2219 Indicates the DA address was a Multicast of Broadcast 2220 address for this MSDU 2221 2222 <legal all> 2223 */ 2224 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000048 2225 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 2226 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 2227 2228 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 2229 2230 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2231 over multiple buffers, this field will be valid in the Last 2232 buffer used by the MSDU 2233 2234 2235 2236 Indicates an unsuccessful MAC destination address search 2237 due to the expiring of the search timer for this MSDU 2238 2239 <legal all> 2240 */ 2241 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000048 2242 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 2243 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 2244 2245 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB 2246 2247 Passed on from 'RX_MSDU_END' TLV (only the MSB is 2248 reported as the LSB is always zero) 2249 2250 Number of bytes padded to make sure that the L3 header 2251 will always start of a Dword boundary 2252 2253 <legal all> 2254 */ 2255 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000048 2256 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 2257 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 2258 2259 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL 2260 2261 Passed on from 'RX_ATTENTION' TLV 2262 2263 Indicates that the computed checksum did not match the 2264 checksum in the TCP/UDP header. 2265 2266 <legal all> 2267 */ 2268 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000048 2269 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 2270 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 2271 2272 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL 2273 2274 Passed on from 'RX_ATTENTION' TLV 2275 2276 Indicates that the computed checksum did not match the 2277 checksum in the IP header. 2278 2279 <legal all> 2280 */ 2281 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000048 2282 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 2283 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 2284 2285 /* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU 2286 2287 Passed on from 'RX_MPDU_INFO' structure in 2288 'RX_MPDU_START' TLV 2289 2290 Set to 1 by RXOLE when it has not performed any 802.11 2291 to Ethernet/Natvie WiFi header conversion on this MPDU. 2292 2293 <legal all> 2294 */ 2295 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000048 2296 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 2297 #define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 2298 2299 /* Description RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0 2300 2301 Passed on from 'RX_MSDU_END' TLV (one MSB is omitted) 2302 2303 Based on a register configuration in RXDMA, this field 2304 will contain: 2305 2306 The offset in the address search table which matches the 2307 MAC source address 2308 2309 OR 2310 2311 2312 2313 'sw_peer_id' from the address search entry corresponding 2314 to the source address of the MSDU 2315 2316 <legal all> 2317 */ 2318 #define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000004c 2319 #define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 2320 #define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff 2321 2322 /* Description RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0 2323 2324 Passed on from 'RX_MPDU_INFO' structure in 2325 'RX_MPDU_START' TLV (one MSB is omitted) 2326 2327 2328 2329 Based on a register configuration in RXDMA, this field 2330 will contain: 2331 2332 The index of the address search entry corresponding to 2333 this MPDU (a value of 0xFFFF indicates an invalid AST index, 2334 meaning that no AST entry was found or no AST search was 2335 performed) 2336 2337 2338 2339 OR: 2340 2341 2342 2343 'sw_peer_id' from the address search entry corresponding 2344 to this MPDU (in case of ndp or phy_err or 2345 AST_based_lookup_valid == 0, this field will be set to 0) 2346 2347 <legal all> 2348 */ 2349 #define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000004c 2350 #define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 2351 #define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 2352 2353 /* Description RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS 2354 2355 Passed on from 'RX_MPDU_INFO' structure in 2356 'RX_MPDU_START' TLV 2357 2358 Set if the 'from DS' bit is set in the frame control. 2359 2360 <legal all> 2361 */ 2362 #define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000004c 2363 #define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 2364 #define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 2365 2366 /* Description RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS 2367 2368 Passed on from 'RX_MPDU_INFO' structure in 2369 'RX_MPDU_START' TLV 2370 2371 Set if the 'to DS' bit is set in the frame control. 2372 2373 <legal all> 2374 */ 2375 #define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000004c 2376 #define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 2377 #define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 2378 2379 /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_3 */ 2380 2381 2382 /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ 2383 2384 2385 /* Description RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 2386 2387 Address (lower 32 bits) of the MSDU buffer OR 2388 MSDU_EXTENSION descriptor OR Link Descriptor 2389 2390 2391 2392 In case of 'NULL' pointer, this field is set to 0 2393 2394 <legal all> 2395 */ 2396 #define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000050 2397 #define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 2398 #define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 2399 2400 /* Description RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 2401 2402 Address (upper 8 bits) of the MSDU buffer OR 2403 MSDU_EXTENSION descriptor OR Link Descriptor 2404 2405 2406 2407 In case of 'NULL' pointer, this field is set to 0 2408 2409 <legal all> 2410 */ 2411 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000054 2412 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 2413 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 2414 2415 /* Description RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER 2416 2417 Consumer: WBM 2418 2419 Producer: SW/FW 2420 2421 2422 2423 In case of 'NULL' pointer, this field is set to 0 2424 2425 2426 2427 Indicates to which buffer manager the buffer OR 2428 MSDU_EXTENSION descriptor OR link descriptor that is being 2429 pointed to shall be returned after the frame has been 2430 processed. It is used by WBM for routing purposes. 2431 2432 2433 2434 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2435 to the WMB buffer idle list 2436 2437 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 2438 returned to the WMB idle link descriptor idle list 2439 2440 <enum 2 FW_BM> This buffer shall be returned to the FW 2441 2442 <enum 3 SW0_BM> This buffer shall be returned to the SW, 2443 ring 0 2444 2445 <enum 4 SW1_BM> This buffer shall be returned to the SW, 2446 ring 1 2447 2448 <enum 5 SW2_BM> This buffer shall be returned to the SW, 2449 ring 2 2450 2451 <enum 6 SW3_BM> This buffer shall be returned to the SW, 2452 ring 3 2453 2454 <enum 7 SW4_BM> This buffer shall be returned to the SW, 2455 ring 4 2456 2457 2458 2459 <legal all> 2460 */ 2461 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 2462 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 2463 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 2464 2465 /* Description RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE 2466 2467 Cookie field exclusively used by SW. 2468 2469 2470 2471 In case of 'NULL' pointer, this field is set to 0 2472 2473 2474 2475 HW ignores the contents, accept that it passes the 2476 programmed value on to other descriptors together with the 2477 physical address 2478 2479 2480 2481 Field can be used by SW to for example associate the 2482 buffers physical address with the virtual address 2483 2484 The bit definitions as used by SW are within SW HLD 2485 specification 2486 2487 2488 2489 NOTE1: 2490 2491 The three most significant bits can have a special 2492 meaning in case this struct is embedded in a TX_MPDU_DETAILS 2493 STRUCT, and field transmit_bw_restriction is set 2494 2495 2496 2497 In case of NON punctured transmission: 2498 2499 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 2500 2501 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 2502 2503 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 2504 2505 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 2506 2507 2508 2509 In case of punctured transmission: 2510 2511 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 2512 2513 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 2514 2515 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 2516 2517 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 2518 2519 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 2520 2521 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 2522 2523 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 2524 2525 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 2526 2527 2528 2529 Note: a punctured transmission is indicated by the 2530 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 2531 TLV 2532 2533 2534 2535 NOTE 2:The five most significant bits can have a special 2536 meaning in case this struct is embedded in an 2537 RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is 2538 configured for passing on the additional info 2539 from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV 2540 (FR56821). This is not supported in HastingsPrime, Pine or 2541 Moselle. 2542 2543 2544 2545 Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS 2546 control field 2547 2548 2549 2550 Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 2551 indicates MPDUs with a QoS control field. 2552 2553 2554 2555 2556 2557 <legal all> 2558 */ 2559 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000054 2560 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 2561 #define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 2562 2563 /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ 2564 2565 2566 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG 2567 2568 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2569 over multiple buffers, this field will be valid in the Last 2570 buffer used by the MSDU 2571 2572 2573 2574 <enum 0 Not_first_msdu> This is not the first MSDU in 2575 the MPDU. 2576 2577 <enum 1 first_msdu> This MSDU is the first one in the 2578 MPDU. 2579 2580 2581 2582 <legal all> 2583 */ 2584 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 2585 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 2586 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 2587 2588 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG 2589 2590 Consumer: WBM/REO/SW/FW 2591 2592 Producer: RXDMA 2593 2594 2595 2596 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2597 over multiple buffers, this field will be valid in the Last 2598 buffer used by the MSDU 2599 2600 2601 2602 <enum 0 Not_last_msdu> There are more MSDUs linked to 2603 this MSDU that belongs to this MPDU 2604 2605 <enum 1 Last_msdu> this MSDU is the last one in the 2606 MPDU. This setting is only allowed in combination with 2607 'Msdu_continuation' set to 0. This implies that when an msdu 2608 is spread out over multiple buffers and thus 2609 msdu_continuation is set, only for the very last buffer of 2610 the msdu, can the 'last_msdu_in_mpdu_flag' be set. 2611 2612 2613 2614 When both first_msdu_in_mpdu_flag and 2615 last_msdu_in_mpdu_flag are set, the MPDU that this MSDU 2616 belongs to only contains a single MSDU. 2617 2618 2619 2620 2621 2622 <legal all> 2623 */ 2624 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 2625 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 2626 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 2627 2628 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION 2629 2630 When set, this MSDU buffer was not able to hold the 2631 entire MSDU. The next buffer will therefor contain 2632 additional information related to this MSDU. 2633 2634 2635 2636 <legal all> 2637 */ 2638 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000058 2639 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 2640 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 2641 2642 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH 2643 2644 Parsed from RX_MSDU_START TLV . In the case MSDU spans 2645 over multiple buffers, this field will be valid in the First 2646 buffer used by MSDU. 2647 2648 2649 2650 Full MSDU length in bytes after decapsulation. 2651 2652 2653 2654 This field is still valid for MPDU frames without 2655 A-MSDU. It still represents MSDU length after decapsulation 2656 2657 2658 2659 Or in case of RAW MPDUs, it indicates the length of the 2660 entire MPDU (without FCS field) 2661 2662 <legal all> 2663 */ 2664 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000058 2665 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 2666 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 2667 2668 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION 2669 2670 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2671 over multiple buffers, this field will be valid in the Last 2672 buffer used by the MSDU 2673 2674 2675 2676 The ID of the REO exit ring where the MSDU frame shall 2677 push after (MPDU level) reordering has finished. 2678 2679 2680 2681 <enum 0 reo_destination_tcl> Reo will push the frame 2682 into the REO2TCL ring 2683 2684 <enum 1 reo_destination_sw1> Reo will push the frame 2685 into the REO2SW1 ring 2686 2687 <enum 2 reo_destination_sw2> Reo will push the frame 2688 into the REO2SW2 ring 2689 2690 <enum 3 reo_destination_sw3> Reo will push the frame 2691 into the REO2SW3 ring 2692 2693 <enum 4 reo_destination_sw4> Reo will push the frame 2694 into the REO2SW4 ring 2695 2696 <enum 5 reo_destination_release> Reo will push the frame 2697 into the REO_release ring 2698 2699 <enum 6 reo_destination_fw> Reo will push the frame into 2700 the REO2FW ring 2701 2702 <enum 7 reo_destination_sw5> Reo will push the frame 2703 into the REO2SW5 ring (REO remaps this in chips without 2704 REO2SW5 ring, e.g. Pine) 2705 2706 <enum 8 reo_destination_sw6> Reo will push the frame 2707 into the REO2SW6 ring (REO remaps this in chips without 2708 REO2SW6 ring, e.g. Pine) 2709 2710 <enum 9 reo_destination_9> REO remaps this <enum 10 2711 reo_destination_10> REO remaps this 2712 2713 <enum 11 reo_destination_11> REO remaps this 2714 2715 <enum 12 reo_destination_12> REO remaps this <enum 13 2716 reo_destination_13> REO remaps this 2717 2718 <enum 14 reo_destination_14> REO remaps this 2719 2720 <enum 15 reo_destination_15> REO remaps this 2721 2722 <enum 16 reo_destination_16> REO remaps this 2723 2724 <enum 17 reo_destination_17> REO remaps this 2725 2726 <enum 18 reo_destination_18> REO remaps this 2727 2728 <enum 19 reo_destination_19> REO remaps this 2729 2730 <enum 20 reo_destination_20> REO remaps this 2731 2732 <enum 21 reo_destination_21> REO remaps this 2733 2734 <enum 22 reo_destination_22> REO remaps this 2735 2736 <enum 23 reo_destination_23> REO remaps this 2737 2738 <enum 24 reo_destination_24> REO remaps this 2739 2740 <enum 25 reo_destination_25> REO remaps this 2741 2742 <enum 26 reo_destination_26> REO remaps this 2743 2744 <enum 27 reo_destination_27> REO remaps this 2745 2746 <enum 28 reo_destination_28> REO remaps this 2747 2748 <enum 29 reo_destination_29> REO remaps this 2749 2750 <enum 30 reo_destination_30> REO remaps this 2751 2752 <enum 31 reo_destination_31> REO remaps this 2753 2754 2755 2756 <legal all> 2757 */ 2758 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000058 2759 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 2760 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 2761 2762 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP 2763 2764 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2765 over multiple buffers, this field will be valid in the Last 2766 buffer used by the MSDU 2767 2768 2769 2770 When set, REO shall drop this MSDU and not forward it to 2771 any other ring... 2772 2773 <legal all> 2774 */ 2775 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000058 2776 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 2777 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 2778 2779 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID 2780 2781 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2782 over multiple buffers, this field will be valid in the Last 2783 buffer used by the MSDU 2784 2785 2786 2787 Indicates that OLE found a valid SA entry for this MSDU 2788 2789 <legal all> 2790 */ 2791 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000058 2792 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 2793 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 2794 2795 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 2796 2797 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2798 over multiple buffers, this field will be valid in the Last 2799 buffer used by the MSDU 2800 2801 2802 2803 Indicates an unsuccessful MAC source address search due 2804 to the expiring of the search timer for this MSDU 2805 2806 <legal all> 2807 */ 2808 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000058 2809 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 2810 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 2811 2812 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID 2813 2814 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2815 over multiple buffers, this field will be valid in the Last 2816 buffer used by the MSDU 2817 2818 2819 2820 Indicates that OLE found a valid DA entry for this MSDU 2821 2822 <legal all> 2823 */ 2824 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000058 2825 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 2826 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 2827 2828 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC 2829 2830 Field Only valid if da_is_valid is set 2831 2832 2833 2834 Indicates the DA address was a Multicast of Broadcast 2835 address for this MSDU 2836 2837 <legal all> 2838 */ 2839 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000058 2840 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 2841 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 2842 2843 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 2844 2845 Parsed from RX_MSDU_END TLV . In the case MSDU spans 2846 over multiple buffers, this field will be valid in the Last 2847 buffer used by the MSDU 2848 2849 2850 2851 Indicates an unsuccessful MAC destination address search 2852 due to the expiring of the search timer for this MSDU 2853 2854 <legal all> 2855 */ 2856 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000058 2857 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 2858 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 2859 2860 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB 2861 2862 Passed on from 'RX_MSDU_END' TLV (only the MSB is 2863 reported as the LSB is always zero) 2864 2865 Number of bytes padded to make sure that the L3 header 2866 will always start of a Dword boundary 2867 2868 <legal all> 2869 */ 2870 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000058 2871 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 2872 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 2873 2874 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL 2875 2876 Passed on from 'RX_ATTENTION' TLV 2877 2878 Indicates that the computed checksum did not match the 2879 checksum in the TCP/UDP header. 2880 2881 <legal all> 2882 */ 2883 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000058 2884 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 2885 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 2886 2887 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL 2888 2889 Passed on from 'RX_ATTENTION' TLV 2890 2891 Indicates that the computed checksum did not match the 2892 checksum in the IP header. 2893 2894 <legal all> 2895 */ 2896 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000058 2897 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 2898 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 2899 2900 /* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU 2901 2902 Passed on from 'RX_MPDU_INFO' structure in 2903 'RX_MPDU_START' TLV 2904 2905 Set to 1 by RXOLE when it has not performed any 802.11 2906 to Ethernet/Natvie WiFi header conversion on this MPDU. 2907 2908 <legal all> 2909 */ 2910 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000058 2911 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 2912 #define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 2913 2914 /* Description RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0 2915 2916 Passed on from 'RX_MSDU_END' TLV (one MSB is omitted) 2917 2918 Based on a register configuration in RXDMA, this field 2919 will contain: 2920 2921 The offset in the address search table which matches the 2922 MAC source address 2923 2924 OR 2925 2926 2927 2928 'sw_peer_id' from the address search entry corresponding 2929 to the source address of the MSDU 2930 2931 <legal all> 2932 */ 2933 #define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000005c 2934 #define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 2935 #define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff 2936 2937 /* Description RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0 2938 2939 Passed on from 'RX_MPDU_INFO' structure in 2940 'RX_MPDU_START' TLV (one MSB is omitted) 2941 2942 2943 2944 Based on a register configuration in RXDMA, this field 2945 will contain: 2946 2947 The index of the address search entry corresponding to 2948 this MPDU (a value of 0xFFFF indicates an invalid AST index, 2949 meaning that no AST entry was found or no AST search was 2950 performed) 2951 2952 2953 2954 OR: 2955 2956 2957 2958 'sw_peer_id' from the address search entry corresponding 2959 to this MPDU (in case of ndp or phy_err or 2960 AST_based_lookup_valid == 0, this field will be set to 0) 2961 2962 <legal all> 2963 */ 2964 #define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000005c 2965 #define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 2966 #define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 2967 2968 /* Description RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS 2969 2970 Passed on from 'RX_MPDU_INFO' structure in 2971 'RX_MPDU_START' TLV 2972 2973 Set if the 'from DS' bit is set in the frame control. 2974 2975 <legal all> 2976 */ 2977 #define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000005c 2978 #define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 2979 #define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 2980 2981 /* Description RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS 2982 2983 Passed on from 'RX_MPDU_INFO' structure in 2984 'RX_MPDU_START' TLV 2985 2986 Set if the 'to DS' bit is set in the frame control. 2987 2988 <legal all> 2989 */ 2990 #define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000005c 2991 #define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 2992 #define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 2993 2994 /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_4 */ 2995 2996 2997 /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ 2998 2999 3000 /* Description RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 3001 3002 Address (lower 32 bits) of the MSDU buffer OR 3003 MSDU_EXTENSION descriptor OR Link Descriptor 3004 3005 3006 3007 In case of 'NULL' pointer, this field is set to 0 3008 3009 <legal all> 3010 */ 3011 #define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000060 3012 #define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 3013 #define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 3014 3015 /* Description RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 3016 3017 Address (upper 8 bits) of the MSDU buffer OR 3018 MSDU_EXTENSION descriptor OR Link Descriptor 3019 3020 3021 3022 In case of 'NULL' pointer, this field is set to 0 3023 3024 <legal all> 3025 */ 3026 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000064 3027 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 3028 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 3029 3030 /* Description RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER 3031 3032 Consumer: WBM 3033 3034 Producer: SW/FW 3035 3036 3037 3038 In case of 'NULL' pointer, this field is set to 0 3039 3040 3041 3042 Indicates to which buffer manager the buffer OR 3043 MSDU_EXTENSION descriptor OR link descriptor that is being 3044 pointed to shall be returned after the frame has been 3045 processed. It is used by WBM for routing purposes. 3046 3047 3048 3049 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 3050 to the WMB buffer idle list 3051 3052 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 3053 returned to the WMB idle link descriptor idle list 3054 3055 <enum 2 FW_BM> This buffer shall be returned to the FW 3056 3057 <enum 3 SW0_BM> This buffer shall be returned to the SW, 3058 ring 0 3059 3060 <enum 4 SW1_BM> This buffer shall be returned to the SW, 3061 ring 1 3062 3063 <enum 5 SW2_BM> This buffer shall be returned to the SW, 3064 ring 2 3065 3066 <enum 6 SW3_BM> This buffer shall be returned to the SW, 3067 ring 3 3068 3069 <enum 7 SW4_BM> This buffer shall be returned to the SW, 3070 ring 4 3071 3072 3073 3074 <legal all> 3075 */ 3076 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 3077 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 3078 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 3079 3080 /* Description RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE 3081 3082 Cookie field exclusively used by SW. 3083 3084 3085 3086 In case of 'NULL' pointer, this field is set to 0 3087 3088 3089 3090 HW ignores the contents, accept that it passes the 3091 programmed value on to other descriptors together with the 3092 physical address 3093 3094 3095 3096 Field can be used by SW to for example associate the 3097 buffers physical address with the virtual address 3098 3099 The bit definitions as used by SW are within SW HLD 3100 specification 3101 3102 3103 3104 NOTE1: 3105 3106 The three most significant bits can have a special 3107 meaning in case this struct is embedded in a TX_MPDU_DETAILS 3108 STRUCT, and field transmit_bw_restriction is set 3109 3110 3111 3112 In case of NON punctured transmission: 3113 3114 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 3115 3116 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 3117 3118 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 3119 3120 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 3121 3122 3123 3124 In case of punctured transmission: 3125 3126 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 3127 3128 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 3129 3130 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 3131 3132 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 3133 3134 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 3135 3136 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 3137 3138 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 3139 3140 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 3141 3142 3143 3144 Note: a punctured transmission is indicated by the 3145 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 3146 TLV 3147 3148 3149 3150 NOTE 2:The five most significant bits can have a special 3151 meaning in case this struct is embedded in an 3152 RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is 3153 configured for passing on the additional info 3154 from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV 3155 (FR56821). This is not supported in HastingsPrime, Pine or 3156 Moselle. 3157 3158 3159 3160 Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS 3161 control field 3162 3163 3164 3165 Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 3166 indicates MPDUs with a QoS control field. 3167 3168 3169 3170 3171 3172 <legal all> 3173 */ 3174 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000064 3175 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 3176 #define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 3177 3178 /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ 3179 3180 3181 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG 3182 3183 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3184 over multiple buffers, this field will be valid in the Last 3185 buffer used by the MSDU 3186 3187 3188 3189 <enum 0 Not_first_msdu> This is not the first MSDU in 3190 the MPDU. 3191 3192 <enum 1 first_msdu> This MSDU is the first one in the 3193 MPDU. 3194 3195 3196 3197 <legal all> 3198 */ 3199 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 3200 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 3201 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 3202 3203 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG 3204 3205 Consumer: WBM/REO/SW/FW 3206 3207 Producer: RXDMA 3208 3209 3210 3211 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3212 over multiple buffers, this field will be valid in the Last 3213 buffer used by the MSDU 3214 3215 3216 3217 <enum 0 Not_last_msdu> There are more MSDUs linked to 3218 this MSDU that belongs to this MPDU 3219 3220 <enum 1 Last_msdu> this MSDU is the last one in the 3221 MPDU. This setting is only allowed in combination with 3222 'Msdu_continuation' set to 0. This implies that when an msdu 3223 is spread out over multiple buffers and thus 3224 msdu_continuation is set, only for the very last buffer of 3225 the msdu, can the 'last_msdu_in_mpdu_flag' be set. 3226 3227 3228 3229 When both first_msdu_in_mpdu_flag and 3230 last_msdu_in_mpdu_flag are set, the MPDU that this MSDU 3231 belongs to only contains a single MSDU. 3232 3233 3234 3235 3236 3237 <legal all> 3238 */ 3239 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 3240 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 3241 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 3242 3243 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION 3244 3245 When set, this MSDU buffer was not able to hold the 3246 entire MSDU. The next buffer will therefor contain 3247 additional information related to this MSDU. 3248 3249 3250 3251 <legal all> 3252 */ 3253 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000068 3254 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 3255 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 3256 3257 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH 3258 3259 Parsed from RX_MSDU_START TLV . In the case MSDU spans 3260 over multiple buffers, this field will be valid in the First 3261 buffer used by MSDU. 3262 3263 3264 3265 Full MSDU length in bytes after decapsulation. 3266 3267 3268 3269 This field is still valid for MPDU frames without 3270 A-MSDU. It still represents MSDU length after decapsulation 3271 3272 3273 3274 Or in case of RAW MPDUs, it indicates the length of the 3275 entire MPDU (without FCS field) 3276 3277 <legal all> 3278 */ 3279 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000068 3280 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 3281 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 3282 3283 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION 3284 3285 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3286 over multiple buffers, this field will be valid in the Last 3287 buffer used by the MSDU 3288 3289 3290 3291 The ID of the REO exit ring where the MSDU frame shall 3292 push after (MPDU level) reordering has finished. 3293 3294 3295 3296 <enum 0 reo_destination_tcl> Reo will push the frame 3297 into the REO2TCL ring 3298 3299 <enum 1 reo_destination_sw1> Reo will push the frame 3300 into the REO2SW1 ring 3301 3302 <enum 2 reo_destination_sw2> Reo will push the frame 3303 into the REO2SW2 ring 3304 3305 <enum 3 reo_destination_sw3> Reo will push the frame 3306 into the REO2SW3 ring 3307 3308 <enum 4 reo_destination_sw4> Reo will push the frame 3309 into the REO2SW4 ring 3310 3311 <enum 5 reo_destination_release> Reo will push the frame 3312 into the REO_release ring 3313 3314 <enum 6 reo_destination_fw> Reo will push the frame into 3315 the REO2FW ring 3316 3317 <enum 7 reo_destination_sw5> Reo will push the frame 3318 into the REO2SW5 ring (REO remaps this in chips without 3319 REO2SW5 ring, e.g. Pine) 3320 3321 <enum 8 reo_destination_sw6> Reo will push the frame 3322 into the REO2SW6 ring (REO remaps this in chips without 3323 REO2SW6 ring, e.g. Pine) 3324 3325 <enum 9 reo_destination_9> REO remaps this <enum 10 3326 reo_destination_10> REO remaps this 3327 3328 <enum 11 reo_destination_11> REO remaps this 3329 3330 <enum 12 reo_destination_12> REO remaps this <enum 13 3331 reo_destination_13> REO remaps this 3332 3333 <enum 14 reo_destination_14> REO remaps this 3334 3335 <enum 15 reo_destination_15> REO remaps this 3336 3337 <enum 16 reo_destination_16> REO remaps this 3338 3339 <enum 17 reo_destination_17> REO remaps this 3340 3341 <enum 18 reo_destination_18> REO remaps this 3342 3343 <enum 19 reo_destination_19> REO remaps this 3344 3345 <enum 20 reo_destination_20> REO remaps this 3346 3347 <enum 21 reo_destination_21> REO remaps this 3348 3349 <enum 22 reo_destination_22> REO remaps this 3350 3351 <enum 23 reo_destination_23> REO remaps this 3352 3353 <enum 24 reo_destination_24> REO remaps this 3354 3355 <enum 25 reo_destination_25> REO remaps this 3356 3357 <enum 26 reo_destination_26> REO remaps this 3358 3359 <enum 27 reo_destination_27> REO remaps this 3360 3361 <enum 28 reo_destination_28> REO remaps this 3362 3363 <enum 29 reo_destination_29> REO remaps this 3364 3365 <enum 30 reo_destination_30> REO remaps this 3366 3367 <enum 31 reo_destination_31> REO remaps this 3368 3369 3370 3371 <legal all> 3372 */ 3373 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000068 3374 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 3375 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 3376 3377 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP 3378 3379 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3380 over multiple buffers, this field will be valid in the Last 3381 buffer used by the MSDU 3382 3383 3384 3385 When set, REO shall drop this MSDU and not forward it to 3386 any other ring... 3387 3388 <legal all> 3389 */ 3390 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000068 3391 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 3392 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 3393 3394 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID 3395 3396 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3397 over multiple buffers, this field will be valid in the Last 3398 buffer used by the MSDU 3399 3400 3401 3402 Indicates that OLE found a valid SA entry for this MSDU 3403 3404 <legal all> 3405 */ 3406 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000068 3407 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 3408 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 3409 3410 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 3411 3412 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3413 over multiple buffers, this field will be valid in the Last 3414 buffer used by the MSDU 3415 3416 3417 3418 Indicates an unsuccessful MAC source address search due 3419 to the expiring of the search timer for this MSDU 3420 3421 <legal all> 3422 */ 3423 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000068 3424 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 3425 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 3426 3427 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID 3428 3429 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3430 over multiple buffers, this field will be valid in the Last 3431 buffer used by the MSDU 3432 3433 3434 3435 Indicates that OLE found a valid DA entry for this MSDU 3436 3437 <legal all> 3438 */ 3439 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000068 3440 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 3441 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 3442 3443 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC 3444 3445 Field Only valid if da_is_valid is set 3446 3447 3448 3449 Indicates the DA address was a Multicast of Broadcast 3450 address for this MSDU 3451 3452 <legal all> 3453 */ 3454 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000068 3455 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 3456 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 3457 3458 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 3459 3460 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3461 over multiple buffers, this field will be valid in the Last 3462 buffer used by the MSDU 3463 3464 3465 3466 Indicates an unsuccessful MAC destination address search 3467 due to the expiring of the search timer for this MSDU 3468 3469 <legal all> 3470 */ 3471 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000068 3472 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 3473 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 3474 3475 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB 3476 3477 Passed on from 'RX_MSDU_END' TLV (only the MSB is 3478 reported as the LSB is always zero) 3479 3480 Number of bytes padded to make sure that the L3 header 3481 will always start of a Dword boundary 3482 3483 <legal all> 3484 */ 3485 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000068 3486 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 3487 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 3488 3489 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL 3490 3491 Passed on from 'RX_ATTENTION' TLV 3492 3493 Indicates that the computed checksum did not match the 3494 checksum in the TCP/UDP header. 3495 3496 <legal all> 3497 */ 3498 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000068 3499 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 3500 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 3501 3502 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL 3503 3504 Passed on from 'RX_ATTENTION' TLV 3505 3506 Indicates that the computed checksum did not match the 3507 checksum in the IP header. 3508 3509 <legal all> 3510 */ 3511 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000068 3512 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 3513 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 3514 3515 /* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU 3516 3517 Passed on from 'RX_MPDU_INFO' structure in 3518 'RX_MPDU_START' TLV 3519 3520 Set to 1 by RXOLE when it has not performed any 802.11 3521 to Ethernet/Natvie WiFi header conversion on this MPDU. 3522 3523 <legal all> 3524 */ 3525 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000068 3526 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 3527 #define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 3528 3529 /* Description RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0 3530 3531 Passed on from 'RX_MSDU_END' TLV (one MSB is omitted) 3532 3533 Based on a register configuration in RXDMA, this field 3534 will contain: 3535 3536 The offset in the address search table which matches the 3537 MAC source address 3538 3539 OR 3540 3541 3542 3543 'sw_peer_id' from the address search entry corresponding 3544 to the source address of the MSDU 3545 3546 <legal all> 3547 */ 3548 #define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000006c 3549 #define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 3550 #define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff 3551 3552 /* Description RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0 3553 3554 Passed on from 'RX_MPDU_INFO' structure in 3555 'RX_MPDU_START' TLV (one MSB is omitted) 3556 3557 3558 3559 Based on a register configuration in RXDMA, this field 3560 will contain: 3561 3562 The index of the address search entry corresponding to 3563 this MPDU (a value of 0xFFFF indicates an invalid AST index, 3564 meaning that no AST entry was found or no AST search was 3565 performed) 3566 3567 3568 3569 OR: 3570 3571 3572 3573 'sw_peer_id' from the address search entry corresponding 3574 to this MPDU (in case of ndp or phy_err or 3575 AST_based_lookup_valid == 0, this field will be set to 0) 3576 3577 <legal all> 3578 */ 3579 #define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000006c 3580 #define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 3581 #define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 3582 3583 /* Description RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS 3584 3585 Passed on from 'RX_MPDU_INFO' structure in 3586 'RX_MPDU_START' TLV 3587 3588 Set if the 'from DS' bit is set in the frame control. 3589 3590 <legal all> 3591 */ 3592 #define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000006c 3593 #define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 3594 #define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 3595 3596 /* Description RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS 3597 3598 Passed on from 'RX_MPDU_INFO' structure in 3599 'RX_MPDU_START' TLV 3600 3601 Set if the 'to DS' bit is set in the frame control. 3602 3603 <legal all> 3604 */ 3605 #define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000006c 3606 #define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 3607 #define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 3608 3609 /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_5 */ 3610 3611 3612 /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ 3613 3614 3615 /* Description RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 3616 3617 Address (lower 32 bits) of the MSDU buffer OR 3618 MSDU_EXTENSION descriptor OR Link Descriptor 3619 3620 3621 3622 In case of 'NULL' pointer, this field is set to 0 3623 3624 <legal all> 3625 */ 3626 #define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000070 3627 #define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 3628 #define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 3629 3630 /* Description RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 3631 3632 Address (upper 8 bits) of the MSDU buffer OR 3633 MSDU_EXTENSION descriptor OR Link Descriptor 3634 3635 3636 3637 In case of 'NULL' pointer, this field is set to 0 3638 3639 <legal all> 3640 */ 3641 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000074 3642 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 3643 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 3644 3645 /* Description RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER 3646 3647 Consumer: WBM 3648 3649 Producer: SW/FW 3650 3651 3652 3653 In case of 'NULL' pointer, this field is set to 0 3654 3655 3656 3657 Indicates to which buffer manager the buffer OR 3658 MSDU_EXTENSION descriptor OR link descriptor that is being 3659 pointed to shall be returned after the frame has been 3660 processed. It is used by WBM for routing purposes. 3661 3662 3663 3664 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 3665 to the WMB buffer idle list 3666 3667 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 3668 returned to the WMB idle link descriptor idle list 3669 3670 <enum 2 FW_BM> This buffer shall be returned to the FW 3671 3672 <enum 3 SW0_BM> This buffer shall be returned to the SW, 3673 ring 0 3674 3675 <enum 4 SW1_BM> This buffer shall be returned to the SW, 3676 ring 1 3677 3678 <enum 5 SW2_BM> This buffer shall be returned to the SW, 3679 ring 2 3680 3681 <enum 6 SW3_BM> This buffer shall be returned to the SW, 3682 ring 3 3683 3684 <enum 7 SW4_BM> This buffer shall be returned to the SW, 3685 ring 4 3686 3687 3688 3689 <legal all> 3690 */ 3691 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 3692 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 3693 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 3694 3695 /* Description RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE 3696 3697 Cookie field exclusively used by SW. 3698 3699 3700 3701 In case of 'NULL' pointer, this field is set to 0 3702 3703 3704 3705 HW ignores the contents, accept that it passes the 3706 programmed value on to other descriptors together with the 3707 physical address 3708 3709 3710 3711 Field can be used by SW to for example associate the 3712 buffers physical address with the virtual address 3713 3714 The bit definitions as used by SW are within SW HLD 3715 specification 3716 3717 3718 3719 NOTE1: 3720 3721 The three most significant bits can have a special 3722 meaning in case this struct is embedded in a TX_MPDU_DETAILS 3723 STRUCT, and field transmit_bw_restriction is set 3724 3725 3726 3727 In case of NON punctured transmission: 3728 3729 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 3730 3731 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 3732 3733 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 3734 3735 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 3736 3737 3738 3739 In case of punctured transmission: 3740 3741 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 3742 3743 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 3744 3745 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 3746 3747 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 3748 3749 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 3750 3751 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 3752 3753 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 3754 3755 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 3756 3757 3758 3759 Note: a punctured transmission is indicated by the 3760 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 3761 TLV 3762 3763 3764 3765 NOTE 2:The five most significant bits can have a special 3766 meaning in case this struct is embedded in an 3767 RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is 3768 configured for passing on the additional info 3769 from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV 3770 (FR56821). This is not supported in HastingsPrime, Pine or 3771 Moselle. 3772 3773 3774 3775 Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS 3776 control field 3777 3778 3779 3780 Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 3781 indicates MPDUs with a QoS control field. 3782 3783 3784 3785 3786 3787 <legal all> 3788 */ 3789 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000074 3790 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 3791 #define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 3792 3793 /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ 3794 3795 3796 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG 3797 3798 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3799 over multiple buffers, this field will be valid in the Last 3800 buffer used by the MSDU 3801 3802 3803 3804 <enum 0 Not_first_msdu> This is not the first MSDU in 3805 the MPDU. 3806 3807 <enum 1 first_msdu> This MSDU is the first one in the 3808 MPDU. 3809 3810 3811 3812 <legal all> 3813 */ 3814 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 3815 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 3816 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 3817 3818 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG 3819 3820 Consumer: WBM/REO/SW/FW 3821 3822 Producer: RXDMA 3823 3824 3825 3826 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3827 over multiple buffers, this field will be valid in the Last 3828 buffer used by the MSDU 3829 3830 3831 3832 <enum 0 Not_last_msdu> There are more MSDUs linked to 3833 this MSDU that belongs to this MPDU 3834 3835 <enum 1 Last_msdu> this MSDU is the last one in the 3836 MPDU. This setting is only allowed in combination with 3837 'Msdu_continuation' set to 0. This implies that when an msdu 3838 is spread out over multiple buffers and thus 3839 msdu_continuation is set, only for the very last buffer of 3840 the msdu, can the 'last_msdu_in_mpdu_flag' be set. 3841 3842 3843 3844 When both first_msdu_in_mpdu_flag and 3845 last_msdu_in_mpdu_flag are set, the MPDU that this MSDU 3846 belongs to only contains a single MSDU. 3847 3848 3849 3850 3851 3852 <legal all> 3853 */ 3854 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 3855 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 3856 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 3857 3858 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION 3859 3860 When set, this MSDU buffer was not able to hold the 3861 entire MSDU. The next buffer will therefor contain 3862 additional information related to this MSDU. 3863 3864 3865 3866 <legal all> 3867 */ 3868 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000078 3869 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 3870 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 3871 3872 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH 3873 3874 Parsed from RX_MSDU_START TLV . In the case MSDU spans 3875 over multiple buffers, this field will be valid in the First 3876 buffer used by MSDU. 3877 3878 3879 3880 Full MSDU length in bytes after decapsulation. 3881 3882 3883 3884 This field is still valid for MPDU frames without 3885 A-MSDU. It still represents MSDU length after decapsulation 3886 3887 3888 3889 Or in case of RAW MPDUs, it indicates the length of the 3890 entire MPDU (without FCS field) 3891 3892 <legal all> 3893 */ 3894 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000078 3895 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 3896 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 3897 3898 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION 3899 3900 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3901 over multiple buffers, this field will be valid in the Last 3902 buffer used by the MSDU 3903 3904 3905 3906 The ID of the REO exit ring where the MSDU frame shall 3907 push after (MPDU level) reordering has finished. 3908 3909 3910 3911 <enum 0 reo_destination_tcl> Reo will push the frame 3912 into the REO2TCL ring 3913 3914 <enum 1 reo_destination_sw1> Reo will push the frame 3915 into the REO2SW1 ring 3916 3917 <enum 2 reo_destination_sw2> Reo will push the frame 3918 into the REO2SW2 ring 3919 3920 <enum 3 reo_destination_sw3> Reo will push the frame 3921 into the REO2SW3 ring 3922 3923 <enum 4 reo_destination_sw4> Reo will push the frame 3924 into the REO2SW4 ring 3925 3926 <enum 5 reo_destination_release> Reo will push the frame 3927 into the REO_release ring 3928 3929 <enum 6 reo_destination_fw> Reo will push the frame into 3930 the REO2FW ring 3931 3932 <enum 7 reo_destination_sw5> Reo will push the frame 3933 into the REO2SW5 ring (REO remaps this in chips without 3934 REO2SW5 ring, e.g. Pine) 3935 3936 <enum 8 reo_destination_sw6> Reo will push the frame 3937 into the REO2SW6 ring (REO remaps this in chips without 3938 REO2SW6 ring, e.g. Pine) 3939 3940 <enum 9 reo_destination_9> REO remaps this <enum 10 3941 reo_destination_10> REO remaps this 3942 3943 <enum 11 reo_destination_11> REO remaps this 3944 3945 <enum 12 reo_destination_12> REO remaps this <enum 13 3946 reo_destination_13> REO remaps this 3947 3948 <enum 14 reo_destination_14> REO remaps this 3949 3950 <enum 15 reo_destination_15> REO remaps this 3951 3952 <enum 16 reo_destination_16> REO remaps this 3953 3954 <enum 17 reo_destination_17> REO remaps this 3955 3956 <enum 18 reo_destination_18> REO remaps this 3957 3958 <enum 19 reo_destination_19> REO remaps this 3959 3960 <enum 20 reo_destination_20> REO remaps this 3961 3962 <enum 21 reo_destination_21> REO remaps this 3963 3964 <enum 22 reo_destination_22> REO remaps this 3965 3966 <enum 23 reo_destination_23> REO remaps this 3967 3968 <enum 24 reo_destination_24> REO remaps this 3969 3970 <enum 25 reo_destination_25> REO remaps this 3971 3972 <enum 26 reo_destination_26> REO remaps this 3973 3974 <enum 27 reo_destination_27> REO remaps this 3975 3976 <enum 28 reo_destination_28> REO remaps this 3977 3978 <enum 29 reo_destination_29> REO remaps this 3979 3980 <enum 30 reo_destination_30> REO remaps this 3981 3982 <enum 31 reo_destination_31> REO remaps this 3983 3984 3985 3986 <legal all> 3987 */ 3988 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000078 3989 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 3990 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 3991 3992 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP 3993 3994 Parsed from RX_MSDU_END TLV . In the case MSDU spans 3995 over multiple buffers, this field will be valid in the Last 3996 buffer used by the MSDU 3997 3998 3999 4000 When set, REO shall drop this MSDU and not forward it to 4001 any other ring... 4002 4003 <legal all> 4004 */ 4005 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000078 4006 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 4007 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 4008 4009 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID 4010 4011 Parsed from RX_MSDU_END TLV . In the case MSDU spans 4012 over multiple buffers, this field will be valid in the Last 4013 buffer used by the MSDU 4014 4015 4016 4017 Indicates that OLE found a valid SA entry for this MSDU 4018 4019 <legal all> 4020 */ 4021 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000078 4022 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 4023 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 4024 4025 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT 4026 4027 Parsed from RX_MSDU_END TLV . In the case MSDU spans 4028 over multiple buffers, this field will be valid in the Last 4029 buffer used by the MSDU 4030 4031 4032 4033 Indicates an unsuccessful MAC source address search due 4034 to the expiring of the search timer for this MSDU 4035 4036 <legal all> 4037 */ 4038 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000078 4039 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 4040 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 4041 4042 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID 4043 4044 Parsed from RX_MSDU_END TLV . In the case MSDU spans 4045 over multiple buffers, this field will be valid in the Last 4046 buffer used by the MSDU 4047 4048 4049 4050 Indicates that OLE found a valid DA entry for this MSDU 4051 4052 <legal all> 4053 */ 4054 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000078 4055 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 4056 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 4057 4058 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC 4059 4060 Field Only valid if da_is_valid is set 4061 4062 4063 4064 Indicates the DA address was a Multicast of Broadcast 4065 address for this MSDU 4066 4067 <legal all> 4068 */ 4069 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000078 4070 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 4071 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 4072 4073 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT 4074 4075 Parsed from RX_MSDU_END TLV . In the case MSDU spans 4076 over multiple buffers, this field will be valid in the Last 4077 buffer used by the MSDU 4078 4079 4080 4081 Indicates an unsuccessful MAC destination address search 4082 due to the expiring of the search timer for this MSDU 4083 4084 <legal all> 4085 */ 4086 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000078 4087 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 4088 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 4089 4090 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB 4091 4092 Passed on from 'RX_MSDU_END' TLV (only the MSB is 4093 reported as the LSB is always zero) 4094 4095 Number of bytes padded to make sure that the L3 header 4096 will always start of a Dword boundary 4097 4098 <legal all> 4099 */ 4100 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000078 4101 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 4102 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 4103 4104 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL 4105 4106 Passed on from 'RX_ATTENTION' TLV 4107 4108 Indicates that the computed checksum did not match the 4109 checksum in the TCP/UDP header. 4110 4111 <legal all> 4112 */ 4113 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000078 4114 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 4115 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 4116 4117 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL 4118 4119 Passed on from 'RX_ATTENTION' TLV 4120 4121 Indicates that the computed checksum did not match the 4122 checksum in the IP header. 4123 4124 <legal all> 4125 */ 4126 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000078 4127 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 4128 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 4129 4130 /* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU 4131 4132 Passed on from 'RX_MPDU_INFO' structure in 4133 'RX_MPDU_START' TLV 4134 4135 Set to 1 by RXOLE when it has not performed any 802.11 4136 to Ethernet/Natvie WiFi header conversion on this MPDU. 4137 4138 <legal all> 4139 */ 4140 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000078 4141 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 4142 #define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 4143 4144 /* Description RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0 4145 4146 Passed on from 'RX_MSDU_END' TLV (one MSB is omitted) 4147 4148 Based on a register configuration in RXDMA, this field 4149 will contain: 4150 4151 The offset in the address search table which matches the 4152 MAC source address 4153 4154 OR 4155 4156 4157 4158 'sw_peer_id' from the address search entry corresponding 4159 to the source address of the MSDU 4160 4161 <legal all> 4162 */ 4163 #define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000007c 4164 #define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 4165 #define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff 4166 4167 /* Description RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0 4168 4169 Passed on from 'RX_MPDU_INFO' structure in 4170 'RX_MPDU_START' TLV (one MSB is omitted) 4171 4172 4173 4174 Based on a register configuration in RXDMA, this field 4175 will contain: 4176 4177 The index of the address search entry corresponding to 4178 this MPDU (a value of 0xFFFF indicates an invalid AST index, 4179 meaning that no AST entry was found or no AST search was 4180 performed) 4181 4182 4183 4184 OR: 4185 4186 4187 4188 'sw_peer_id' from the address search entry corresponding 4189 to this MPDU (in case of ndp or phy_err or 4190 AST_based_lookup_valid == 0, this field will be set to 0) 4191 4192 <legal all> 4193 */ 4194 #define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000007c 4195 #define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 4196 #define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 4197 4198 /* Description RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS 4199 4200 Passed on from 'RX_MPDU_INFO' structure in 4201 'RX_MPDU_START' TLV 4202 4203 Set if the 'from DS' bit is set in the frame control. 4204 4205 <legal all> 4206 */ 4207 #define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000007c 4208 #define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 4209 #define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 4210 4211 /* Description RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS 4212 4213 Passed on from 'RX_MPDU_INFO' structure in 4214 'RX_MPDU_START' TLV 4215 4216 Set if the 'to DS' bit is set in the frame control. 4217 4218 <legal all> 4219 */ 4220 #define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000007c 4221 #define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 4222 #define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 4223 4224 4225 #endif // _RX_MSDU_LINK_H_ 4226