1 /* 2 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _RX_REO_QUEUE_EXT_H_ 18 #define _RX_REO_QUEUE_EXT_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "uniform_descriptor_header.h" 23 #include "rx_mpdu_link_ptr.h" 24 25 // ################ START SUMMARY ################# 26 // 27 // Dword Fields 28 // 0 struct uniform_descriptor_header descriptor_header; 29 // 1 reserved_1a[31:0] 30 // 2-3 struct rx_mpdu_link_ptr mpdu_link_pointer_0; 31 // 4-5 struct rx_mpdu_link_ptr mpdu_link_pointer_1; 32 // 6-7 struct rx_mpdu_link_ptr mpdu_link_pointer_2; 33 // 8-9 struct rx_mpdu_link_ptr mpdu_link_pointer_3; 34 // 10-11 struct rx_mpdu_link_ptr mpdu_link_pointer_4; 35 // 12-13 struct rx_mpdu_link_ptr mpdu_link_pointer_5; 36 // 14-15 struct rx_mpdu_link_ptr mpdu_link_pointer_6; 37 // 16-17 struct rx_mpdu_link_ptr mpdu_link_pointer_7; 38 // 18-19 struct rx_mpdu_link_ptr mpdu_link_pointer_8; 39 // 20-21 struct rx_mpdu_link_ptr mpdu_link_pointer_9; 40 // 22-23 struct rx_mpdu_link_ptr mpdu_link_pointer_10; 41 // 24-25 struct rx_mpdu_link_ptr mpdu_link_pointer_11; 42 // 26-27 struct rx_mpdu_link_ptr mpdu_link_pointer_12; 43 // 28-29 struct rx_mpdu_link_ptr mpdu_link_pointer_13; 44 // 30-31 struct rx_mpdu_link_ptr mpdu_link_pointer_14; 45 // 46 // ################ END SUMMARY ################# 47 48 #define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32 49 50 struct rx_reo_queue_ext { 51 struct uniform_descriptor_header descriptor_header; 52 uint32_t reserved_1a : 32; //[31:0] 53 struct rx_mpdu_link_ptr mpdu_link_pointer_0; 54 struct rx_mpdu_link_ptr mpdu_link_pointer_1; 55 struct rx_mpdu_link_ptr mpdu_link_pointer_2; 56 struct rx_mpdu_link_ptr mpdu_link_pointer_3; 57 struct rx_mpdu_link_ptr mpdu_link_pointer_4; 58 struct rx_mpdu_link_ptr mpdu_link_pointer_5; 59 struct rx_mpdu_link_ptr mpdu_link_pointer_6; 60 struct rx_mpdu_link_ptr mpdu_link_pointer_7; 61 struct rx_mpdu_link_ptr mpdu_link_pointer_8; 62 struct rx_mpdu_link_ptr mpdu_link_pointer_9; 63 struct rx_mpdu_link_ptr mpdu_link_pointer_10; 64 struct rx_mpdu_link_ptr mpdu_link_pointer_11; 65 struct rx_mpdu_link_ptr mpdu_link_pointer_12; 66 struct rx_mpdu_link_ptr mpdu_link_pointer_13; 67 struct rx_mpdu_link_ptr mpdu_link_pointer_14; 68 }; 69 70 /* 71 72 struct uniform_descriptor_header descriptor_header 73 74 Details about which module owns this struct. 75 76 Note that sub field Buffer_type shall be set to 77 Receive_REO_queue_ext_descriptor 78 79 reserved_1a 80 81 <legal 0> 82 83 struct rx_mpdu_link_ptr mpdu_link_pointer_0 84 85 Consumer: REO 86 87 Producer: REO 88 89 90 91 Pointer to the next MPDU_link descriptor in the MPDU 92 queue 93 94 struct rx_mpdu_link_ptr mpdu_link_pointer_1 95 96 Consumer: REO 97 98 Producer: REO 99 100 101 102 Pointer to the next MPDU_link descriptor in the MPDU 103 queue 104 105 struct rx_mpdu_link_ptr mpdu_link_pointer_2 106 107 Consumer: REO 108 109 Producer: REO 110 111 112 113 Pointer to the next MPDU_link descriptor in the MPDU 114 queue 115 116 struct rx_mpdu_link_ptr mpdu_link_pointer_3 117 118 Consumer: REO 119 120 Producer: REO 121 122 123 124 Pointer to the next MPDU_link descriptor in the MPDU 125 queue 126 127 struct rx_mpdu_link_ptr mpdu_link_pointer_4 128 129 Consumer: REO 130 131 Producer: REO 132 133 134 135 Pointer to the next MPDU_link descriptor in the MPDU 136 queue 137 138 struct rx_mpdu_link_ptr mpdu_link_pointer_5 139 140 Consumer: REO 141 142 Producer: REO 143 144 145 146 Pointer to the next MPDU_link descriptor in the MPDU 147 queue 148 149 struct rx_mpdu_link_ptr mpdu_link_pointer_6 150 151 Consumer: REO 152 153 Producer: REO 154 155 156 157 Pointer to the next MPDU_link descriptor in the MPDU 158 queue 159 160 struct rx_mpdu_link_ptr mpdu_link_pointer_7 161 162 Consumer: REO 163 164 Producer: REO 165 166 167 168 Pointer to the next MPDU_link descriptor in the MPDU 169 queue 170 171 struct rx_mpdu_link_ptr mpdu_link_pointer_8 172 173 Consumer: REO 174 175 Producer: REO 176 177 178 179 Pointer to the next MPDU_link descriptor in the MPDU 180 queue 181 182 struct rx_mpdu_link_ptr mpdu_link_pointer_9 183 184 Consumer: REO 185 186 Producer: REO 187 188 189 190 Pointer to the next MPDU_link descriptor in the MPDU 191 queue 192 193 struct rx_mpdu_link_ptr mpdu_link_pointer_10 194 195 Consumer: REO 196 197 Producer: REO 198 199 200 201 Pointer to the next MPDU_link descriptor in the MPDU 202 queue 203 204 struct rx_mpdu_link_ptr mpdu_link_pointer_11 205 206 Consumer: REO 207 208 Producer: REO 209 210 211 212 Pointer to the next MPDU_link descriptor in the MPDU 213 queue 214 215 struct rx_mpdu_link_ptr mpdu_link_pointer_12 216 217 Consumer: REO 218 219 Producer: REO 220 221 222 223 Pointer to the next MPDU_link descriptor in the MPDU 224 queue 225 226 struct rx_mpdu_link_ptr mpdu_link_pointer_13 227 228 Consumer: REO 229 230 Producer: REO 231 232 233 234 Pointer to the next MPDU_link descriptor in the MPDU 235 queue 236 237 struct rx_mpdu_link_ptr mpdu_link_pointer_14 238 239 Consumer: REO 240 241 Producer: REO 242 243 244 245 Pointer to the next MPDU_link descriptor in the MPDU 246 queue 247 */ 248 249 250 /* EXTERNAL REFERENCE : struct uniform_descriptor_header descriptor_header */ 251 252 253 /* Description RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER 254 255 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 256 257 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 258 259 260 261 The owner of this data structure: 262 263 <enum 0 WBM_owned> Buffer Manager currently owns this 264 data structure. 265 266 <enum 1 SW_OR_FW_owned> Software of FW currently owns 267 this data structure. 268 269 <enum 2 TQM_owned> Transmit Queue Manager currently owns 270 this data structure. 271 272 <enum 3 RXDMA_owned> Receive DMA currently owns this 273 data structure. 274 275 <enum 4 REO_owned> Reorder currently owns this data 276 structure. 277 278 <enum 5 SWITCH_owned> SWITCH currently owns this data 279 structure. 280 281 282 283 <legal 0-5> 284 */ 285 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 286 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_LSB 0 287 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f 288 289 /* Description RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE 290 291 Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 292 293 Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 294 295 296 297 Field describing what contents format is of this 298 descriptor 299 300 301 302 <enum 0 Transmit_MSDU_Link_descriptor > 303 304 <enum 1 Transmit_MPDU_Link_descriptor > 305 306 <enum 2 Transmit_MPDU_Queue_head_descriptor> 307 308 <enum 3 Transmit_MPDU_Queue_ext_descriptor> 309 310 <enum 4 Transmit_flow_descriptor> 311 312 <enum 5 Transmit_buffer > NOT TO BE USED: 313 314 315 316 <enum 6 Receive_MSDU_Link_descriptor > 317 318 <enum 7 Receive_MPDU_Link_descriptor > 319 320 <enum 8 Receive_REO_queue_descriptor > 321 322 <enum 9 Receive_REO_queue_ext_descriptor > 323 324 325 326 <enum 10 Receive_buffer > 327 328 329 330 <enum 11 Idle_link_list_entry> 331 332 333 334 <legal 0-11> 335 */ 336 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 337 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 338 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 339 340 /* Description RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A 341 342 <legal 0> 343 */ 344 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 345 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 346 #define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 347 348 /* Description RX_REO_QUEUE_EXT_1_RESERVED_1A 349 350 <legal 0> 351 */ 352 #define RX_REO_QUEUE_EXT_1_RESERVED_1A_OFFSET 0x00000004 353 #define RX_REO_QUEUE_EXT_1_RESERVED_1A_LSB 0 354 #define RX_REO_QUEUE_EXT_1_RESERVED_1A_MASK 0xffffffff 355 356 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_0 */ 357 358 359 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 360 361 362 /* Description RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 363 364 Address (lower 32 bits) of the MSDU buffer OR 365 MSDU_EXTENSION descriptor OR Link Descriptor 366 367 368 369 In case of 'NULL' pointer, this field is set to 0 370 371 <legal all> 372 */ 373 #define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000008 374 #define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 375 #define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 376 377 /* Description RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 378 379 Address (upper 8 bits) of the MSDU buffer OR 380 MSDU_EXTENSION descriptor OR Link Descriptor 381 382 383 384 In case of 'NULL' pointer, this field is set to 0 385 386 <legal all> 387 */ 388 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000000c 389 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 390 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 391 392 /* Description RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 393 394 Consumer: WBM 395 396 Producer: SW/FW 397 398 399 400 In case of 'NULL' pointer, this field is set to 0 401 402 403 404 Indicates to which buffer manager the buffer OR 405 MSDU_EXTENSION descriptor OR link descriptor that is being 406 pointed to shall be returned after the frame has been 407 processed. It is used by WBM for routing purposes. 408 409 410 411 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 412 to the WMB buffer idle list 413 414 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 415 returned to the WMB idle link descriptor idle list 416 417 <enum 2 FW_BM> This buffer shall be returned to the FW 418 419 <enum 3 SW0_BM> This buffer shall be returned to the SW, 420 ring 0 421 422 <enum 4 SW1_BM> This buffer shall be returned to the SW, 423 ring 1 424 425 <enum 5 SW2_BM> This buffer shall be returned to the SW, 426 ring 2 427 428 <enum 6 SW3_BM> This buffer shall be returned to the SW, 429 ring 3 430 431 <enum 7 SW4_BM> This buffer shall be returned to the SW, 432 ring 4 433 434 435 436 <legal all> 437 */ 438 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000000c 439 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 440 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 441 442 /* Description RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 443 444 Cookie field exclusively used by SW. 445 446 447 448 In case of 'NULL' pointer, this field is set to 0 449 450 451 452 HW ignores the contents, accept that it passes the 453 programmed value on to other descriptors together with the 454 physical address 455 456 457 458 Field can be used by SW to for example associate the 459 buffers physical address with the virtual address 460 461 The bit definitions as used by SW are within SW HLD 462 specification 463 464 465 466 NOTE1: 467 468 The three most significant bits can have a special 469 meaning in case this struct is embedded in a TX_MPDU_DETAILS 470 STRUCT, and field transmit_bw_restriction is set 471 472 473 474 In case of NON punctured transmission: 475 476 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 477 478 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 479 480 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 481 482 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 483 484 485 486 In case of punctured transmission: 487 488 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 489 490 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 491 492 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 493 494 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 495 496 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 497 498 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 499 500 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 501 502 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 503 504 505 506 Note: a punctured transmission is indicated by the 507 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 508 TLV 509 510 511 512 NOTE 2:The five most significant bits can have a special 513 meaning in case this struct is embedded in an 514 RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is 515 configured for passing on the additional info 516 from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV 517 (FR56821). This is not supported in HastingsPrime, Pine or 518 Moselle. 519 520 521 522 Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS 523 control field 524 525 526 527 Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 528 indicates MPDUs with a QoS control field. 529 530 531 532 533 534 <legal all> 535 */ 536 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000000c 537 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 538 #define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 539 540 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_1 */ 541 542 543 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 544 545 546 /* Description RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 547 548 Address (lower 32 bits) of the MSDU buffer OR 549 MSDU_EXTENSION descriptor OR Link Descriptor 550 551 552 553 In case of 'NULL' pointer, this field is set to 0 554 555 <legal all> 556 */ 557 #define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010 558 #define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 559 #define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 560 561 /* Description RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 562 563 Address (upper 8 bits) of the MSDU buffer OR 564 MSDU_EXTENSION descriptor OR Link Descriptor 565 566 567 568 In case of 'NULL' pointer, this field is set to 0 569 570 <legal all> 571 */ 572 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014 573 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 574 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 575 576 /* Description RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 577 578 Consumer: WBM 579 580 Producer: SW/FW 581 582 583 584 In case of 'NULL' pointer, this field is set to 0 585 586 587 588 Indicates to which buffer manager the buffer OR 589 MSDU_EXTENSION descriptor OR link descriptor that is being 590 pointed to shall be returned after the frame has been 591 processed. It is used by WBM for routing purposes. 592 593 594 595 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 596 to the WMB buffer idle list 597 598 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 599 returned to the WMB idle link descriptor idle list 600 601 <enum 2 FW_BM> This buffer shall be returned to the FW 602 603 <enum 3 SW0_BM> This buffer shall be returned to the SW, 604 ring 0 605 606 <enum 4 SW1_BM> This buffer shall be returned to the SW, 607 ring 1 608 609 <enum 5 SW2_BM> This buffer shall be returned to the SW, 610 ring 2 611 612 <enum 6 SW3_BM> This buffer shall be returned to the SW, 613 ring 3 614 615 <enum 7 SW4_BM> This buffer shall be returned to the SW, 616 ring 4 617 618 619 620 <legal all> 621 */ 622 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 623 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 624 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 625 626 /* Description RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 627 628 Cookie field exclusively used by SW. 629 630 631 632 In case of 'NULL' pointer, this field is set to 0 633 634 635 636 HW ignores the contents, accept that it passes the 637 programmed value on to other descriptors together with the 638 physical address 639 640 641 642 Field can be used by SW to for example associate the 643 buffers physical address with the virtual address 644 645 The bit definitions as used by SW are within SW HLD 646 specification 647 648 649 650 NOTE1: 651 652 The three most significant bits can have a special 653 meaning in case this struct is embedded in a TX_MPDU_DETAILS 654 STRUCT, and field transmit_bw_restriction is set 655 656 657 658 In case of NON punctured transmission: 659 660 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 661 662 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 663 664 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 665 666 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 667 668 669 670 In case of punctured transmission: 671 672 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 673 674 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 675 676 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 677 678 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 679 680 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 681 682 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 683 684 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 685 686 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 687 688 689 690 Note: a punctured transmission is indicated by the 691 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 692 TLV 693 694 695 696 NOTE 2:The five most significant bits can have a special 697 meaning in case this struct is embedded in an 698 RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is 699 configured for passing on the additional info 700 from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV 701 (FR56821). This is not supported in HastingsPrime, Pine or 702 Moselle. 703 704 705 706 Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS 707 control field 708 709 710 711 Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 712 indicates MPDUs with a QoS control field. 713 714 715 716 717 718 <legal all> 719 */ 720 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014 721 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 722 #define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 723 724 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_2 */ 725 726 727 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 728 729 730 /* Description RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 731 732 Address (lower 32 bits) of the MSDU buffer OR 733 MSDU_EXTENSION descriptor OR Link Descriptor 734 735 736 737 In case of 'NULL' pointer, this field is set to 0 738 739 <legal all> 740 */ 741 #define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000018 742 #define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 743 #define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 744 745 /* Description RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 746 747 Address (upper 8 bits) of the MSDU buffer OR 748 MSDU_EXTENSION descriptor OR Link Descriptor 749 750 751 752 In case of 'NULL' pointer, this field is set to 0 753 754 <legal all> 755 */ 756 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000001c 757 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 758 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 759 760 /* Description RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 761 762 Consumer: WBM 763 764 Producer: SW/FW 765 766 767 768 In case of 'NULL' pointer, this field is set to 0 769 770 771 772 Indicates to which buffer manager the buffer OR 773 MSDU_EXTENSION descriptor OR link descriptor that is being 774 pointed to shall be returned after the frame has been 775 processed. It is used by WBM for routing purposes. 776 777 778 779 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 780 to the WMB buffer idle list 781 782 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 783 returned to the WMB idle link descriptor idle list 784 785 <enum 2 FW_BM> This buffer shall be returned to the FW 786 787 <enum 3 SW0_BM> This buffer shall be returned to the SW, 788 ring 0 789 790 <enum 4 SW1_BM> This buffer shall be returned to the SW, 791 ring 1 792 793 <enum 5 SW2_BM> This buffer shall be returned to the SW, 794 ring 2 795 796 <enum 6 SW3_BM> This buffer shall be returned to the SW, 797 ring 3 798 799 <enum 7 SW4_BM> This buffer shall be returned to the SW, 800 ring 4 801 802 803 804 <legal all> 805 */ 806 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000001c 807 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 808 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 809 810 /* Description RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 811 812 Cookie field exclusively used by SW. 813 814 815 816 In case of 'NULL' pointer, this field is set to 0 817 818 819 820 HW ignores the contents, accept that it passes the 821 programmed value on to other descriptors together with the 822 physical address 823 824 825 826 Field can be used by SW to for example associate the 827 buffers physical address with the virtual address 828 829 The bit definitions as used by SW are within SW HLD 830 specification 831 832 833 834 NOTE1: 835 836 The three most significant bits can have a special 837 meaning in case this struct is embedded in a TX_MPDU_DETAILS 838 STRUCT, and field transmit_bw_restriction is set 839 840 841 842 In case of NON punctured transmission: 843 844 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 845 846 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 847 848 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 849 850 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 851 852 853 854 In case of punctured transmission: 855 856 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 857 858 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 859 860 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 861 862 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 863 864 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 865 866 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 867 868 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 869 870 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 871 872 873 874 Note: a punctured transmission is indicated by the 875 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 876 TLV 877 878 879 880 NOTE 2:The five most significant bits can have a special 881 meaning in case this struct is embedded in an 882 RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is 883 configured for passing on the additional info 884 from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV 885 (FR56821). This is not supported in HastingsPrime, Pine or 886 Moselle. 887 888 889 890 Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS 891 control field 892 893 894 895 Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 896 indicates MPDUs with a QoS control field. 897 898 899 900 901 902 <legal all> 903 */ 904 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000001c 905 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 906 #define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 907 908 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_3 */ 909 910 911 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 912 913 914 /* Description RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 915 916 Address (lower 32 bits) of the MSDU buffer OR 917 MSDU_EXTENSION descriptor OR Link Descriptor 918 919 920 921 In case of 'NULL' pointer, this field is set to 0 922 923 <legal all> 924 */ 925 #define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000020 926 #define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 927 #define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 928 929 /* Description RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 930 931 Address (upper 8 bits) of the MSDU buffer OR 932 MSDU_EXTENSION descriptor OR Link Descriptor 933 934 935 936 In case of 'NULL' pointer, this field is set to 0 937 938 <legal all> 939 */ 940 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000024 941 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 942 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 943 944 /* Description RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 945 946 Consumer: WBM 947 948 Producer: SW/FW 949 950 951 952 In case of 'NULL' pointer, this field is set to 0 953 954 955 956 Indicates to which buffer manager the buffer OR 957 MSDU_EXTENSION descriptor OR link descriptor that is being 958 pointed to shall be returned after the frame has been 959 processed. It is used by WBM for routing purposes. 960 961 962 963 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 964 to the WMB buffer idle list 965 966 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 967 returned to the WMB idle link descriptor idle list 968 969 <enum 2 FW_BM> This buffer shall be returned to the FW 970 971 <enum 3 SW0_BM> This buffer shall be returned to the SW, 972 ring 0 973 974 <enum 4 SW1_BM> This buffer shall be returned to the SW, 975 ring 1 976 977 <enum 5 SW2_BM> This buffer shall be returned to the SW, 978 ring 2 979 980 <enum 6 SW3_BM> This buffer shall be returned to the SW, 981 ring 3 982 983 <enum 7 SW4_BM> This buffer shall be returned to the SW, 984 ring 4 985 986 987 988 <legal all> 989 */ 990 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 991 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 992 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 993 994 /* Description RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 995 996 Cookie field exclusively used by SW. 997 998 999 1000 In case of 'NULL' pointer, this field is set to 0 1001 1002 1003 1004 HW ignores the contents, accept that it passes the 1005 programmed value on to other descriptors together with the 1006 physical address 1007 1008 1009 1010 Field can be used by SW to for example associate the 1011 buffers physical address with the virtual address 1012 1013 The bit definitions as used by SW are within SW HLD 1014 specification 1015 1016 1017 1018 NOTE1: 1019 1020 The three most significant bits can have a special 1021 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1022 STRUCT, and field transmit_bw_restriction is set 1023 1024 1025 1026 In case of NON punctured transmission: 1027 1028 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1029 1030 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1031 1032 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1033 1034 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1035 1036 1037 1038 In case of punctured transmission: 1039 1040 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1041 1042 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1043 1044 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1045 1046 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1047 1048 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1049 1050 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1051 1052 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1053 1054 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1055 1056 1057 1058 Note: a punctured transmission is indicated by the 1059 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1060 TLV 1061 1062 1063 1064 NOTE 2:The five most significant bits can have a special 1065 meaning in case this struct is embedded in an 1066 RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is 1067 configured for passing on the additional info 1068 from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV 1069 (FR56821). This is not supported in HastingsPrime, Pine or 1070 Moselle. 1071 1072 1073 1074 Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS 1075 control field 1076 1077 1078 1079 Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 1080 indicates MPDUs with a QoS control field. 1081 1082 1083 1084 1085 1086 <legal all> 1087 */ 1088 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000024 1089 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 1090 #define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 1091 1092 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_4 */ 1093 1094 1095 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 1096 1097 1098 /* Description RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 1099 1100 Address (lower 32 bits) of the MSDU buffer OR 1101 MSDU_EXTENSION descriptor OR Link Descriptor 1102 1103 1104 1105 In case of 'NULL' pointer, this field is set to 0 1106 1107 <legal all> 1108 */ 1109 #define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000028 1110 #define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1111 #define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1112 1113 /* Description RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 1114 1115 Address (upper 8 bits) of the MSDU buffer OR 1116 MSDU_EXTENSION descriptor OR Link Descriptor 1117 1118 1119 1120 In case of 'NULL' pointer, this field is set to 0 1121 1122 <legal all> 1123 */ 1124 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000002c 1125 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1126 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1127 1128 /* Description RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 1129 1130 Consumer: WBM 1131 1132 Producer: SW/FW 1133 1134 1135 1136 In case of 'NULL' pointer, this field is set to 0 1137 1138 1139 1140 Indicates to which buffer manager the buffer OR 1141 MSDU_EXTENSION descriptor OR link descriptor that is being 1142 pointed to shall be returned after the frame has been 1143 processed. It is used by WBM for routing purposes. 1144 1145 1146 1147 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1148 to the WMB buffer idle list 1149 1150 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1151 returned to the WMB idle link descriptor idle list 1152 1153 <enum 2 FW_BM> This buffer shall be returned to the FW 1154 1155 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1156 ring 0 1157 1158 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1159 ring 1 1160 1161 <enum 5 SW2_BM> This buffer shall be returned to the SW, 1162 ring 2 1163 1164 <enum 6 SW3_BM> This buffer shall be returned to the SW, 1165 ring 3 1166 1167 <enum 7 SW4_BM> This buffer shall be returned to the SW, 1168 ring 4 1169 1170 1171 1172 <legal all> 1173 */ 1174 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000002c 1175 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1176 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 1177 1178 /* Description RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 1179 1180 Cookie field exclusively used by SW. 1181 1182 1183 1184 In case of 'NULL' pointer, this field is set to 0 1185 1186 1187 1188 HW ignores the contents, accept that it passes the 1189 programmed value on to other descriptors together with the 1190 physical address 1191 1192 1193 1194 Field can be used by SW to for example associate the 1195 buffers physical address with the virtual address 1196 1197 The bit definitions as used by SW are within SW HLD 1198 specification 1199 1200 1201 1202 NOTE1: 1203 1204 The three most significant bits can have a special 1205 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1206 STRUCT, and field transmit_bw_restriction is set 1207 1208 1209 1210 In case of NON punctured transmission: 1211 1212 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1213 1214 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1215 1216 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1217 1218 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1219 1220 1221 1222 In case of punctured transmission: 1223 1224 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1225 1226 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1227 1228 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1229 1230 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1231 1232 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1233 1234 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1235 1236 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1237 1238 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1239 1240 1241 1242 Note: a punctured transmission is indicated by the 1243 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1244 TLV 1245 1246 1247 1248 NOTE 2:The five most significant bits can have a special 1249 meaning in case this struct is embedded in an 1250 RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is 1251 configured for passing on the additional info 1252 from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV 1253 (FR56821). This is not supported in HastingsPrime, Pine or 1254 Moselle. 1255 1256 1257 1258 Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS 1259 control field 1260 1261 1262 1263 Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 1264 indicates MPDUs with a QoS control field. 1265 1266 1267 1268 1269 1270 <legal all> 1271 */ 1272 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000002c 1273 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 1274 #define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 1275 1276 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_5 */ 1277 1278 1279 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 1280 1281 1282 /* Description RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 1283 1284 Address (lower 32 bits) of the MSDU buffer OR 1285 MSDU_EXTENSION descriptor OR Link Descriptor 1286 1287 1288 1289 In case of 'NULL' pointer, this field is set to 0 1290 1291 <legal all> 1292 */ 1293 #define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000030 1294 #define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1295 #define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1296 1297 /* Description RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 1298 1299 Address (upper 8 bits) of the MSDU buffer OR 1300 MSDU_EXTENSION descriptor OR Link Descriptor 1301 1302 1303 1304 In case of 'NULL' pointer, this field is set to 0 1305 1306 <legal all> 1307 */ 1308 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000034 1309 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1310 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1311 1312 /* Description RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 1313 1314 Consumer: WBM 1315 1316 Producer: SW/FW 1317 1318 1319 1320 In case of 'NULL' pointer, this field is set to 0 1321 1322 1323 1324 Indicates to which buffer manager the buffer OR 1325 MSDU_EXTENSION descriptor OR link descriptor that is being 1326 pointed to shall be returned after the frame has been 1327 processed. It is used by WBM for routing purposes. 1328 1329 1330 1331 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1332 to the WMB buffer idle list 1333 1334 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1335 returned to the WMB idle link descriptor idle list 1336 1337 <enum 2 FW_BM> This buffer shall be returned to the FW 1338 1339 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1340 ring 0 1341 1342 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1343 ring 1 1344 1345 <enum 5 SW2_BM> This buffer shall be returned to the SW, 1346 ring 2 1347 1348 <enum 6 SW3_BM> This buffer shall be returned to the SW, 1349 ring 3 1350 1351 <enum 7 SW4_BM> This buffer shall be returned to the SW, 1352 ring 4 1353 1354 1355 1356 <legal all> 1357 */ 1358 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 1359 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1360 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 1361 1362 /* Description RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 1363 1364 Cookie field exclusively used by SW. 1365 1366 1367 1368 In case of 'NULL' pointer, this field is set to 0 1369 1370 1371 1372 HW ignores the contents, accept that it passes the 1373 programmed value on to other descriptors together with the 1374 physical address 1375 1376 1377 1378 Field can be used by SW to for example associate the 1379 buffers physical address with the virtual address 1380 1381 The bit definitions as used by SW are within SW HLD 1382 specification 1383 1384 1385 1386 NOTE1: 1387 1388 The three most significant bits can have a special 1389 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1390 STRUCT, and field transmit_bw_restriction is set 1391 1392 1393 1394 In case of NON punctured transmission: 1395 1396 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1397 1398 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1399 1400 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1401 1402 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1403 1404 1405 1406 In case of punctured transmission: 1407 1408 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1409 1410 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1411 1412 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1413 1414 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1415 1416 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1417 1418 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1419 1420 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1421 1422 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1423 1424 1425 1426 Note: a punctured transmission is indicated by the 1427 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1428 TLV 1429 1430 1431 1432 NOTE 2:The five most significant bits can have a special 1433 meaning in case this struct is embedded in an 1434 RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is 1435 configured for passing on the additional info 1436 from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV 1437 (FR56821). This is not supported in HastingsPrime, Pine or 1438 Moselle. 1439 1440 1441 1442 Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS 1443 control field 1444 1445 1446 1447 Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 1448 indicates MPDUs with a QoS control field. 1449 1450 1451 1452 1453 1454 <legal all> 1455 */ 1456 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000034 1457 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 1458 #define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 1459 1460 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_6 */ 1461 1462 1463 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 1464 1465 1466 /* Description RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 1467 1468 Address (lower 32 bits) of the MSDU buffer OR 1469 MSDU_EXTENSION descriptor OR Link Descriptor 1470 1471 1472 1473 In case of 'NULL' pointer, this field is set to 0 1474 1475 <legal all> 1476 */ 1477 #define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000038 1478 #define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1479 #define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1480 1481 /* Description RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 1482 1483 Address (upper 8 bits) of the MSDU buffer OR 1484 MSDU_EXTENSION descriptor OR Link Descriptor 1485 1486 1487 1488 In case of 'NULL' pointer, this field is set to 0 1489 1490 <legal all> 1491 */ 1492 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000003c 1493 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1494 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1495 1496 /* Description RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 1497 1498 Consumer: WBM 1499 1500 Producer: SW/FW 1501 1502 1503 1504 In case of 'NULL' pointer, this field is set to 0 1505 1506 1507 1508 Indicates to which buffer manager the buffer OR 1509 MSDU_EXTENSION descriptor OR link descriptor that is being 1510 pointed to shall be returned after the frame has been 1511 processed. It is used by WBM for routing purposes. 1512 1513 1514 1515 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1516 to the WMB buffer idle list 1517 1518 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1519 returned to the WMB idle link descriptor idle list 1520 1521 <enum 2 FW_BM> This buffer shall be returned to the FW 1522 1523 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1524 ring 0 1525 1526 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1527 ring 1 1528 1529 <enum 5 SW2_BM> This buffer shall be returned to the SW, 1530 ring 2 1531 1532 <enum 6 SW3_BM> This buffer shall be returned to the SW, 1533 ring 3 1534 1535 <enum 7 SW4_BM> This buffer shall be returned to the SW, 1536 ring 4 1537 1538 1539 1540 <legal all> 1541 */ 1542 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000003c 1543 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1544 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 1545 1546 /* Description RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 1547 1548 Cookie field exclusively used by SW. 1549 1550 1551 1552 In case of 'NULL' pointer, this field is set to 0 1553 1554 1555 1556 HW ignores the contents, accept that it passes the 1557 programmed value on to other descriptors together with the 1558 physical address 1559 1560 1561 1562 Field can be used by SW to for example associate the 1563 buffers physical address with the virtual address 1564 1565 The bit definitions as used by SW are within SW HLD 1566 specification 1567 1568 1569 1570 NOTE1: 1571 1572 The three most significant bits can have a special 1573 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1574 STRUCT, and field transmit_bw_restriction is set 1575 1576 1577 1578 In case of NON punctured transmission: 1579 1580 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1581 1582 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1583 1584 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1585 1586 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1587 1588 1589 1590 In case of punctured transmission: 1591 1592 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1593 1594 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1595 1596 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1597 1598 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1599 1600 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1601 1602 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1603 1604 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1605 1606 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1607 1608 1609 1610 Note: a punctured transmission is indicated by the 1611 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1612 TLV 1613 1614 1615 1616 NOTE 2:The five most significant bits can have a special 1617 meaning in case this struct is embedded in an 1618 RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is 1619 configured for passing on the additional info 1620 from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV 1621 (FR56821). This is not supported in HastingsPrime, Pine or 1622 Moselle. 1623 1624 1625 1626 Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS 1627 control field 1628 1629 1630 1631 Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 1632 indicates MPDUs with a QoS control field. 1633 1634 1635 1636 1637 1638 <legal all> 1639 */ 1640 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000003c 1641 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 1642 #define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 1643 1644 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_7 */ 1645 1646 1647 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 1648 1649 1650 /* Description RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 1651 1652 Address (lower 32 bits) of the MSDU buffer OR 1653 MSDU_EXTENSION descriptor OR Link Descriptor 1654 1655 1656 1657 In case of 'NULL' pointer, this field is set to 0 1658 1659 <legal all> 1660 */ 1661 #define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000040 1662 #define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1663 #define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1664 1665 /* Description RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 1666 1667 Address (upper 8 bits) of the MSDU buffer OR 1668 MSDU_EXTENSION descriptor OR Link Descriptor 1669 1670 1671 1672 In case of 'NULL' pointer, this field is set to 0 1673 1674 <legal all> 1675 */ 1676 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000044 1677 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1678 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1679 1680 /* Description RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 1681 1682 Consumer: WBM 1683 1684 Producer: SW/FW 1685 1686 1687 1688 In case of 'NULL' pointer, this field is set to 0 1689 1690 1691 1692 Indicates to which buffer manager the buffer OR 1693 MSDU_EXTENSION descriptor OR link descriptor that is being 1694 pointed to shall be returned after the frame has been 1695 processed. It is used by WBM for routing purposes. 1696 1697 1698 1699 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1700 to the WMB buffer idle list 1701 1702 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1703 returned to the WMB idle link descriptor idle list 1704 1705 <enum 2 FW_BM> This buffer shall be returned to the FW 1706 1707 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1708 ring 0 1709 1710 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1711 ring 1 1712 1713 <enum 5 SW2_BM> This buffer shall be returned to the SW, 1714 ring 2 1715 1716 <enum 6 SW3_BM> This buffer shall be returned to the SW, 1717 ring 3 1718 1719 <enum 7 SW4_BM> This buffer shall be returned to the SW, 1720 ring 4 1721 1722 1723 1724 <legal all> 1725 */ 1726 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 1727 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1728 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 1729 1730 /* Description RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 1731 1732 Cookie field exclusively used by SW. 1733 1734 1735 1736 In case of 'NULL' pointer, this field is set to 0 1737 1738 1739 1740 HW ignores the contents, accept that it passes the 1741 programmed value on to other descriptors together with the 1742 physical address 1743 1744 1745 1746 Field can be used by SW to for example associate the 1747 buffers physical address with the virtual address 1748 1749 The bit definitions as used by SW are within SW HLD 1750 specification 1751 1752 1753 1754 NOTE1: 1755 1756 The three most significant bits can have a special 1757 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1758 STRUCT, and field transmit_bw_restriction is set 1759 1760 1761 1762 In case of NON punctured transmission: 1763 1764 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1765 1766 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1767 1768 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1769 1770 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1771 1772 1773 1774 In case of punctured transmission: 1775 1776 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1777 1778 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1779 1780 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1781 1782 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1783 1784 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1785 1786 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1787 1788 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1789 1790 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1791 1792 1793 1794 Note: a punctured transmission is indicated by the 1795 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1796 TLV 1797 1798 1799 1800 NOTE 2:The five most significant bits can have a special 1801 meaning in case this struct is embedded in an 1802 RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is 1803 configured for passing on the additional info 1804 from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV 1805 (FR56821). This is not supported in HastingsPrime, Pine or 1806 Moselle. 1807 1808 1809 1810 Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS 1811 control field 1812 1813 1814 1815 Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 1816 indicates MPDUs with a QoS control field. 1817 1818 1819 1820 1821 1822 <legal all> 1823 */ 1824 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000044 1825 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 1826 #define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 1827 1828 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_8 */ 1829 1830 1831 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 1832 1833 1834 /* Description RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 1835 1836 Address (lower 32 bits) of the MSDU buffer OR 1837 MSDU_EXTENSION descriptor OR Link Descriptor 1838 1839 1840 1841 In case of 'NULL' pointer, this field is set to 0 1842 1843 <legal all> 1844 */ 1845 #define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000048 1846 #define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 1847 #define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 1848 1849 /* Description RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 1850 1851 Address (upper 8 bits) of the MSDU buffer OR 1852 MSDU_EXTENSION descriptor OR Link Descriptor 1853 1854 1855 1856 In case of 'NULL' pointer, this field is set to 0 1857 1858 <legal all> 1859 */ 1860 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000004c 1861 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 1862 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 1863 1864 /* Description RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 1865 1866 Consumer: WBM 1867 1868 Producer: SW/FW 1869 1870 1871 1872 In case of 'NULL' pointer, this field is set to 0 1873 1874 1875 1876 Indicates to which buffer manager the buffer OR 1877 MSDU_EXTENSION descriptor OR link descriptor that is being 1878 pointed to shall be returned after the frame has been 1879 processed. It is used by WBM for routing purposes. 1880 1881 1882 1883 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 1884 to the WMB buffer idle list 1885 1886 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 1887 returned to the WMB idle link descriptor idle list 1888 1889 <enum 2 FW_BM> This buffer shall be returned to the FW 1890 1891 <enum 3 SW0_BM> This buffer shall be returned to the SW, 1892 ring 0 1893 1894 <enum 4 SW1_BM> This buffer shall be returned to the SW, 1895 ring 1 1896 1897 <enum 5 SW2_BM> This buffer shall be returned to the SW, 1898 ring 2 1899 1900 <enum 6 SW3_BM> This buffer shall be returned to the SW, 1901 ring 3 1902 1903 <enum 7 SW4_BM> This buffer shall be returned to the SW, 1904 ring 4 1905 1906 1907 1908 <legal all> 1909 */ 1910 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000004c 1911 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 1912 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 1913 1914 /* Description RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 1915 1916 Cookie field exclusively used by SW. 1917 1918 1919 1920 In case of 'NULL' pointer, this field is set to 0 1921 1922 1923 1924 HW ignores the contents, accept that it passes the 1925 programmed value on to other descriptors together with the 1926 physical address 1927 1928 1929 1930 Field can be used by SW to for example associate the 1931 buffers physical address with the virtual address 1932 1933 The bit definitions as used by SW are within SW HLD 1934 specification 1935 1936 1937 1938 NOTE1: 1939 1940 The three most significant bits can have a special 1941 meaning in case this struct is embedded in a TX_MPDU_DETAILS 1942 STRUCT, and field transmit_bw_restriction is set 1943 1944 1945 1946 In case of NON punctured transmission: 1947 1948 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 1949 1950 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 1951 1952 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 1953 1954 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 1955 1956 1957 1958 In case of punctured transmission: 1959 1960 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 1961 1962 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 1963 1964 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 1965 1966 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 1967 1968 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 1969 1970 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 1971 1972 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 1973 1974 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 1975 1976 1977 1978 Note: a punctured transmission is indicated by the 1979 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 1980 TLV 1981 1982 1983 1984 NOTE 2:The five most significant bits can have a special 1985 meaning in case this struct is embedded in an 1986 RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is 1987 configured for passing on the additional info 1988 from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV 1989 (FR56821). This is not supported in HastingsPrime, Pine or 1990 Moselle. 1991 1992 1993 1994 Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS 1995 control field 1996 1997 1998 1999 Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 2000 indicates MPDUs with a QoS control field. 2001 2002 2003 2004 2005 2006 <legal all> 2007 */ 2008 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000004c 2009 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 2010 #define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 2011 2012 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_9 */ 2013 2014 2015 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 2016 2017 2018 /* Description RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 2019 2020 Address (lower 32 bits) of the MSDU buffer OR 2021 MSDU_EXTENSION descriptor OR Link Descriptor 2022 2023 2024 2025 In case of 'NULL' pointer, this field is set to 0 2026 2027 <legal all> 2028 */ 2029 #define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000050 2030 #define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2031 #define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2032 2033 /* Description RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 2034 2035 Address (upper 8 bits) of the MSDU buffer OR 2036 MSDU_EXTENSION descriptor OR Link Descriptor 2037 2038 2039 2040 In case of 'NULL' pointer, this field is set to 0 2041 2042 <legal all> 2043 */ 2044 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000054 2045 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2046 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2047 2048 /* Description RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 2049 2050 Consumer: WBM 2051 2052 Producer: SW/FW 2053 2054 2055 2056 In case of 'NULL' pointer, this field is set to 0 2057 2058 2059 2060 Indicates to which buffer manager the buffer OR 2061 MSDU_EXTENSION descriptor OR link descriptor that is being 2062 pointed to shall be returned after the frame has been 2063 processed. It is used by WBM for routing purposes. 2064 2065 2066 2067 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2068 to the WMB buffer idle list 2069 2070 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 2071 returned to the WMB idle link descriptor idle list 2072 2073 <enum 2 FW_BM> This buffer shall be returned to the FW 2074 2075 <enum 3 SW0_BM> This buffer shall be returned to the SW, 2076 ring 0 2077 2078 <enum 4 SW1_BM> This buffer shall be returned to the SW, 2079 ring 1 2080 2081 <enum 5 SW2_BM> This buffer shall be returned to the SW, 2082 ring 2 2083 2084 <enum 6 SW3_BM> This buffer shall be returned to the SW, 2085 ring 3 2086 2087 <enum 7 SW4_BM> This buffer shall be returned to the SW, 2088 ring 4 2089 2090 2091 2092 <legal all> 2093 */ 2094 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 2095 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2096 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 2097 2098 /* Description RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 2099 2100 Cookie field exclusively used by SW. 2101 2102 2103 2104 In case of 'NULL' pointer, this field is set to 0 2105 2106 2107 2108 HW ignores the contents, accept that it passes the 2109 programmed value on to other descriptors together with the 2110 physical address 2111 2112 2113 2114 Field can be used by SW to for example associate the 2115 buffers physical address with the virtual address 2116 2117 The bit definitions as used by SW are within SW HLD 2118 specification 2119 2120 2121 2122 NOTE1: 2123 2124 The three most significant bits can have a special 2125 meaning in case this struct is embedded in a TX_MPDU_DETAILS 2126 STRUCT, and field transmit_bw_restriction is set 2127 2128 2129 2130 In case of NON punctured transmission: 2131 2132 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 2133 2134 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 2135 2136 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 2137 2138 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 2139 2140 2141 2142 In case of punctured transmission: 2143 2144 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 2145 2146 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 2147 2148 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 2149 2150 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 2151 2152 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 2153 2154 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 2155 2156 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 2157 2158 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 2159 2160 2161 2162 Note: a punctured transmission is indicated by the 2163 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 2164 TLV 2165 2166 2167 2168 NOTE 2:The five most significant bits can have a special 2169 meaning in case this struct is embedded in an 2170 RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is 2171 configured for passing on the additional info 2172 from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV 2173 (FR56821). This is not supported in HastingsPrime, Pine or 2174 Moselle. 2175 2176 2177 2178 Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS 2179 control field 2180 2181 2182 2183 Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 2184 indicates MPDUs with a QoS control field. 2185 2186 2187 2188 2189 2190 <legal all> 2191 */ 2192 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000054 2193 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 2194 #define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 2195 2196 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_10 */ 2197 2198 2199 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 2200 2201 2202 /* Description RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 2203 2204 Address (lower 32 bits) of the MSDU buffer OR 2205 MSDU_EXTENSION descriptor OR Link Descriptor 2206 2207 2208 2209 In case of 'NULL' pointer, this field is set to 0 2210 2211 <legal all> 2212 */ 2213 #define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000058 2214 #define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2215 #define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2216 2217 /* Description RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 2218 2219 Address (upper 8 bits) of the MSDU buffer OR 2220 MSDU_EXTENSION descriptor OR Link Descriptor 2221 2222 2223 2224 In case of 'NULL' pointer, this field is set to 0 2225 2226 <legal all> 2227 */ 2228 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000005c 2229 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2230 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2231 2232 /* Description RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 2233 2234 Consumer: WBM 2235 2236 Producer: SW/FW 2237 2238 2239 2240 In case of 'NULL' pointer, this field is set to 0 2241 2242 2243 2244 Indicates to which buffer manager the buffer OR 2245 MSDU_EXTENSION descriptor OR link descriptor that is being 2246 pointed to shall be returned after the frame has been 2247 processed. It is used by WBM for routing purposes. 2248 2249 2250 2251 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2252 to the WMB buffer idle list 2253 2254 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 2255 returned to the WMB idle link descriptor idle list 2256 2257 <enum 2 FW_BM> This buffer shall be returned to the FW 2258 2259 <enum 3 SW0_BM> This buffer shall be returned to the SW, 2260 ring 0 2261 2262 <enum 4 SW1_BM> This buffer shall be returned to the SW, 2263 ring 1 2264 2265 <enum 5 SW2_BM> This buffer shall be returned to the SW, 2266 ring 2 2267 2268 <enum 6 SW3_BM> This buffer shall be returned to the SW, 2269 ring 3 2270 2271 <enum 7 SW4_BM> This buffer shall be returned to the SW, 2272 ring 4 2273 2274 2275 2276 <legal all> 2277 */ 2278 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000005c 2279 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2280 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 2281 2282 /* Description RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 2283 2284 Cookie field exclusively used by SW. 2285 2286 2287 2288 In case of 'NULL' pointer, this field is set to 0 2289 2290 2291 2292 HW ignores the contents, accept that it passes the 2293 programmed value on to other descriptors together with the 2294 physical address 2295 2296 2297 2298 Field can be used by SW to for example associate the 2299 buffers physical address with the virtual address 2300 2301 The bit definitions as used by SW are within SW HLD 2302 specification 2303 2304 2305 2306 NOTE1: 2307 2308 The three most significant bits can have a special 2309 meaning in case this struct is embedded in a TX_MPDU_DETAILS 2310 STRUCT, and field transmit_bw_restriction is set 2311 2312 2313 2314 In case of NON punctured transmission: 2315 2316 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 2317 2318 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 2319 2320 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 2321 2322 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 2323 2324 2325 2326 In case of punctured transmission: 2327 2328 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 2329 2330 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 2331 2332 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 2333 2334 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 2335 2336 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 2337 2338 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 2339 2340 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 2341 2342 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 2343 2344 2345 2346 Note: a punctured transmission is indicated by the 2347 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 2348 TLV 2349 2350 2351 2352 NOTE 2:The five most significant bits can have a special 2353 meaning in case this struct is embedded in an 2354 RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is 2355 configured for passing on the additional info 2356 from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV 2357 (FR56821). This is not supported in HastingsPrime, Pine or 2358 Moselle. 2359 2360 2361 2362 Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS 2363 control field 2364 2365 2366 2367 Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 2368 indicates MPDUs with a QoS control field. 2369 2370 2371 2372 2373 2374 <legal all> 2375 */ 2376 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000005c 2377 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 2378 #define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 2379 2380 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_11 */ 2381 2382 2383 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 2384 2385 2386 /* Description RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 2387 2388 Address (lower 32 bits) of the MSDU buffer OR 2389 MSDU_EXTENSION descriptor OR Link Descriptor 2390 2391 2392 2393 In case of 'NULL' pointer, this field is set to 0 2394 2395 <legal all> 2396 */ 2397 #define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000060 2398 #define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2399 #define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2400 2401 /* Description RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 2402 2403 Address (upper 8 bits) of the MSDU buffer OR 2404 MSDU_EXTENSION descriptor OR Link Descriptor 2405 2406 2407 2408 In case of 'NULL' pointer, this field is set to 0 2409 2410 <legal all> 2411 */ 2412 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000064 2413 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2414 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2415 2416 /* Description RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 2417 2418 Consumer: WBM 2419 2420 Producer: SW/FW 2421 2422 2423 2424 In case of 'NULL' pointer, this field is set to 0 2425 2426 2427 2428 Indicates to which buffer manager the buffer OR 2429 MSDU_EXTENSION descriptor OR link descriptor that is being 2430 pointed to shall be returned after the frame has been 2431 processed. It is used by WBM for routing purposes. 2432 2433 2434 2435 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2436 to the WMB buffer idle list 2437 2438 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 2439 returned to the WMB idle link descriptor idle list 2440 2441 <enum 2 FW_BM> This buffer shall be returned to the FW 2442 2443 <enum 3 SW0_BM> This buffer shall be returned to the SW, 2444 ring 0 2445 2446 <enum 4 SW1_BM> This buffer shall be returned to the SW, 2447 ring 1 2448 2449 <enum 5 SW2_BM> This buffer shall be returned to the SW, 2450 ring 2 2451 2452 <enum 6 SW3_BM> This buffer shall be returned to the SW, 2453 ring 3 2454 2455 <enum 7 SW4_BM> This buffer shall be returned to the SW, 2456 ring 4 2457 2458 2459 2460 <legal all> 2461 */ 2462 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 2463 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2464 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 2465 2466 /* Description RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 2467 2468 Cookie field exclusively used by SW. 2469 2470 2471 2472 In case of 'NULL' pointer, this field is set to 0 2473 2474 2475 2476 HW ignores the contents, accept that it passes the 2477 programmed value on to other descriptors together with the 2478 physical address 2479 2480 2481 2482 Field can be used by SW to for example associate the 2483 buffers physical address with the virtual address 2484 2485 The bit definitions as used by SW are within SW HLD 2486 specification 2487 2488 2489 2490 NOTE1: 2491 2492 The three most significant bits can have a special 2493 meaning in case this struct is embedded in a TX_MPDU_DETAILS 2494 STRUCT, and field transmit_bw_restriction is set 2495 2496 2497 2498 In case of NON punctured transmission: 2499 2500 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 2501 2502 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 2503 2504 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 2505 2506 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 2507 2508 2509 2510 In case of punctured transmission: 2511 2512 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 2513 2514 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 2515 2516 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 2517 2518 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 2519 2520 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 2521 2522 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 2523 2524 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 2525 2526 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 2527 2528 2529 2530 Note: a punctured transmission is indicated by the 2531 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 2532 TLV 2533 2534 2535 2536 NOTE 2:The five most significant bits can have a special 2537 meaning in case this struct is embedded in an 2538 RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is 2539 configured for passing on the additional info 2540 from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV 2541 (FR56821). This is not supported in HastingsPrime, Pine or 2542 Moselle. 2543 2544 2545 2546 Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS 2547 control field 2548 2549 2550 2551 Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 2552 indicates MPDUs with a QoS control field. 2553 2554 2555 2556 2557 2558 <legal all> 2559 */ 2560 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000064 2561 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 2562 #define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 2563 2564 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_12 */ 2565 2566 2567 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 2568 2569 2570 /* Description RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 2571 2572 Address (lower 32 bits) of the MSDU buffer OR 2573 MSDU_EXTENSION descriptor OR Link Descriptor 2574 2575 2576 2577 In case of 'NULL' pointer, this field is set to 0 2578 2579 <legal all> 2580 */ 2581 #define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000068 2582 #define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2583 #define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2584 2585 /* Description RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 2586 2587 Address (upper 8 bits) of the MSDU buffer OR 2588 MSDU_EXTENSION descriptor OR Link Descriptor 2589 2590 2591 2592 In case of 'NULL' pointer, this field is set to 0 2593 2594 <legal all> 2595 */ 2596 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000006c 2597 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2598 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2599 2600 /* Description RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 2601 2602 Consumer: WBM 2603 2604 Producer: SW/FW 2605 2606 2607 2608 In case of 'NULL' pointer, this field is set to 0 2609 2610 2611 2612 Indicates to which buffer manager the buffer OR 2613 MSDU_EXTENSION descriptor OR link descriptor that is being 2614 pointed to shall be returned after the frame has been 2615 processed. It is used by WBM for routing purposes. 2616 2617 2618 2619 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2620 to the WMB buffer idle list 2621 2622 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 2623 returned to the WMB idle link descriptor idle list 2624 2625 <enum 2 FW_BM> This buffer shall be returned to the FW 2626 2627 <enum 3 SW0_BM> This buffer shall be returned to the SW, 2628 ring 0 2629 2630 <enum 4 SW1_BM> This buffer shall be returned to the SW, 2631 ring 1 2632 2633 <enum 5 SW2_BM> This buffer shall be returned to the SW, 2634 ring 2 2635 2636 <enum 6 SW3_BM> This buffer shall be returned to the SW, 2637 ring 3 2638 2639 <enum 7 SW4_BM> This buffer shall be returned to the SW, 2640 ring 4 2641 2642 2643 2644 <legal all> 2645 */ 2646 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000006c 2647 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2648 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 2649 2650 /* Description RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 2651 2652 Cookie field exclusively used by SW. 2653 2654 2655 2656 In case of 'NULL' pointer, this field is set to 0 2657 2658 2659 2660 HW ignores the contents, accept that it passes the 2661 programmed value on to other descriptors together with the 2662 physical address 2663 2664 2665 2666 Field can be used by SW to for example associate the 2667 buffers physical address with the virtual address 2668 2669 The bit definitions as used by SW are within SW HLD 2670 specification 2671 2672 2673 2674 NOTE1: 2675 2676 The three most significant bits can have a special 2677 meaning in case this struct is embedded in a TX_MPDU_DETAILS 2678 STRUCT, and field transmit_bw_restriction is set 2679 2680 2681 2682 In case of NON punctured transmission: 2683 2684 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 2685 2686 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 2687 2688 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 2689 2690 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 2691 2692 2693 2694 In case of punctured transmission: 2695 2696 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 2697 2698 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 2699 2700 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 2701 2702 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 2703 2704 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 2705 2706 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 2707 2708 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 2709 2710 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 2711 2712 2713 2714 Note: a punctured transmission is indicated by the 2715 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 2716 TLV 2717 2718 2719 2720 NOTE 2:The five most significant bits can have a special 2721 meaning in case this struct is embedded in an 2722 RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is 2723 configured for passing on the additional info 2724 from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV 2725 (FR56821). This is not supported in HastingsPrime, Pine or 2726 Moselle. 2727 2728 2729 2730 Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS 2731 control field 2732 2733 2734 2735 Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 2736 indicates MPDUs with a QoS control field. 2737 2738 2739 2740 2741 2742 <legal all> 2743 */ 2744 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000006c 2745 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 2746 #define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 2747 2748 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_13 */ 2749 2750 2751 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 2752 2753 2754 /* Description RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 2755 2756 Address (lower 32 bits) of the MSDU buffer OR 2757 MSDU_EXTENSION descriptor OR Link Descriptor 2758 2759 2760 2761 In case of 'NULL' pointer, this field is set to 0 2762 2763 <legal all> 2764 */ 2765 #define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000070 2766 #define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2767 #define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2768 2769 /* Description RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 2770 2771 Address (upper 8 bits) of the MSDU buffer OR 2772 MSDU_EXTENSION descriptor OR Link Descriptor 2773 2774 2775 2776 In case of 'NULL' pointer, this field is set to 0 2777 2778 <legal all> 2779 */ 2780 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000074 2781 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2782 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2783 2784 /* Description RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 2785 2786 Consumer: WBM 2787 2788 Producer: SW/FW 2789 2790 2791 2792 In case of 'NULL' pointer, this field is set to 0 2793 2794 2795 2796 Indicates to which buffer manager the buffer OR 2797 MSDU_EXTENSION descriptor OR link descriptor that is being 2798 pointed to shall be returned after the frame has been 2799 processed. It is used by WBM for routing purposes. 2800 2801 2802 2803 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2804 to the WMB buffer idle list 2805 2806 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 2807 returned to the WMB idle link descriptor idle list 2808 2809 <enum 2 FW_BM> This buffer shall be returned to the FW 2810 2811 <enum 3 SW0_BM> This buffer shall be returned to the SW, 2812 ring 0 2813 2814 <enum 4 SW1_BM> This buffer shall be returned to the SW, 2815 ring 1 2816 2817 <enum 5 SW2_BM> This buffer shall be returned to the SW, 2818 ring 2 2819 2820 <enum 6 SW3_BM> This buffer shall be returned to the SW, 2821 ring 3 2822 2823 <enum 7 SW4_BM> This buffer shall be returned to the SW, 2824 ring 4 2825 2826 2827 2828 <legal all> 2829 */ 2830 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 2831 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 2832 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 2833 2834 /* Description RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 2835 2836 Cookie field exclusively used by SW. 2837 2838 2839 2840 In case of 'NULL' pointer, this field is set to 0 2841 2842 2843 2844 HW ignores the contents, accept that it passes the 2845 programmed value on to other descriptors together with the 2846 physical address 2847 2848 2849 2850 Field can be used by SW to for example associate the 2851 buffers physical address with the virtual address 2852 2853 The bit definitions as used by SW are within SW HLD 2854 specification 2855 2856 2857 2858 NOTE1: 2859 2860 The three most significant bits can have a special 2861 meaning in case this struct is embedded in a TX_MPDU_DETAILS 2862 STRUCT, and field transmit_bw_restriction is set 2863 2864 2865 2866 In case of NON punctured transmission: 2867 2868 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 2869 2870 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 2871 2872 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 2873 2874 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 2875 2876 2877 2878 In case of punctured transmission: 2879 2880 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 2881 2882 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 2883 2884 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 2885 2886 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 2887 2888 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 2889 2890 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 2891 2892 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 2893 2894 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 2895 2896 2897 2898 Note: a punctured transmission is indicated by the 2899 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 2900 TLV 2901 2902 2903 2904 NOTE 2:The five most significant bits can have a special 2905 meaning in case this struct is embedded in an 2906 RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is 2907 configured for passing on the additional info 2908 from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV 2909 (FR56821). This is not supported in HastingsPrime, Pine or 2910 Moselle. 2911 2912 2913 2914 Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS 2915 control field 2916 2917 2918 2919 Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 2920 indicates MPDUs with a QoS control field. 2921 2922 2923 2924 2925 2926 <legal all> 2927 */ 2928 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000074 2929 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 2930 #define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 2931 2932 /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_14 */ 2933 2934 2935 /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ 2936 2937 2938 /* Description RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 2939 2940 Address (lower 32 bits) of the MSDU buffer OR 2941 MSDU_EXTENSION descriptor OR Link Descriptor 2942 2943 2944 2945 In case of 'NULL' pointer, this field is set to 0 2946 2947 <legal all> 2948 */ 2949 #define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000078 2950 #define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 2951 #define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff 2952 2953 /* Description RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 2954 2955 Address (upper 8 bits) of the MSDU buffer OR 2956 MSDU_EXTENSION descriptor OR Link Descriptor 2957 2958 2959 2960 In case of 'NULL' pointer, this field is set to 0 2961 2962 <legal all> 2963 */ 2964 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000007c 2965 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 2966 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff 2967 2968 /* Description RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER 2969 2970 Consumer: WBM 2971 2972 Producer: SW/FW 2973 2974 2975 2976 In case of 'NULL' pointer, this field is set to 0 2977 2978 2979 2980 Indicates to which buffer manager the buffer OR 2981 MSDU_EXTENSION descriptor OR link descriptor that is being 2982 pointed to shall be returned after the frame has been 2983 processed. It is used by WBM for routing purposes. 2984 2985 2986 2987 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 2988 to the WMB buffer idle list 2989 2990 <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be 2991 returned to the WMB idle link descriptor idle list 2992 2993 <enum 2 FW_BM> This buffer shall be returned to the FW 2994 2995 <enum 3 SW0_BM> This buffer shall be returned to the SW, 2996 ring 0 2997 2998 <enum 4 SW1_BM> This buffer shall be returned to the SW, 2999 ring 1 3000 3001 <enum 5 SW2_BM> This buffer shall be returned to the SW, 3002 ring 2 3003 3004 <enum 6 SW3_BM> This buffer shall be returned to the SW, 3005 ring 3 3006 3007 <enum 7 SW4_BM> This buffer shall be returned to the SW, 3008 ring 4 3009 3010 3011 3012 <legal all> 3013 */ 3014 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000007c 3015 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 3016 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 3017 3018 /* Description RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE 3019 3020 Cookie field exclusively used by SW. 3021 3022 3023 3024 In case of 'NULL' pointer, this field is set to 0 3025 3026 3027 3028 HW ignores the contents, accept that it passes the 3029 programmed value on to other descriptors together with the 3030 physical address 3031 3032 3033 3034 Field can be used by SW to for example associate the 3035 buffers physical address with the virtual address 3036 3037 The bit definitions as used by SW are within SW HLD 3038 specification 3039 3040 3041 3042 NOTE1: 3043 3044 The three most significant bits can have a special 3045 meaning in case this struct is embedded in a TX_MPDU_DETAILS 3046 STRUCT, and field transmit_bw_restriction is set 3047 3048 3049 3050 In case of NON punctured transmission: 3051 3052 Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only 3053 3054 Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only 3055 3056 Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only 3057 3058 Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only 3059 3060 3061 3062 In case of punctured transmission: 3063 3064 Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only 3065 3066 Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only 3067 3068 Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only 3069 3070 Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only 3071 3072 Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only 3073 3074 Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only 3075 3076 Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only 3077 3078 Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only 3079 3080 3081 3082 Note: a punctured transmission is indicated by the 3083 presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler 3084 TLV 3085 3086 3087 3088 NOTE 2:The five most significant bits can have a special 3089 meaning in case this struct is embedded in an 3090 RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is 3091 configured for passing on the additional info 3092 from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV 3093 (FR56821). This is not supported in HastingsPrime, Pine or 3094 Moselle. 3095 3096 3097 3098 Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS 3099 control field 3100 3101 3102 3103 Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 3104 indicates MPDUs with a QoS control field. 3105 3106 3107 3108 3109 3110 <legal all> 3111 */ 3112 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000007c 3113 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 3114 #define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 3115 3116 3117 #endif // _RX_REO_QUEUE_EXT_H_ 3118