1 /* 2 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef __WCSS_SEQ_BASE_H__ 18 #define __WCSS_SEQ_BASE_H__ 19 20 #ifdef SCALE_INCLUDES 21 #include "HALhwio.h" 22 #else 23 #include "msmhwio.h" 24 #endif 25 26 27 /////////////////////////////////////////////////////////////////////////////////////////////// 28 // Instance Relative Offsets from Block wcss 29 /////////////////////////////////////////////////////////////////////////////////////////////// 30 31 #define SEQ_WCSS_UMAC_NOC_OFFSET 0x00140000 32 #define SEQ_WCSS_PHYA_OFFSET 0x00300000 33 #define SEQ_WCSS_PHYA_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00300000 34 #define SEQ_WCSS_PHYA_WFAX_PCSS_REG_MAP_OFFSET 0x00380000 35 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00380400 36 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00380800 37 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00380c00 38 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00381000 39 #define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00381400 40 #define SEQ_WCSS_PHYA_WFAX_PCSS_DUAL_TIMER_REG_MAP_OFFSET 0x00381800 41 #define SEQ_WCSS_PHYA_WFAX_PCSS_WATCHDOG_REG_MAP_OFFSET 0x00381c00 42 #define SEQ_WCSS_PHYA_WFAX_PCSS_XDMAC5_REG_MAP_OFFSET 0x00382c00 43 #define SEQ_WCSS_PHYA_WFAX_PCSS_XDMAC6_REG_MAP_OFFSET 0x00383000 44 #define SEQ_WCSS_PHYA_WFAX_NOC_REG_MAP_OFFSET 0x00388000 45 #define SEQ_WCSS_PHYA_WFAX_TXFD_REG_MAP_OFFSET 0x00390000 46 #define SEQ_WCSS_PHYA_WFAX_RXTD_REG_MAP_OFFSET 0x003a0000 47 #define SEQ_WCSS_PHYA_WFAX_TXTD_REG_MAP_OFFSET 0x003b0000 48 #define SEQ_WCSS_PHYA_WFAX_TXBF_REG_MAP_OFFSET 0x003c0000 49 #define SEQ_WCSS_PHYA_WFAX_DEMFRONT_0_REG_MAP_OFFSET 0x00400000 50 #define SEQ_WCSS_PHYA_WFAX_PHYRF_REG_MAP_OFFSET 0x00480000 51 #define SEQ_WCSS_PHYA_WFAX_ROBE_REG_MAP_OFFSET 0x004b0000 52 #define SEQ_WCSS_PHYA_WFAX_DEMFRONT_1_REG_MAP_OFFSET 0x00500000 53 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_OFFSET 0x005c0000 54 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x005d4000 55 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x005d4000 56 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_XFEM_OFFSET 0x005d4240 57 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET 0x005d42c0 58 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x005d4300 59 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x005d4400 60 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET 0x005d4480 61 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x005d4800 62 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x005d6000 63 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x005d6040 64 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x005d6100 65 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x005d6140 66 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x005d6180 67 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x005d61c0 68 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x005d6280 69 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x005d7c00 70 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_PMU_OFFSET 0x005da000 71 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_PMU_PMU_OFFSET 0x005da000 72 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x005e0000 73 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x005e0000 74 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x005e0400 75 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x005e0800 76 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH0_OFFSET 0x005e1000 77 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH0_OFFSET 0x005e1300 78 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x005e1600 79 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_CH0_OFFSET 0x005e1640 80 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x005e2000 81 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH0_OFFSET 0x005e4000 82 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x005e8000 83 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x005e8400 84 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x005e8800 85 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH1_OFFSET 0x005e9000 86 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH1_OFFSET 0x005e9300 87 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x005e9600 88 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_CH1_OFFSET 0x005e9640 89 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x005ea000 90 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH1_OFFSET 0x005ec000 91 #define SEQ_WCSS_UMAC_OFFSET 0x00a00000 92 #define SEQ_WCSS_UMAC_CXC_TOP_REG_OFFSET 0x00a20000 93 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00a20000 94 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00a22000 95 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00a24000 96 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00a26000 97 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00a28000 98 #define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x00a2a000 99 #define SEQ_WCSS_UMAC_MAC_TRACER_REG_OFFSET 0x00a30000 100 #define SEQ_WCSS_UMAC_WBM_REG_OFFSET 0x00a34000 101 #define SEQ_WCSS_UMAC_REO_REG_OFFSET 0x00a38000 102 #define SEQ_WCSS_UMAC_TQM_REG_OFFSET 0x00a3c000 103 #define SEQ_WCSS_UMAC_MAC_UMCMN_REG_OFFSET 0x00a40000 104 #define SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET 0x00a44000 105 #define SEQ_WCSS_UMAC_MAC_CMN_PARSER_REG_OFFSET 0x00a47000 106 #define SEQ_WCSS_WMAC0_OFFSET 0x00a80000 107 #define SEQ_WCSS_WMAC0_MAC_PDG_REG_OFFSET 0x00a80000 108 #define SEQ_WCSS_WMAC0_MAC_TXDMA_REG_OFFSET 0x00a83000 109 #define SEQ_WCSS_WMAC0_MAC_RXDMA_REG_OFFSET 0x00a86000 110 #define SEQ_WCSS_WMAC0_MAC_MCMN_REG_OFFSET 0x00a89000 111 #define SEQ_WCSS_WMAC0_MAC_RXPCU_REG_OFFSET 0x00a8c000 112 #define SEQ_WCSS_WMAC0_MAC_TXPCU_REG_OFFSET 0x00a8f000 113 #define SEQ_WCSS_WMAC0_MAC_AMPI_REG_OFFSET 0x00a92000 114 #define SEQ_WCSS_WMAC0_MAC_RXOLE_REG_OFFSET 0x00a95000 115 #define SEQ_WCSS_WMAC0_MAC_RXOLE_PARSER_REG_OFFSET 0x00a98000 116 #define SEQ_WCSS_WMAC0_MAC_CCE_REG_OFFSET 0x00a9b000 117 #define SEQ_WCSS_WMAC0_MAC_TXOLE_REG_OFFSET 0x00a9e000 118 #define SEQ_WCSS_WMAC0_MAC_TXOLE_PARSER_REG_OFFSET 0x00aa1000 119 #define SEQ_WCSS_WMAC0_MAC_RRI_REG_OFFSET 0x00aa4000 120 #define SEQ_WCSS_WMAC0_MAC_CRYPTO_REG_OFFSET 0x00aa7000 121 #define SEQ_WCSS_WMAC0_MAC_HWSCH_REG_OFFSET 0x00aaa000 122 #define SEQ_WCSS_WMAC0_MAC_MXI_REG_OFFSET 0x00ab0000 123 #define SEQ_WCSS_WMAC0_MAC_SFM_REG_OFFSET 0x00ab3000 124 #define SEQ_WCSS_WMAC0_MAC_RXDMA1_REG_OFFSET 0x00ab6000 125 #define SEQ_WCSS_APB_TSLV_OFFSET 0x00b40000 126 #define SEQ_WCSS_TOP_CMN_OFFSET 0x00b50000 127 #define SEQ_WCSS_WCMN_CORE_OFFSET 0x00b58000 128 #define SEQ_WCSS_WFSS_PMM_OFFSET 0x00b60000 129 #define SEQ_WCSS_PMM_TOP_OFFSET 0x00b70000 130 #define SEQ_WCSS_WL_MSIP_OFFSET 0x00b80000 131 #define SEQ_WCSS_WL_MSIP_RBIST_TX_CH0_OFFSET 0x00b80000 132 #define SEQ_WCSS_WL_MSIP_WL_DAC_CH0_OFFSET 0x00b80080 133 #define SEQ_WCSS_WL_MSIP_WL_DAC_DIG_CORRECTION_CH0_OFFSET 0x00b800c0 134 #define SEQ_WCSS_WL_MSIP_WL_DAC_MISC_CH0_OFFSET 0x00b80340 135 #define SEQ_WCSS_WL_MSIP_WL_DAC_BBCLKGEN_CH0_OFFSET 0x00b803c4 136 #define SEQ_WCSS_WL_MSIP_WL_ADC_CH0_OFFSET 0x00b80400 137 #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_EVEN_CH0_OFFSET 0x00b80800 138 #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_ODD_CH0_OFFSET 0x00b80840 139 #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH0_OFFSET 0x00b80880 140 #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_ODD_CH0_OFFSET 0x00b808c0 141 #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_RO_CH0_OFFSET 0x00b80900 142 #define SEQ_WCSS_WL_MSIP_WL_ADC_BBCLKGEN_CH0_OFFSET 0x00b8099c 143 #define SEQ_WCSS_WL_MSIP_RBIST_TX_CH1_OFFSET 0x00b81000 144 #define SEQ_WCSS_WL_MSIP_WL_DAC_CH1_OFFSET 0x00b81080 145 #define SEQ_WCSS_WL_MSIP_WL_DAC_DIG_CORRECTION_CH1_OFFSET 0x00b810c0 146 #define SEQ_WCSS_WL_MSIP_WL_DAC_MISC_CH1_OFFSET 0x00b81340 147 #define SEQ_WCSS_WL_MSIP_WL_DAC_BBCLKGEN_CH1_OFFSET 0x00b813c4 148 #define SEQ_WCSS_WL_MSIP_WL_ADC_CH1_OFFSET 0x00b81400 149 #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_EVEN_CH1_OFFSET 0x00b81800 150 #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_I_ODD_CH1_OFFSET 0x00b81840 151 #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH1_OFFSET 0x00b81880 152 #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_Q_ODD_CH1_OFFSET 0x00b818c0 153 #define SEQ_WCSS_WL_MSIP_WL_ADC_POSTPROC_RO_CH1_OFFSET 0x00b81900 154 #define SEQ_WCSS_WL_MSIP_WL_ADC_BBCLKGEN_CH1_OFFSET 0x00b8199c 155 #define SEQ_WCSS_WL_MSIP_MSIP_TMUX_OFFSET 0x00b8d000 156 #define SEQ_WCSS_WL_MSIP_MSIP_OTP_OFFSET 0x00b8d080 157 #define SEQ_WCSS_WL_MSIP_MSIP_LDO_CTRL_OFFSET 0x00b8d0b4 158 #define SEQ_WCSS_WL_MSIP_MSIP_CLKGEN_OFFSET 0x00b8d100 159 #define SEQ_WCSS_WL_MSIP_MSIP_BIAS_OFFSET 0x00b8e000 160 #define SEQ_WCSS_WL_MSIP_BBPLL_OFFSET 0x00b8f000 161 #define SEQ_WCSS_WL_MSIP_WL_TOP_CLKGEN_OFFSET 0x00b8f100 162 #define SEQ_WCSS_WL_MSIP_MSIP_DRM_REG_OFFSET 0x00b8fc00 163 #define SEQ_WCSS_DBG_OFFSET 0x00b90000 164 #define SEQ_WCSS_DBG_WCSS_DBG_DAPROM_OFFSET 0x00b90000 165 #define SEQ_WCSS_DBG_CSR_WCSS_DBG_CSR_OFFSET 0x00b91000 166 #define SEQ_WCSS_DBG_TSGEN_CXTSGEN_OFFSET 0x00b92000 167 #define SEQ_WCSS_DBG_CTIDBG_QC_CTI_32T_8CH_OFFSET 0x00b94000 168 #define SEQ_WCSS_DBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00b95000 169 #define SEQ_WCSS_DBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00b96000 170 #define SEQ_WCSS_DBG_EVENT_MACEVENT_OFFSET 0x00bb0000 171 #define SEQ_WCSS_DBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb1000 172 #define SEQ_WCSS_DBG_TLV_MACTLV_OFFSET 0x00bb2000 173 #define SEQ_WCSS_DBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb3000 174 #define SEQ_WCSS_DBG_TBUS_MACTBUS_OFFSET 0x00bb4000 175 #define SEQ_WCSS_DBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb5000 176 #define SEQ_WCSS_DBG_CTIMAC_QC_CTI_12T_8CH_OFFSET 0x00bb6000 177 #define SEQ_WCSS_DBG_WCSS_DBG_TSTMP_INJCTR_OFFSET 0x00bb8000 178 #define SEQ_WCSS_DBG_TPDM_OFFSET 0x00bb9000 179 #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00bb9280 180 #define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00bb9000 181 #define SEQ_WCSS_DBG_TPDA_OFFSET 0x00bba000 182 #define SEQ_WCSS_DBG_CXATBFUNNEL_128W8SP_OFFSET 0x00bbb000 183 #define SEQ_WCSS_DBG_TMC_CXTMC_F128W32K_OFFSET 0x00bbc000 184 #define SEQ_WCSS_DBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET 0x00bbe000 185 #define SEQ_WCSS_DBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET 0x00bbf000 186 #define SEQ_WCSS_DBG_OUTDMUX_ATB_DEMUX_OFFSET 0x00bc0000 187 #define SEQ_WCSS_DBG_TRCCNTRS_OFFSET 0x00bc1000 188 #define SEQ_WCSS_DBG_TLV_TPDM_ATB128_CMB64_OFFSET 0x00bc2000 189 #define SEQ_WCSS_DBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00bc2280 190 #define SEQ_WCSS_DBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00bc2000 191 #define SEQ_WCSS_DBG_MISC_TPDM_ATB128_CMB64_OFFSET 0x00bc3000 192 #define SEQ_WCSS_DBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00bc3280 193 #define SEQ_WCSS_DBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00bc3000 194 #define SEQ_WCSS_DBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET 0x00bc4000 195 #define SEQ_WCSS_DBG_CTITGU_QC_CTI_4T_8CH_OFFSET 0x00bc5000 196 #define SEQ_WCSS_DBG_PHYADMUX_ATB_DEMUX_OFFSET 0x00bc6000 197 #define SEQ_WCSS_DBG_MISCFUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bc8000 198 #define SEQ_WCSS_DBG_UNOC_UMAC_NOC_OFFSET 0x00bd0000 199 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_OFFSET 0x00be0000 200 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_PHYA_NOC_OFFSET 0x00be0000 201 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00be4000 202 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00be5000 203 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00be6000 204 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_ITM_OFFSET 0x00be8000 205 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_DWT_OFFSET 0x00be9000 206 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_FPB_OFFSET 0x00bea000 207 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_SCS_OFFSET 0x00beb000 208 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_M3_ETM_OFFSET 0x00bec000 209 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x00bed000 210 #define SEQ_WCSS_DBG_PHYA_PHYA_DBG_CPU0_M3_AHB_AP_OFFSET 0x00bee000 211 #define SEQ_WCSS_DBG_BUS_TIMEOUT_OFFSET 0x00c31000 212 #define SEQ_WCSS_RET_AHB_OFFSET 0x00c90000 213 #define SEQ_WCSS_WAHB_TSLV_OFFSET 0x00ca0000 214 #define SEQ_WCSS_CC_OFFSET 0x00cb0000 215 #define SEQ_WCSS_UMAC_ACMT_OFFSET 0x00cc0000 216 217 218 /////////////////////////////////////////////////////////////////////////////////////////////// 219 // Instance Relative Offsets from Block wfax_top 220 /////////////////////////////////////////////////////////////////////////////////////////////// 221 222 #define SEQ_WFAX_TOP_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00000000 223 #define SEQ_WFAX_TOP_WFAX_PCSS_REG_MAP_OFFSET 0x00080000 224 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00080400 225 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00080800 226 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00080c00 227 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00081000 228 #define SEQ_WFAX_TOP_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00081400 229 #define SEQ_WFAX_TOP_WFAX_PCSS_DUAL_TIMER_REG_MAP_OFFSET 0x00081800 230 #define SEQ_WFAX_TOP_WFAX_PCSS_WATCHDOG_REG_MAP_OFFSET 0x00081c00 231 #define SEQ_WFAX_TOP_WFAX_PCSS_XDMAC5_REG_MAP_OFFSET 0x00082c00 232 #define SEQ_WFAX_TOP_WFAX_PCSS_XDMAC6_REG_MAP_OFFSET 0x00083000 233 #define SEQ_WFAX_TOP_WFAX_NOC_REG_MAP_OFFSET 0x00088000 234 #define SEQ_WFAX_TOP_WFAX_TXFD_REG_MAP_OFFSET 0x00090000 235 #define SEQ_WFAX_TOP_WFAX_RXTD_REG_MAP_OFFSET 0x000a0000 236 #define SEQ_WFAX_TOP_WFAX_TXTD_REG_MAP_OFFSET 0x000b0000 237 #define SEQ_WFAX_TOP_WFAX_TXBF_REG_MAP_OFFSET 0x000c0000 238 #define SEQ_WFAX_TOP_WFAX_DEMFRONT_0_REG_MAP_OFFSET 0x00100000 239 #define SEQ_WFAX_TOP_WFAX_PHYRF_REG_MAP_OFFSET 0x00180000 240 #define SEQ_WFAX_TOP_WFAX_ROBE_REG_MAP_OFFSET 0x001b0000 241 #define SEQ_WFAX_TOP_WFAX_DEMFRONT_1_REG_MAP_OFFSET 0x00200000 242 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_OFFSET 0x002c0000 243 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x002d4000 244 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x002d4000 245 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_XFEM_OFFSET 0x002d4240 246 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET 0x002d42c0 247 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x002d4300 248 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x002d4400 249 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET 0x002d4480 250 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x002d4800 251 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x002d6000 252 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x002d6040 253 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x002d6100 254 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x002d6140 255 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x002d6180 256 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x002d61c0 257 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x002d6280 258 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x002d7c00 259 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_PMU_OFFSET 0x002da000 260 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_PMU_PMU_OFFSET 0x002da000 261 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x002e0000 262 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x002e0000 263 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x002e0400 264 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x002e0800 265 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH0_OFFSET 0x002e1000 266 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH0_OFFSET 0x002e1300 267 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x002e1600 268 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_CH0_OFFSET 0x002e1640 269 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x002e2000 270 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH0_OFFSET 0x002e4000 271 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x002e8000 272 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x002e8400 273 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x002e8800 274 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_CH1_OFFSET 0x002e9000 275 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_CH1_OFFSET 0x002e9300 276 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x002e9600 277 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_CH1_OFFSET 0x002e9640 278 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x002ea000 279 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH1_OFFSET 0x002ec000 280 281 282 /////////////////////////////////////////////////////////////////////////////////////////////// 283 // Instance Relative Offsets from Block rfa_from_wsi 284 /////////////////////////////////////////////////////////////////////////////////////////////// 285 286 #define SEQ_RFA_FROM_WSI_RFA_CMN_OFFSET 0x00014000 287 #define SEQ_RFA_FROM_WSI_RFA_CMN_AON_OFFSET 0x00014000 288 #define SEQ_RFA_FROM_WSI_RFA_CMN_AON_XFEM_OFFSET 0x00014240 289 #define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_OFFSET 0x000142c0 290 #define SEQ_RFA_FROM_WSI_RFA_CMN_RFFE_M_OFFSET 0x00014300 291 #define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00014400 292 #define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_OTP_OFFSET 0x00014480 293 #define SEQ_RFA_FROM_WSI_RFA_CMN_CLKGEN_OFFSET 0x00014800 294 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00016000 295 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00016040 296 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00016100 297 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00016140 298 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00016180 299 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000161c0 300 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00016280 301 #define SEQ_RFA_FROM_WSI_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00017c00 302 #define SEQ_RFA_FROM_WSI_RFA_PMU_OFFSET 0x0001a000 303 #define SEQ_RFA_FROM_WSI_RFA_PMU_PMU_OFFSET 0x0001a000 304 #define SEQ_RFA_FROM_WSI_RFA_WL_OFFSET 0x00020000 305 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_CH0_OFFSET 0x00020000 306 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH0_OFFSET 0x00020400 307 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH0_OFFSET 0x00020800 308 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_CH0_OFFSET 0x00021000 309 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_CH0_OFFSET 0x00021300 310 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x00021600 311 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_CH0_OFFSET 0x00021640 312 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_CH0_OFFSET 0x00022000 313 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_CH0_OFFSET 0x00024000 314 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_CH1_OFFSET 0x00028000 315 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH1_OFFSET 0x00028400 316 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH1_OFFSET 0x00028800 317 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_CH1_OFFSET 0x00029000 318 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_CH1_OFFSET 0x00029300 319 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x00029600 320 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_CH1_OFFSET 0x00029640 321 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_CH1_OFFSET 0x0002a000 322 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_CH1_OFFSET 0x0002c000 323 324 325 /////////////////////////////////////////////////////////////////////////////////////////////// 326 // Instance Relative Offsets from Block rfa_cmn 327 /////////////////////////////////////////////////////////////////////////////////////////////// 328 329 #define SEQ_RFA_CMN_AON_OFFSET 0x00000000 330 #define SEQ_RFA_CMN_AON_XFEM_OFFSET 0x00000240 331 #define SEQ_RFA_CMN_AON_COEX_OFFSET 0x000002c0 332 #define SEQ_RFA_CMN_RFFE_M_OFFSET 0x00000300 333 #define SEQ_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00000400 334 #define SEQ_RFA_CMN_RFA_OTP_OFFSET 0x00000480 335 #define SEQ_RFA_CMN_CLKGEN_OFFSET 0x00000800 336 #define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00002000 337 #define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00002040 338 #define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00002100 339 #define SEQ_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00002140 340 #define SEQ_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00002180 341 #define SEQ_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000021c0 342 #define SEQ_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00002280 343 #define SEQ_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00003c00 344 345 346 /////////////////////////////////////////////////////////////////////////////////////////////// 347 // Instance Relative Offsets from Block rfa_pmu 348 /////////////////////////////////////////////////////////////////////////////////////////////// 349 350 #define SEQ_RFA_PMU_PMU_OFFSET 0x00000000 351 352 353 /////////////////////////////////////////////////////////////////////////////////////////////// 354 // Instance Relative Offsets from Block rfa_wl 355 /////////////////////////////////////////////////////////////////////////////////////////////// 356 357 #define SEQ_RFA_WL_WL_MC_CH0_OFFSET 0x00000000 358 #define SEQ_RFA_WL_WL_RXBB_CH0_OFFSET 0x00000400 359 #define SEQ_RFA_WL_WL_TXBB_CH0_OFFSET 0x00000800 360 #define SEQ_RFA_WL_WL_RXFE_CH0_OFFSET 0x00001000 361 #define SEQ_RFA_WL_WL_TXFE_CH0_OFFSET 0x00001300 362 #define SEQ_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x00001600 363 #define SEQ_RFA_WL_WL_LO_CH0_OFFSET 0x00001640 364 #define SEQ_RFA_WL_WL_TPC_CH0_OFFSET 0x00002000 365 #define SEQ_RFA_WL_WL_MEM_CH0_OFFSET 0x00004000 366 #define SEQ_RFA_WL_WL_MC_CH1_OFFSET 0x00008000 367 #define SEQ_RFA_WL_WL_RXBB_CH1_OFFSET 0x00008400 368 #define SEQ_RFA_WL_WL_TXBB_CH1_OFFSET 0x00008800 369 #define SEQ_RFA_WL_WL_RXFE_CH1_OFFSET 0x00009000 370 #define SEQ_RFA_WL_WL_TXFE_CH1_OFFSET 0x00009300 371 #define SEQ_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x00009600 372 #define SEQ_RFA_WL_WL_LO_CH1_OFFSET 0x00009640 373 #define SEQ_RFA_WL_WL_TPC_CH1_OFFSET 0x0000a000 374 #define SEQ_RFA_WL_WL_MEM_CH1_OFFSET 0x0000c000 375 376 377 /////////////////////////////////////////////////////////////////////////////////////////////// 378 // Instance Relative Offsets from Block umac_top_reg 379 /////////////////////////////////////////////////////////////////////////////////////////////// 380 381 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_OFFSET 0x00020000 382 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00020000 383 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00022000 384 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00024000 385 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00026000 386 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00028000 387 #define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0002a000 388 #define SEQ_UMAC_TOP_REG_MAC_TRACER_REG_OFFSET 0x00030000 389 #define SEQ_UMAC_TOP_REG_WBM_REG_OFFSET 0x00034000 390 #define SEQ_UMAC_TOP_REG_REO_REG_OFFSET 0x00038000 391 #define SEQ_UMAC_TOP_REG_TQM_REG_OFFSET 0x0003c000 392 #define SEQ_UMAC_TOP_REG_MAC_UMCMN_REG_OFFSET 0x00040000 393 #define SEQ_UMAC_TOP_REG_MAC_TCL_REG_OFFSET 0x00044000 394 #define SEQ_UMAC_TOP_REG_MAC_CMN_PARSER_REG_OFFSET 0x00047000 395 396 397 /////////////////////////////////////////////////////////////////////////////////////////////// 398 // Instance Relative Offsets from Block cxc_top_reg 399 /////////////////////////////////////////////////////////////////////////////////////////////// 400 401 #define SEQ_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00000000 402 #define SEQ_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00002000 403 #define SEQ_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00004000 404 #define SEQ_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00006000 405 #define SEQ_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00008000 406 #define SEQ_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0000a000 407 408 409 /////////////////////////////////////////////////////////////////////////////////////////////// 410 // Instance Relative Offsets from Block wmac_top_reg 411 /////////////////////////////////////////////////////////////////////////////////////////////// 412 413 #define SEQ_WMAC_TOP_REG_MAC_PDG_REG_OFFSET 0x00000000 414 #define SEQ_WMAC_TOP_REG_MAC_TXDMA_REG_OFFSET 0x00003000 415 #define SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET 0x00006000 416 #define SEQ_WMAC_TOP_REG_MAC_MCMN_REG_OFFSET 0x00009000 417 #define SEQ_WMAC_TOP_REG_MAC_RXPCU_REG_OFFSET 0x0000c000 418 #define SEQ_WMAC_TOP_REG_MAC_TXPCU_REG_OFFSET 0x0000f000 419 #define SEQ_WMAC_TOP_REG_MAC_AMPI_REG_OFFSET 0x00012000 420 #define SEQ_WMAC_TOP_REG_MAC_RXOLE_REG_OFFSET 0x00015000 421 #define SEQ_WMAC_TOP_REG_MAC_RXOLE_PARSER_REG_OFFSET 0x00018000 422 #define SEQ_WMAC_TOP_REG_MAC_CCE_REG_OFFSET 0x0001b000 423 #define SEQ_WMAC_TOP_REG_MAC_TXOLE_REG_OFFSET 0x0001e000 424 #define SEQ_WMAC_TOP_REG_MAC_TXOLE_PARSER_REG_OFFSET 0x00021000 425 #define SEQ_WMAC_TOP_REG_MAC_RRI_REG_OFFSET 0x00024000 426 #define SEQ_WMAC_TOP_REG_MAC_CRYPTO_REG_OFFSET 0x00027000 427 #define SEQ_WMAC_TOP_REG_MAC_HWSCH_REG_OFFSET 0x0002a000 428 #define SEQ_WMAC_TOP_REG_MAC_MXI_REG_OFFSET 0x00030000 429 #define SEQ_WMAC_TOP_REG_MAC_SFM_REG_OFFSET 0x00033000 430 #define SEQ_WMAC_TOP_REG_MAC_RXDMA1_REG_OFFSET 0x00036000 431 432 433 /////////////////////////////////////////////////////////////////////////////////////////////// 434 // Instance Relative Offsets from Block msip 435 /////////////////////////////////////////////////////////////////////////////////////////////// 436 437 #define SEQ_MSIP_RBIST_TX_CH0_OFFSET 0x00000000 438 #define SEQ_MSIP_WL_DAC_CH0_OFFSET 0x00000080 439 #define SEQ_MSIP_WL_DAC_DIG_CORRECTION_CH0_OFFSET 0x000000c0 440 #define SEQ_MSIP_WL_DAC_MISC_CH0_OFFSET 0x00000340 441 #define SEQ_MSIP_WL_DAC_BBCLKGEN_CH0_OFFSET 0x000003c4 442 #define SEQ_MSIP_WL_ADC_CH0_OFFSET 0x00000400 443 #define SEQ_MSIP_WL_ADC_POSTPROC_I_EVEN_CH0_OFFSET 0x00000800 444 #define SEQ_MSIP_WL_ADC_POSTPROC_I_ODD_CH0_OFFSET 0x00000840 445 #define SEQ_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH0_OFFSET 0x00000880 446 #define SEQ_MSIP_WL_ADC_POSTPROC_Q_ODD_CH0_OFFSET 0x000008c0 447 #define SEQ_MSIP_WL_ADC_POSTPROC_RO_CH0_OFFSET 0x00000900 448 #define SEQ_MSIP_WL_ADC_BBCLKGEN_CH0_OFFSET 0x0000099c 449 #define SEQ_MSIP_RBIST_TX_CH1_OFFSET 0x00001000 450 #define SEQ_MSIP_WL_DAC_CH1_OFFSET 0x00001080 451 #define SEQ_MSIP_WL_DAC_DIG_CORRECTION_CH1_OFFSET 0x000010c0 452 #define SEQ_MSIP_WL_DAC_MISC_CH1_OFFSET 0x00001340 453 #define SEQ_MSIP_WL_DAC_BBCLKGEN_CH1_OFFSET 0x000013c4 454 #define SEQ_MSIP_WL_ADC_CH1_OFFSET 0x00001400 455 #define SEQ_MSIP_WL_ADC_POSTPROC_I_EVEN_CH1_OFFSET 0x00001800 456 #define SEQ_MSIP_WL_ADC_POSTPROC_I_ODD_CH1_OFFSET 0x00001840 457 #define SEQ_MSIP_WL_ADC_POSTPROC_Q_EVEN_CH1_OFFSET 0x00001880 458 #define SEQ_MSIP_WL_ADC_POSTPROC_Q_ODD_CH1_OFFSET 0x000018c0 459 #define SEQ_MSIP_WL_ADC_POSTPROC_RO_CH1_OFFSET 0x00001900 460 #define SEQ_MSIP_WL_ADC_BBCLKGEN_CH1_OFFSET 0x0000199c 461 #define SEQ_MSIP_MSIP_TMUX_OFFSET 0x0000d000 462 #define SEQ_MSIP_MSIP_OTP_OFFSET 0x0000d080 463 #define SEQ_MSIP_MSIP_LDO_CTRL_OFFSET 0x0000d0b4 464 #define SEQ_MSIP_MSIP_CLKGEN_OFFSET 0x0000d100 465 #define SEQ_MSIP_MSIP_BIAS_OFFSET 0x0000e000 466 #define SEQ_MSIP_BBPLL_OFFSET 0x0000f000 467 #define SEQ_MSIP_WL_TOP_CLKGEN_OFFSET 0x0000f100 468 #define SEQ_MSIP_MSIP_DRM_REG_OFFSET 0x0000fc00 469 470 471 /////////////////////////////////////////////////////////////////////////////////////////////// 472 // Instance Relative Offsets from Block wcssdbg 473 /////////////////////////////////////////////////////////////////////////////////////////////// 474 475 #define SEQ_WCSSDBG_WCSS_DBG_DAPROM_OFFSET 0x00000000 476 #define SEQ_WCSSDBG_CSR_WCSS_DBG_CSR_OFFSET 0x00001000 477 #define SEQ_WCSSDBG_TSGEN_CXTSGEN_OFFSET 0x00002000 478 #define SEQ_WCSSDBG_CTIDBG_QC_CTI_32T_8CH_OFFSET 0x00004000 479 #define SEQ_WCSSDBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00005000 480 #define SEQ_WCSSDBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00006000 481 #define SEQ_WCSSDBG_EVENT_MACEVENT_OFFSET 0x00020000 482 #define SEQ_WCSSDBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00021000 483 #define SEQ_WCSSDBG_TLV_MACTLV_OFFSET 0x00022000 484 #define SEQ_WCSSDBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00023000 485 #define SEQ_WCSSDBG_TBUS_MACTBUS_OFFSET 0x00024000 486 #define SEQ_WCSSDBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00025000 487 #define SEQ_WCSSDBG_CTIMAC_QC_CTI_12T_8CH_OFFSET 0x00026000 488 #define SEQ_WCSSDBG_WCSS_DBG_TSTMP_INJCTR_OFFSET 0x00028000 489 #define SEQ_WCSSDBG_TPDM_OFFSET 0x00029000 490 #define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00029280 491 #define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00029000 492 #define SEQ_WCSSDBG_TPDA_OFFSET 0x0002a000 493 #define SEQ_WCSSDBG_CXATBFUNNEL_128W8SP_OFFSET 0x0002b000 494 #define SEQ_WCSSDBG_TMC_CXTMC_F128W32K_OFFSET 0x0002c000 495 #define SEQ_WCSSDBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET 0x0002e000 496 #define SEQ_WCSSDBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET 0x0002f000 497 #define SEQ_WCSSDBG_OUTDMUX_ATB_DEMUX_OFFSET 0x00030000 498 #define SEQ_WCSSDBG_TRCCNTRS_OFFSET 0x00031000 499 #define SEQ_WCSSDBG_TLV_TPDM_ATB128_CMB64_OFFSET 0x00032000 500 #define SEQ_WCSSDBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00032280 501 #define SEQ_WCSSDBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00032000 502 #define SEQ_WCSSDBG_MISC_TPDM_ATB128_CMB64_OFFSET 0x00033000 503 #define SEQ_WCSSDBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00033280 504 #define SEQ_WCSSDBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00033000 505 #define SEQ_WCSSDBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET 0x00034000 506 #define SEQ_WCSSDBG_CTITGU_QC_CTI_4T_8CH_OFFSET 0x00035000 507 #define SEQ_WCSSDBG_PHYADMUX_ATB_DEMUX_OFFSET 0x00036000 508 #define SEQ_WCSSDBG_MISCFUN_CXATBFUNNEL_64W8SP_OFFSET 0x00038000 509 #define SEQ_WCSSDBG_UNOC_UMAC_NOC_OFFSET 0x00040000 510 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_OFFSET 0x00050000 511 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_PHYA_NOC_OFFSET 0x00050000 512 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00054000 513 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00055000 514 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00056000 515 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_ITM_OFFSET 0x00058000 516 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_DWT_OFFSET 0x00059000 517 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_FPB_OFFSET 0x0005a000 518 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_SCS_OFFSET 0x0005b000 519 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_M3_ETM_OFFSET 0x0005c000 520 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x0005d000 521 #define SEQ_WCSSDBG_PHYA_PHYA_DBG_CPU0_M3_AHB_AP_OFFSET 0x0005e000 522 #define SEQ_WCSSDBG_BUS_TIMEOUT_OFFSET 0x000a1000 523 524 525 /////////////////////////////////////////////////////////////////////////////////////////////// 526 // Instance Relative Offsets from Block tpdm_atb64_cmb40_dsb256_csbe6c04f7 527 /////////////////////////////////////////////////////////////////////////////////////////////// 528 529 #define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00000280 530 #define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00000000 531 532 533 /////////////////////////////////////////////////////////////////////////////////////////////// 534 // Instance Relative Offsets from Block tpdm_atb128_cmb64 535 /////////////////////////////////////////////////////////////////////////////////////////////// 536 537 #define SEQ_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00000280 538 #define SEQ_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00000000 539 540 541 /////////////////////////////////////////////////////////////////////////////////////////////// 542 // Instance Relative Offsets from Block phya_dbg 543 /////////////////////////////////////////////////////////////////////////////////////////////// 544 545 #define SEQ_PHYA_DBG_PHYA_NOC_OFFSET 0x00000000 546 #define SEQ_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00004000 547 #define SEQ_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00005000 548 #define SEQ_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00006000 549 #define SEQ_PHYA_DBG_ITM_OFFSET 0x00008000 550 #define SEQ_PHYA_DBG_DWT_OFFSET 0x00009000 551 #define SEQ_PHYA_DBG_FPB_OFFSET 0x0000a000 552 #define SEQ_PHYA_DBG_SCS_OFFSET 0x0000b000 553 #define SEQ_PHYA_DBG_M3_ETM_OFFSET 0x0000c000 554 #define SEQ_PHYA_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x0000d000 555 #define SEQ_PHYA_DBG_CPU0_M3_AHB_AP_OFFSET 0x0000e000 556 557 558 #endif 559 560