1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 18 #ifndef _COEX_RX_STATUS_H_ 19 #define _COEX_RX_STATUS_H_ 20 #if !defined(__ASSEMBLER__) 21 #endif 22 23 #define NUM_OF_DWORDS_COEX_RX_STATUS 2 24 25 #define NUM_OF_QWORDS_COEX_RX_STATUS 1 26 27 28 struct coex_rx_status { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 uint32_t rx_mac_frame_status : 2, // [1:0] 31 rx_with_tx_response : 1, // [2:2] 32 rx_rate : 5, // [7:3] 33 rx_bw : 3, // [10:8] 34 single_mpdu : 1, // [11:11] 35 filter_status : 1, // [12:12] 36 ampdu : 1, // [13:13] 37 directed : 1, // [14:14] 38 reserved_0 : 1, // [15:15] 39 rx_nss : 3, // [18:16] 40 rx_rssi : 8, // [26:19] 41 rx_type : 3, // [29:27] 42 retry_bit_setting : 1, // [30:30] 43 more_data_bit_setting : 1; // [31:31] 44 uint32_t remain_rx_packet_time : 16, // [15:0] 45 rx_remaining_fes_time : 16; // [31:16] 46 #else 47 uint32_t more_data_bit_setting : 1, // [31:31] 48 retry_bit_setting : 1, // [30:30] 49 rx_type : 3, // [29:27] 50 rx_rssi : 8, // [26:19] 51 rx_nss : 3, // [18:16] 52 reserved_0 : 1, // [15:15] 53 directed : 1, // [14:14] 54 ampdu : 1, // [13:13] 55 filter_status : 1, // [12:12] 56 single_mpdu : 1, // [11:11] 57 rx_bw : 3, // [10:8] 58 rx_rate : 5, // [7:3] 59 rx_with_tx_response : 1, // [2:2] 60 rx_mac_frame_status : 2; // [1:0] 61 uint32_t rx_remaining_fes_time : 16, // [31:16] 62 remain_rx_packet_time : 16; // [15:0] 63 #endif 64 }; 65 66 67 /* Description RX_MAC_FRAME_STATUS 68 69 RXPCU send this bit as 1 when it receives the begin of a 70 frame from PHY, and it passes the address filter. RXPCUsend 71 this bit as 0 when the frame ends. (on/off bit) 72 <enum 0 ppdu_start> start of PPDU reception. 73 For SU: Generated the first time the MPDU header passes 74 the address filter and is destined to this STA. 75 For MU: Generated the first time the MPDU header from any 76 user passes the address filter and is destined to this 77 STA. 78 <enum 1 first_mpdu_FCS_pass> message only sent in case 79 of A-MPDU reception. 80 For SU: first time the FCS of an MPDU passes (and frame 81 is destined to this device) 82 For MU: first time the FCS of any MPDU passes (and frame 83 is destined to this device) 84 85 <enum 2 ppdu_end> receive of PPDU frame reception has 86 finished 87 <enum 3 ppdu_end_due_to_phy_nap> receive of PPDU frame reception 88 has finished as it has been aborted due to PHY NAP generation 89 90 <legal all> 91 */ 92 93 #define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_OFFSET 0x0000000000000000 94 #define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_LSB 0 95 #define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MSB 1 96 #define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MASK 0x0000000000000003 97 98 99 /* Description RX_WITH_TX_RESPONSE 100 101 Field only valid when rx_mac_frame_status is first_mpdu_FCS_pass 102 or ppdu_end. 103 104 For SU: RXPCU set this bit to indicate it is expecting the 105 TX to send a response after the receive. 106 For MU: RXPCU set this bit to indicate it is expecting that 107 at least for one of the users a response after the reception 108 needs to be generated. 109 110 <legal all> 111 */ 112 113 #define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_OFFSET 0x0000000000000000 114 #define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_LSB 2 115 #define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MSB 2 116 #define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MASK 0x0000000000000004 117 118 119 /* Description RX_RATE 120 121 For SU: RXPCU send the current receive rate at the beginning 122 of receive when rate is available from PHY. 123 For MU: RXPCU to use the current receive rate from the first 124 USER that triggers this TLV to be generated. 125 126 Field is always valid 127 128 <legal all> 129 */ 130 131 #define COEX_RX_STATUS_RX_RATE_OFFSET 0x0000000000000000 132 #define COEX_RX_STATUS_RX_RATE_LSB 3 133 #define COEX_RX_STATUS_RX_RATE_MSB 7 134 #define COEX_RX_STATUS_RX_RATE_MASK 0x00000000000000f8 135 136 137 /* Description RX_BW 138 139 Actual RX bandwidth. Not SU or MU dependent. 140 RXPCU send the current receive rate at the beginning of 141 receive. This information is from PHY. 142 Field is always valid 143 144 <enum 0 20_mhz>20 Mhz BW 145 <enum 1 40_mhz>40 Mhz BW 146 <enum 2 80_mhz>80 Mhz BW 147 <enum 3 160_mhz>160 Mhz BW 148 <enum 4 320_mhz>320 Mhz BW 149 <enum 5 240_mhz>240 Mhz BW 150 */ 151 152 #define COEX_RX_STATUS_RX_BW_OFFSET 0x0000000000000000 153 #define COEX_RX_STATUS_RX_BW_LSB 8 154 #define COEX_RX_STATUS_RX_BW_MSB 10 155 #define COEX_RX_STATUS_RX_BW_MASK 0x0000000000000700 156 157 158 /* Description SINGLE_MPDU 159 160 For SU: Once set the Received frame is a single MPDU. This 161 can be a non-AMPDU reception or A-MPDU reception but with 162 an EOF bit set (VHT single AMPDU). 163 For MU: RXPCU to base this on the first USER that triggers 164 this TLV to be generated. 165 <legal all> 166 */ 167 168 #define COEX_RX_STATUS_SINGLE_MPDU_OFFSET 0x0000000000000000 169 #define COEX_RX_STATUS_SINGLE_MPDU_LSB 11 170 #define COEX_RX_STATUS_SINGLE_MPDU_MSB 11 171 #define COEX_RX_STATUS_SINGLE_MPDU_MASK 0x0000000000000800 172 173 174 /* Description FILTER_STATUS 175 176 1: LMAC is interested in receiving the full packet and forward 177 it to downstream modules. 0: LMAC is not interested in 178 receiving the packet. 179 180 Based on the register bit 'COEX_RX_STATUS_NOFILTERIN,' 181 Rx PCU will send this TLV for filtered-out packets as well, 182 with appropriate info in the fields filter_status, AMPDU 183 and Directed. Otherwise, and in other chips, this TLV is 184 sent only for packets filtered in, with these fields set 185 to zero. 186 <legal all> 187 */ 188 189 #define COEX_RX_STATUS_FILTER_STATUS_OFFSET 0x0000000000000000 190 #define COEX_RX_STATUS_FILTER_STATUS_LSB 12 191 #define COEX_RX_STATUS_FILTER_STATUS_MSB 12 192 #define COEX_RX_STATUS_FILTER_STATUS_MASK 0x0000000000001000 193 194 195 /* Description AMPDU 196 197 1: Indicates received frame is an AMPDU0: indicates received 198 frames in not an AMPDU 199 200 Based on the register bit 'COEX_RX_STATUS_NOFILTERIN,' 201 Rx PCU will send this TLV for filtered-out packets as well, 202 with appropriate info in the fields filter_status, AMPDU 203 and Directed. Otherwise, and in other chips, this TLV is 204 sent only for packets filtered in, with these fields set 205 to zero. 206 <legal all> 207 */ 208 209 #define COEX_RX_STATUS_AMPDU_OFFSET 0x0000000000000000 210 #define COEX_RX_STATUS_AMPDU_LSB 13 211 #define COEX_RX_STATUS_AMPDU_MSB 13 212 #define COEX_RX_STATUS_AMPDU_MASK 0x0000000000002000 213 214 215 /* Description DIRECTED 216 217 1: indicates AD1 matches our Receiver address0: indicates 218 AD1 does not match our Receiver address 219 220 Based on the register bit 'COEX_RX_STATUS_NOFILTERIN,' 221 Rx PCU will send this TLV for filtered-out packets as well, 222 with appropriate info in the fields filter_status, AMPDU 223 and Directed. Otherwise, and in other chips, this TLV is 224 sent only for packets filtered in, with these fields set 225 to zero. 226 <legal all> 227 */ 228 229 #define COEX_RX_STATUS_DIRECTED_OFFSET 0x0000000000000000 230 #define COEX_RX_STATUS_DIRECTED_LSB 14 231 #define COEX_RX_STATUS_DIRECTED_MSB 14 232 #define COEX_RX_STATUS_DIRECTED_MASK 0x0000000000004000 233 234 235 /* Description RESERVED_0 236 237 <legal 0> 238 */ 239 240 #define COEX_RX_STATUS_RESERVED_0_OFFSET 0x0000000000000000 241 #define COEX_RX_STATUS_RESERVED_0_LSB 15 242 #define COEX_RX_STATUS_RESERVED_0_MSB 15 243 #define COEX_RX_STATUS_RESERVED_0_MASK 0x0000000000008000 244 245 246 /* Description RX_NSS 247 248 For SU: Number of spatial streams in the reception. Field 249 is always valid 250 For MU: RXPCU to base this on the first USER that triggers 251 this TLV to be generated. 252 253 <enum 0 1_spatial_stream>Single spatial stream 254 <enum 1 2_spatial_streams>2 spatial streams 255 <enum 2 3_spatial_streams>3 spatial streams 256 <enum 3 4_spatial_streams>4 spatial streams 257 <enum 4 5_spatial_streams>5 spatial streams 258 <enum 5 6_spatial_streams>6 spatial streams 259 <enum 6 7_spatial_streams>7 spatial streams 260 <enum 7 8_spatial_streams>8 spatial streams 261 */ 262 263 #define COEX_RX_STATUS_RX_NSS_OFFSET 0x0000000000000000 264 #define COEX_RX_STATUS_RX_NSS_LSB 16 265 #define COEX_RX_STATUS_RX_NSS_MSB 18 266 #define COEX_RX_STATUS_RX_NSS_MASK 0x0000000000070000 267 268 269 /* Description RX_RSSI 270 271 RXPCU send the current receive RSSI (from the PHYRX_RSSI_LEGACY 272 TLV) at the beginning of reception. This is information 273 is from PHY and is not SU or MU dependent. 274 Field is always valid 275 <legal all> 276 */ 277 278 #define COEX_RX_STATUS_RX_RSSI_OFFSET 0x0000000000000000 279 #define COEX_RX_STATUS_RX_RSSI_LSB 19 280 #define COEX_RX_STATUS_RX_RSSI_MSB 26 281 #define COEX_RX_STATUS_RX_RSSI_MASK 0x0000000007f80000 282 283 284 /* Description RX_TYPE 285 286 For SU: RXPCU send the current receive packet type. Field 287 is always valid.This info is from MAC. 288 For MU: RXPCU to base this on the first USER that triggers 289 this TLV to be generated. 290 291 <enum 0 data > 292 <enum 1 management> 293 <enum 2 beacon> 294 <enum 3 control> For reception of RTS frame 295 <enum 4 control_response> For reception of CTS, ACK 296 or BA frames 297 <enum 5 others> 298 <legal 0-5> 299 */ 300 301 #define COEX_RX_STATUS_RX_TYPE_OFFSET 0x0000000000000000 302 #define COEX_RX_STATUS_RX_TYPE_LSB 27 303 #define COEX_RX_STATUS_RX_TYPE_MSB 29 304 #define COEX_RX_STATUS_RX_TYPE_MASK 0x0000000038000000 305 306 307 /* Description RETRY_BIT_SETTING 308 309 For SU: Value of the retry bit in the frame control field 310 of the first MPDU MAC header that passes the RxPCU frame 311 filter 312 For MU: RXPCU to base this on the first USER that triggers 313 this TLV to be generated. 314 315 <legal all> 316 */ 317 318 #define COEX_RX_STATUS_RETRY_BIT_SETTING_OFFSET 0x0000000000000000 319 #define COEX_RX_STATUS_RETRY_BIT_SETTING_LSB 30 320 #define COEX_RX_STATUS_RETRY_BIT_SETTING_MSB 30 321 #define COEX_RX_STATUS_RETRY_BIT_SETTING_MASK 0x0000000040000000 322 323 324 /* Description MORE_DATA_BIT_SETTING 325 326 For SU: Value of the more data bit in the frame control 327 field of the first MPDU MAC header that passes the RxPCU 328 frame filter 329 For MU: RXPCU to base this on the first USER that triggers 330 this TLV to be generated. 331 332 <legal all> 333 */ 334 335 #define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_OFFSET 0x0000000000000000 336 #define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_LSB 31 337 #define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MSB 31 338 #define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MASK 0x0000000080000000 339 340 341 /* Description REMAIN_RX_PACKET_TIME 342 343 HWSCH sends current remaining rx PPDU frame time. This time 344 covers the entire rx_frame. This information is not in 345 the L-SIG and we expect to get it from PHY at the start 346 of the reception. 347 This is not SU or MU dependent. 348 <legal all> 349 */ 350 351 #define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_OFFSET 0x0000000000000000 352 #define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_LSB 32 353 #define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MSB 47 354 #define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MASK 0x0000ffff00000000 355 356 357 /* Description RX_REMAINING_FES_TIME 358 359 RXPCU sends the remaining time FES time the moment a frame 360 with proper FCS is received. The time indicated is the 361 remaining rx packet time with the duration field value added. 362 As long as no frame with valid FCS is received, this field 363 should be set equal to 'remain_rx_packet_time' 364 This is not SU or MU dependent. 365 <legal all> 366 */ 367 368 #define COEX_RX_STATUS_RX_REMAINING_FES_TIME_OFFSET 0x0000000000000000 369 #define COEX_RX_STATUS_RX_REMAINING_FES_TIME_LSB 48 370 #define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MSB 63 371 #define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MASK 0xffff000000000000 372 373 374 375 #endif // COEX_RX_STATUS 376