1*5113495bSYour Name /* 2*5113495bSYour Name * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3*5113495bSYour Name * 4*5113495bSYour Name * Permission to use, copy, modify, and/or distribute this software for any 5*5113495bSYour Name * purpose with or without fee is hereby granted, provided that the above 6*5113495bSYour Name * copyright notice and this permission notice appear in all copies. 7*5113495bSYour Name * 8*5113495bSYour Name * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9*5113495bSYour Name * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10*5113495bSYour Name * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11*5113495bSYour Name * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12*5113495bSYour Name * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13*5113495bSYour Name * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14*5113495bSYour Name * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15*5113495bSYour Name */ 16*5113495bSYour Name 17*5113495bSYour Name #ifndef _MACTX_EHT_SIG_USR_MU_MIMO_H_ 18*5113495bSYour Name #define _MACTX_EHT_SIG_USR_MU_MIMO_H_ 19*5113495bSYour Name #if !defined(__ASSEMBLER__) 20*5113495bSYour Name #endif 21*5113495bSYour Name 22*5113495bSYour Name #include "eht_sig_usr_mu_mimo_info.h" 23*5113495bSYour Name #define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_MU_MIMO 2 24*5113495bSYour Name 25*5113495bSYour Name #define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_MU_MIMO 1 26*5113495bSYour Name 27*5113495bSYour Name 28*5113495bSYour Name struct mactx_eht_sig_usr_mu_mimo { 29*5113495bSYour Name #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30*5113495bSYour Name struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; 31*5113495bSYour Name #else 32*5113495bSYour Name struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; 33*5113495bSYour Name #endif 34*5113495bSYour Name }; 35*5113495bSYour Name 36*5113495bSYour Name 37*5113495bSYour Name /* Description MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS 38*5113495bSYour Name 39*5113495bSYour Name See detailed description of the STRUCT 40*5113495bSYour Name */ 41*5113495bSYour Name 42*5113495bSYour Name 43*5113495bSYour Name /* Description STA_ID 44*5113495bSYour Name 45*5113495bSYour Name Identifies the STA that is addressed. Details of STA ID 46*5113495bSYour Name are TBD 47*5113495bSYour Name */ 48*5113495bSYour Name 49*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 50*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_LSB 0 51*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MSB 10 52*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff 53*5113495bSYour Name 54*5113495bSYour Name 55*5113495bSYour Name /* Description STA_MCS 56*5113495bSYour Name 57*5113495bSYour Name Indicates the data MCS 58*5113495bSYour Name 0 - 13: MCS 0 - 13 59*5113495bSYour Name 14: validate 60*5113495bSYour Name 15: MCS 0 with DCM 61*5113495bSYour Name <legal 0-13, 15> 62*5113495bSYour Name */ 63*5113495bSYour Name 64*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 65*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_LSB 11 66*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MSB 14 67*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 68*5113495bSYour Name 69*5113495bSYour Name 70*5113495bSYour Name /* Description STA_CODING 71*5113495bSYour Name 72*5113495bSYour Name Distinguishes between BCC/LDPC 73*5113495bSYour Name 74*5113495bSYour Name 0: BCC 75*5113495bSYour Name 1: LDPC 76*5113495bSYour Name <legal all> 77*5113495bSYour Name */ 78*5113495bSYour Name 79*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 80*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_LSB 15 81*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MSB 15 82*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MASK 0x0000000000008000 83*5113495bSYour Name 84*5113495bSYour Name 85*5113495bSYour Name /* Description STA_SPATIAL_CONFIG 86*5113495bSYour Name 87*5113495bSYour Name Number of assigned spatial streams and their corresponding 88*5113495bSYour Name index. 89*5113495bSYour Name Total number of spatial streams assigned for the MU-MIMO 90*5113495bSYour Name allocation is also signaled. 91*5113495bSYour Name */ 92*5113495bSYour Name 93*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 94*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 16 95*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 21 96*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00000000003f0000 97*5113495bSYour Name 98*5113495bSYour Name 99*5113495bSYour Name /* Description RESERVED_0A 100*5113495bSYour Name 101*5113495bSYour Name <legal 0> 102*5113495bSYour Name */ 103*5113495bSYour Name 104*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 105*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_LSB 22 106*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MSB 22 107*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000400000 108*5113495bSYour Name 109*5113495bSYour Name 110*5113495bSYour Name /* Description RX_INTEGRITY_CHECK_PASSED 111*5113495bSYour Name 112*5113495bSYour Name TX side: Set to 0 113*5113495bSYour Name RX side: Set to 1 if PHY determines the CRC check of the 114*5113495bSYour Name codeblock containing this EHT-SIG user info has passed, 115*5113495bSYour Name else set to 0 116*5113495bSYour Name 117*5113495bSYour Name <legal all> 118*5113495bSYour Name */ 119*5113495bSYour Name 120*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 121*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23 122*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23 123*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000 124*5113495bSYour Name 125*5113495bSYour Name 126*5113495bSYour Name /* Description SUBBAND80_CC_MASK 127*5113495bSYour Name 128*5113495bSYour Name RX side: Set to 0 129*5113495bSYour Name TX side: Indicates what content channels of what 80 MHz 130*5113495bSYour Name subbands this User field can go to 131*5113495bSYour Name Bit 0: lowest 80 MHz content channel 0 132*5113495bSYour Name Bit 1: lowest 80 MHz content channel 1 133*5113495bSYour Name Bit 2: 2nd lowest 80 MHz content channel 0 134*5113495bSYour Name ... 135*5113495bSYour Name Bit 7: highest 80 MHz content channel 1 136*5113495bSYour Name <legal all> 137*5113495bSYour Name */ 138*5113495bSYour Name 139*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000 140*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24 141*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31 142*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000 143*5113495bSYour Name 144*5113495bSYour Name 145*5113495bSYour Name /* Description USER_ORDER_SUBBAND80_0 146*5113495bSYour Name 147*5113495bSYour Name RX side: Set to 0 148*5113495bSYour Name TX side: Ordering index of the User field within the lowest 149*5113495bSYour Name 80 MHz 150*5113495bSYour Name Gaps between the ordering indices of User fields indicate 151*5113495bSYour Name that the microcode shall generate "unallocated RU" User 152*5113495bSYour Name fields (STAID=2046) to fill the gaps. 153*5113495bSYour Name <legal all> 154*5113495bSYour Name */ 155*5113495bSYour Name 156*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000 157*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32 158*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39 159*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000 160*5113495bSYour Name 161*5113495bSYour Name 162*5113495bSYour Name /* Description USER_ORDER_SUBBAND80_1 163*5113495bSYour Name 164*5113495bSYour Name RX side: Set to 0 165*5113495bSYour Name TX side: Ordering index of the User field within the 2nd 166*5113495bSYour Name lowest 80 MHz 167*5113495bSYour Name See 'user_order_subband80_0.' 168*5113495bSYour Name <legal all> 169*5113495bSYour Name */ 170*5113495bSYour Name 171*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000 172*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40 173*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47 174*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000 175*5113495bSYour Name 176*5113495bSYour Name 177*5113495bSYour Name /* Description USER_ORDER_SUBBAND80_2 178*5113495bSYour Name 179*5113495bSYour Name RX side: Set to 0 180*5113495bSYour Name TX side: Ordering index of the User field within the 2nd 181*5113495bSYour Name highest 80 MHz 182*5113495bSYour Name See 'user_order_subband80_0.' 183*5113495bSYour Name <legal all> 184*5113495bSYour Name */ 185*5113495bSYour Name 186*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000 187*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48 188*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55 189*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000 190*5113495bSYour Name 191*5113495bSYour Name 192*5113495bSYour Name /* Description USER_ORDER_SUBBAND80_3 193*5113495bSYour Name 194*5113495bSYour Name RX side: Set to 0 195*5113495bSYour Name TX side: Ordering index of the User field within the highest 196*5113495bSYour Name 80 MHz 197*5113495bSYour Name See 'user_order_subband80_0.' 198*5113495bSYour Name <legal all> 199*5113495bSYour Name */ 200*5113495bSYour Name 201*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000 202*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56 203*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63 204*5113495bSYour Name #define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000 205*5113495bSYour Name 206*5113495bSYour Name 207*5113495bSYour Name 208*5113495bSYour Name #endif // MACTX_EHT_SIG_USR_MU_MIMO 209