1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _MACTX_U_SIG_EHT_TB_H_ 18 #define _MACTX_U_SIG_EHT_TB_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "u_sig_eht_tb_info.h" 23 #define NUM_OF_DWORDS_MACTX_U_SIG_EHT_TB 2 24 25 #define NUM_OF_QWORDS_MACTX_U_SIG_EHT_TB 1 26 27 28 struct mactx_u_sig_eht_tb { 29 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 30 struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details; 31 #else 32 struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details; 33 #endif 34 }; 35 36 37 /* Description MACTX_U_SIG_EHT_TB_INFO_DETAILS 38 39 See detailed description of the STRUCT 40 */ 41 42 43 /* Description PHY_VERSION 44 45 <enum 0 U_SIG_VERSION_EHT> 46 Values 1 - 7 are reserved. 47 <legal 0> 48 */ 49 50 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_OFFSET 0x0000000000000000 51 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_LSB 0 52 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MSB 2 53 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MASK 0x0000000000000007 54 55 56 /* Description TRANSMIT_BW 57 58 Bandwidth of the PPDU, as indicated in the trigger frame 59 60 61 <enum 0 U_SIG_BW20> 20 MHz 62 <enum 1 U_SIG_BW40> 40 MHz 63 <enum 2 U_SIG_BW80> 80 MHz 64 <enum 3 U_SIG_BW160> 160 MHz 65 <enum 4 U_SIG_BW320> 320 MHz channelization scheme 1 66 <enum 5 U_SIG_BW320_2> 320 MHz channelization scheme 2 67 68 On RX side, field used by MAC HW 69 <legal all> 70 */ 71 72 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 73 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_LSB 3 74 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MSB 5 75 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000000038 76 77 78 /* Description DL_UL_FLAG 79 80 Differentiates between DL and UL transmission 81 82 <enum 0 DL_UL_FLAG_IS_DL_OR_TDLS> 83 <enum 1 DL_UL_FLAG_IS_UL> 84 <legal all> 85 */ 86 87 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 88 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_LSB 6 89 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MSB 6 90 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000040 91 92 93 /* Description BSS_COLOR_ID 94 95 BSS color ID 96 97 Field used by MAC HW 98 <legal all> 99 */ 100 101 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 102 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_LSB 7 103 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MSB 12 104 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000001f80 105 106 107 /* Description TXOP_DURATION 108 109 Indicates the remaining time in the current TXOP 110 111 Field used by MAC HW 112 <legal all> 113 */ 114 115 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 116 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_LSB 13 117 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MSB 19 118 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000 119 120 121 /* Description DISREGARD_0A 122 123 Set to value indicated in the trigger frame 124 <legal all> 125 */ 126 127 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000 128 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_LSB 20 129 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MSB 25 130 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MASK 0x0000000003f00000 131 132 133 /* Description RESERVED_0C 134 135 <legal 0> 136 */ 137 138 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 139 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_LSB 26 140 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MSB 31 141 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MASK 0x00000000fc000000 142 143 144 /* Description EHT_PPDU_SIG_CMN_TYPE 145 146 <enum 3 EHT_PPDU_SIG_rsvd> DO NOT USE 147 <enum 0 EHT_PPDU_SIG_TB_or_DL_OFDMA> Need to look at both 148 EHT-SIG content channels for DL OFDMA (including OFDMA+MU-MIMO) 149 150 <enum 2 EHT_PPDU_SIG_DL_MU_MIMO> Need to look at both EHT-SIG 151 content channels 152 <enum 1 EHT_PPDU_SIG_SU> Need to look at only one EHT-SIG 153 content channel 154 <legal all> 155 */ 156 157 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000 158 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32 159 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33 160 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000 161 162 163 /* Description VALIDATE_1A 164 165 Set to value indicated in the trigger frame 166 <legal 1> 167 */ 168 169 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000 170 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_LSB 34 171 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MSB 34 172 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MASK 0x0000000400000000 173 174 175 /* Description SPATIAL_REUSE 176 177 TODO: Placeholder 178 <legal all> 179 */ 180 181 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 182 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_LSB 35 183 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MSB 42 184 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MASK 0x000007f800000000 185 186 187 /* Description DISREGARD_1B 188 189 Set to value indicated in the trigger frame 190 <legal all> 191 */ 192 193 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_OFFSET 0x0000000000000000 194 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_LSB 43 195 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MSB 47 196 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MASK 0x0000f80000000000 197 198 199 /* Description CRC 200 201 CRC for U-SIG contents 202 <legal all> 203 */ 204 205 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 206 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_LSB 48 207 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MSB 51 208 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MASK 0x000f000000000000 209 210 211 /* Description TAIL 212 213 <legal 0> 214 */ 215 216 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 217 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_LSB 52 218 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MSB 57 219 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 220 221 222 /* Description RESERVED_1C 223 224 <legal 0> 225 */ 226 227 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_OFFSET 0x0000000000000000 228 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_LSB 58 229 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MSB 62 230 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MASK 0x7c00000000000000 231 232 233 /* Description RX_INTEGRITY_CHECK_PASSED 234 235 TX side: Set to 0 236 RX side: Set to 1 if PHY determines the U-SIG CRC check 237 has passed, else set to 0 238 239 <legal all> 240 */ 241 242 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 243 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 244 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 245 #define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 246 247 248 249 #endif // MACTX_U_SIG_EHT_TB 250