1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _MON_BUFFER_ADDR_H_ 18 #define _MON_BUFFER_ADDR_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #define NUM_OF_DWORDS_MON_BUFFER_ADDR 4 23 24 #define NUM_OF_QWORDS_MON_BUFFER_ADDR 2 25 26 27 struct mon_buffer_addr { 28 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 29 uint32_t buffer_virt_addr_31_0 : 32; // [31:0] 30 uint32_t buffer_virt_addr_63_32 : 32; // [31:0] 31 uint32_t dma_length : 12, // [11:0] 32 reserved_2a : 4, // [15:12] 33 msdu_continuation : 1, // [16:16] 34 truncated : 1, // [17:17] 35 reserved_2b : 14; // [31:18] 36 uint32_t tlv64_padding : 32; // [31:0] 37 #else 38 uint32_t buffer_virt_addr_31_0 : 32; // [31:0] 39 uint32_t buffer_virt_addr_63_32 : 32; // [31:0] 40 uint32_t reserved_2b : 14, // [31:18] 41 truncated : 1, // [17:17] 42 msdu_continuation : 1, // [16:16] 43 reserved_2a : 4, // [15:12] 44 dma_length : 12; // [11:0] 45 uint32_t tlv64_padding : 32; // [31:0] 46 #endif 47 }; 48 49 50 /* Description BUFFER_VIRT_ADDR_31_0 51 52 Lower 32 bits of the 64-bit virtual address of the packet 53 buffer 54 <legal all> 55 */ 56 57 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_OFFSET 0x0000000000000000 58 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_LSB 0 59 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MSB 31 60 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MASK 0x00000000ffffffff 61 62 63 /* Description BUFFER_VIRT_ADDR_63_32 64 65 Upper 32 bits of the 64-bit virtual address of the packet 66 buffer 67 <legal all> 68 */ 69 70 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000000000000 71 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_LSB 32 72 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MSB 63 73 #define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff00000000 74 75 76 /* Description DMA_LENGTH 77 78 The number of bytes DMA'd into the packet buffer MINUS 1. 79 80 81 The packet could be truncated in case of a 'TX_FLUSH' or 82 'RX_FLUSH,' or in case of drops due to back-pressure. 83 <legal all> 84 */ 85 86 #define MON_BUFFER_ADDR_DMA_LENGTH_OFFSET 0x0000000000000008 87 #define MON_BUFFER_ADDR_DMA_LENGTH_LSB 0 88 #define MON_BUFFER_ADDR_DMA_LENGTH_MSB 11 89 #define MON_BUFFER_ADDR_DMA_LENGTH_MASK 0x0000000000000fff 90 91 92 /* Description RESERVED_2A 93 94 <legal 0> 95 */ 96 97 #define MON_BUFFER_ADDR_RESERVED_2A_OFFSET 0x0000000000000008 98 #define MON_BUFFER_ADDR_RESERVED_2A_LSB 12 99 #define MON_BUFFER_ADDR_RESERVED_2A_MSB 15 100 #define MON_BUFFER_ADDR_RESERVED_2A_MASK 0x000000000000f000 101 102 103 /* Description MSDU_CONTINUATION 104 105 When set, this packet buffer was not able to hold the entire 106 MSDU. The next buffer will therefore contain additional 107 packet bytes. 108 <legal all> 109 */ 110 111 #define MON_BUFFER_ADDR_MSDU_CONTINUATION_OFFSET 0x0000000000000008 112 #define MON_BUFFER_ADDR_MSDU_CONTINUATION_LSB 16 113 #define MON_BUFFER_ADDR_MSDU_CONTINUATION_MSB 16 114 #define MON_BUFFER_ADDR_MSDU_CONTINUATION_MASK 0x0000000000010000 115 116 117 /* Description TRUNCATED 118 119 When set, this TLV belongs to a previously truncated MPDU. 120 121 <legal all> 122 */ 123 124 #define MON_BUFFER_ADDR_TRUNCATED_OFFSET 0x0000000000000008 125 #define MON_BUFFER_ADDR_TRUNCATED_LSB 17 126 #define MON_BUFFER_ADDR_TRUNCATED_MSB 17 127 #define MON_BUFFER_ADDR_TRUNCATED_MASK 0x0000000000020000 128 129 130 /* Description RESERVED_2B 131 132 <legal 0> 133 */ 134 135 #define MON_BUFFER_ADDR_RESERVED_2B_OFFSET 0x0000000000000008 136 #define MON_BUFFER_ADDR_RESERVED_2B_LSB 18 137 #define MON_BUFFER_ADDR_RESERVED_2B_MSB 31 138 #define MON_BUFFER_ADDR_RESERVED_2B_MASK 0x00000000fffc0000 139 140 141 /* Description TLV64_PADDING 142 143 Automatic DWORD padding inserted while converting TLV32 144 to TLV64 for 64 bit ARCH 145 <legal 0> 146 */ 147 148 #define MON_BUFFER_ADDR_TLV64_PADDING_OFFSET 0x0000000000000008 149 #define MON_BUFFER_ADDR_TLV64_PADDING_LSB 32 150 #define MON_BUFFER_ADDR_TLV64_PADDING_MSB 63 151 #define MON_BUFFER_ADDR_TLV64_PADDING_MASK 0xffffffff00000000 152 153 154 155 #endif // MON_BUFFER_ADDR 156