1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _MON_INGRESS_RING_H_ 18 #define _MON_INGRESS_RING_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #include "buffer_addr_info.h" 23 #define NUM_OF_DWORDS_MON_INGRESS_RING 4 24 25 26 struct mon_ingress_ring { 27 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 28 struct buffer_addr_info buffer_addr_info_details; 29 uint32_t buffer_virt_addr_31_0 : 32; // [31:0] 30 uint32_t buffer_virt_addr_63_32 : 32; // [31:0] 31 #else 32 struct buffer_addr_info buffer_addr_info_details; 33 uint32_t buffer_virt_addr_31_0 : 32; // [31:0] 34 uint32_t buffer_virt_addr_63_32 : 32; // [31:0] 35 #endif 36 }; 37 38 39 /* Description BUFFER_ADDR_INFO_DETAILS 40 41 Consumer: TXMON/RXMON 42 Producer: SW 43 44 Details of the physical address of the buffer 45 46 'Sw_buffer_cookie' and 'Return_buffer_manager' sub-fields 47 are reserved and unused by TXMON/RXMON. 48 */ 49 50 51 /* Description BUFFER_ADDR_31_0 52 53 Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION 54 descriptor OR Link Descriptor 55 56 In case of 'NULL' pointer, this field is set to 0 57 <legal all> 58 */ 59 60 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 61 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 62 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 63 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff 64 65 66 /* Description BUFFER_ADDR_39_32 67 68 Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION 69 descriptor OR Link Descriptor 70 71 In case of 'NULL' pointer, this field is set to 0 72 <legal all> 73 */ 74 75 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 76 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 77 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 78 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff 79 80 81 /* Description RETURN_BUFFER_MANAGER 82 83 Consumer: WBM 84 Producer: SW/FW 85 86 In case of 'NULL' pointer, this field is set to 0 87 88 Indicates to which buffer manager the buffer OR MSDU_EXTENSION 89 descriptor OR link descriptor that is being pointed to 90 shall be returned after the frame has been processed. It 91 is used by WBM for routing purposes. 92 93 <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned 94 to the WMB buffer idle list 95 <enum 1 WBM_CHIP0_IDLE_DESC_LIST> This buffer shall be returned 96 to the WBM idle link descriptor idle list, where the chip 97 0 WBM is chosen in case of a multi-chip config 98 <enum 2 WBM_CHIP1_IDLE_DESC_LIST> This buffer shall be returned 99 to the chip 1 WBM idle link descriptor idle list 100 <enum 3 WBM_CHIP2_IDLE_DESC_LIST> This buffer shall be returned 101 to the chip 2 WBM idle link descriptor idle list 102 <enum 12 WBM_CHIP3_IDLE_DESC_LIST> This buffer shall be 103 returned to chip 3 WBM idle link descriptor idle list 104 <enum 4 FW_BM> This buffer shall be returned to the FW 105 <enum 5 SW0_BM> This buffer shall be returned to the SW, 106 ring 0 107 <enum 6 SW1_BM> This buffer shall be returned to the SW, 108 ring 1 109 <enum 7 SW2_BM> This buffer shall be returned to the SW, 110 ring 2 111 <enum 8 SW3_BM> This buffer shall be returned to the SW, 112 ring 3 113 <enum 9 SW4_BM> This buffer shall be returned to the SW, 114 ring 4 115 <enum 10 SW5_BM> This buffer shall be returned to the SW, 116 ring 5 117 <enum 11 SW6_BM> This buffer shall be returned to the SW, 118 ring 6 119 120 <legal 0-12> 121 */ 122 123 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 124 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 125 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 126 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 127 128 129 /* Description SW_BUFFER_COOKIE 130 131 Cookie field exclusively used by SW. 132 133 In case of 'NULL' pointer, this field is set to 0 134 135 HW ignores the contents, accept that it passes the programmed 136 value on to other descriptors together with the physical 137 address 138 139 Field can be used by SW to for example associate the buffers 140 physical address with the virtual address 141 The bit definitions as used by SW are within SW HLD specification 142 143 144 NOTE1: 145 The three most significant bits can have a special meaning 146 in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 147 and field transmit_bw_restriction is set 148 149 In case of NON punctured transmission: 150 Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 151 Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 152 Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 153 Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 154 Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 155 Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 156 Sw_buffer_cookie[19:18] = 2'b11: reserved 157 158 In case of punctured transmission: 159 Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 160 Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 161 Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 162 Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 163 Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 164 Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 165 Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 166 Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 167 Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 168 Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 169 Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 170 Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 171 Sw_buffer_cookie[19:18] = 2'b11: reserved 172 173 Note: a punctured transmission is indicated by the presence 174 of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 175 176 <legal all> 177 */ 178 179 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 180 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 181 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 182 #define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 183 184 185 /* Description BUFFER_VIRT_ADDR_31_0 186 187 Lower 32 bits of the 64-bit virtual address corresponding 188 to Buffer_addr_info_details 189 <legal all> 190 */ 191 192 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008 193 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 194 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 195 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff 196 197 198 /* Description BUFFER_VIRT_ADDR_63_32 199 200 Upper 32 bits of the 64-bit virtual address corresponding 201 to Buffer_addr_info_details 202 <legal all> 203 */ 204 205 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c 206 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 207 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 208 #define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff 209 210 211 212 #endif // MON_INGRESS_RING 213