1 /* 2 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef _PHYRX_ABORT_REQUEST_INFO_H_ 18 #define _PHYRX_ABORT_REQUEST_INFO_H_ 19 #if !defined(__ASSEMBLER__) 20 #endif 21 22 #define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1 23 24 25 struct phyrx_abort_request_info { 26 #ifndef WIFI_BIT_ORDER_BIG_ENDIAN 27 uint32_t phyrx_abort_reason : 8, // [7:0] 28 phy_enters_nap_state : 1, // [8:8] 29 phy_enters_defer_state : 1, // [9:9] 30 reserved_0 : 6, // [15:10] 31 receive_duration : 16; // [31:16] 32 #else 33 uint32_t receive_duration : 16, // [31:16] 34 reserved_0 : 6, // [15:10] 35 phy_enters_defer_state : 1, // [9:9] 36 phy_enters_nap_state : 1, // [8:8] 37 phyrx_abort_reason : 8; // [7:0] 38 #endif 39 }; 40 41 42 /* Description PHYRX_ABORT_REASON 43 44 <enum 0 phyrx_err_phy_off> Reception aborted due to receiving 45 a PHY_OFF TLV 46 <enum 1 phyrx_err_synth_off> 47 <enum 2 phyrx_err_ofdma_timing> 48 <enum 3 phyrx_err_ofdma_signal_parity> 49 <enum 4 phyrx_err_ofdma_rate_illegal> 50 <enum 5 phyrx_err_ofdma_length_illegal> 51 <enum 6 phyrx_err_ofdma_restart> 52 <enum 7 phyrx_err_ofdma_service> 53 <enum 8 phyrx_err_ppdu_ofdma_power_drop> 54 55 <enum 9 phyrx_err_cck_blokker> 56 <enum 10 phyrx_err_cck_timing> 57 <enum 11 phyrx_err_cck_header_crc> 58 <enum 12 phyrx_err_cck_rate_illegal> 59 <enum 13 phyrx_err_cck_length_illegal> 60 <enum 14 phyrx_err_cck_restart> 61 <enum 15 phyrx_err_cck_service> 62 <enum 16 phyrx_err_cck_power_drop> 63 64 <enum 17 phyrx_err_ht_crc_err> 65 <enum 18 phyrx_err_ht_length_illegal> 66 <enum 19 phyrx_err_ht_rate_illegal> 67 <enum 20 phyrx_err_ht_zlf> 68 <enum 21 phyrx_err_false_radar_ext> 69 <enum 22 phyrx_err_green_field> 70 <enum 60 phyrx_err_ht_nsym_lt_zero> 71 72 <enum 23 phyrx_err_bw_gt_dyn_bw> 73 <enum 24 phyrx_err_leg_ht_mismatch> 74 <enum 25 phyrx_err_vht_crc_error> 75 <enum 26 phyrx_err_vht_siga_unsupported> 76 <enum 27 phyrx_err_vht_lsig_len_invalid> 77 <enum 28 phyrx_err_vht_ndp_or_zlf> 78 <enum 29 phyrx_err_vht_nsym_lt_zero> 79 <enum 30 phyrx_err_vht_rx_extra_symbol_mismatch> 80 <enum 31 phyrx_err_vht_rx_skip_group_id0> 81 <enum 32 phyrx_err_vht_rx_skip_group_id1to62> 82 <enum 33 phyrx_err_vht_rx_skip_group_id63> 83 <enum 34 phyrx_err_ofdm_ldpc_decoder_disabled> 84 <enum 35 phyrx_err_defer_nap> 85 86 <enum 61 phyrx_err_vht_lsig_rate_mismatch> 87 <enum 62 phyrx_err_vht_paid_gid_mismatch> 88 <enum 63 phyrx_err_vht_unsupported_bw> 89 <enum 64 phyrx_err_vht_gi_disam_mismatch> 90 91 <enum 36 phyrx_err_fdomain_timeout> 92 <enum 37 phyrx_err_lsig_rel_check> 93 <enum 38 phyrx_err_bt_collision> 94 <enum 39 phyrx_err_unsupported_mu_feedback> 95 <enum 40 phyrx_err_ppdu_tx_interrupt_rx> 96 <enum 41 phyrx_err_unsupported_cbf> 97 98 <enum 42 phyrx_err_other> Should not really be used. If 99 needed, ask for documentation update 100 101 <enum 43 phyrx_err_he_siga_unsupported > <enum 44 phyrx_err_he_crc_error 102 > <enum 45 phyrx_err_he_sigb_unsupported > <enum 46 phyrx_err_he_mu_mode_unsupported 103 > <enum 47 phyrx_err_he_ndp_or_zlf > <enum 48 phyrx_err_he_nsym_lt_zero 104 > <enum 49 phyrx_err_he_ru_params_unsupported > <enum 50 105 phyrx_err_he_num_users_unsupported ><enum 51 phyrx_err_he_sounding_params_unsupported 106 > 107 <enum 54 phyrx_err_he_sigb_crc_error> 108 <enum 55 phyrx_err_he_ext_su_unsupported> 109 <enum 56 phyrx_err_he_trig_unsupported> 110 <enum 57 phyrx_err_he_lsig_len_invalid> 111 <enum 58 phyrx_err_he_lsig_rate_mismatch> 112 <enum 59 phyrx_err_ofdma_signal_reliability> 113 114 <enum 77 phyrx_err_wur_detection> 115 116 <enum 72 phyrx_err_u_sig_crc_error> 117 <enum 73 phyrx_err_u_sig_unsupported_mode> 118 <enum 74 phyrx_err_u_sig_rsvd_err> 119 <enum 75 phyrx_err_u_sig_mcs_error> 120 <enum 76 phyrx_err_u_sig_bw_error> 121 <enum 79 phyrx_err_u_sig_320_channel_mismatch> 122 <enum 71 phyrx_err_eht_sig_crc_error> 123 <enum 78 phyrx_err_eht_sig_unsupported_mode> 124 125 <enum 80 phyrx_err_ehtplus_er_detection> 126 127 <enum 52 phyrx_err_MU_UL_no_power_detected> 128 <enum 53 phyrx_err_MU_UL_not_for_me> 129 130 <enum 65 phyrx_err_rx_wdg_timeout> 131 <enum 66 phyrx_err_sizing_evt_unexpected> 132 <enum 67 phyrx_err_spectralscan> 133 <enum 68 phyrx_err_radar_misdetected_as_ofdm> 134 <enum 69 phyrx_err_rx_stuck> 135 <enum 70 phyrx_err_invalid_11b_state> 136 137 <legal 0 - 80> 138 */ 139 140 #define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_OFFSET 0x00000000 141 #define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_LSB 0 142 #define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MSB 7 143 #define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MASK 0x000000ff 144 145 146 /* Description PHY_ENTERS_NAP_STATE 147 148 When set, PHY enters PHY NAP state after sending this abort 149 150 151 Note that nap and defer state are mutually exclusive. 152 153 Field put pro-actively in place....usage still to be agreed 154 upon. 155 <legal all> 156 */ 157 158 #define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_OFFSET 0x00000000 159 #define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_LSB 8 160 #define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MSB 8 161 #define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MASK 0x00000100 162 163 164 /* Description PHY_ENTERS_DEFER_STATE 165 166 When set, PHY enters PHY defer state after sending this 167 abort 168 169 Note that nap and defer state are mutually exclusive. 170 171 Field put pro-actively in place....usage still to be agreed 172 upon. 173 <legal all> 174 */ 175 176 #define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_OFFSET 0x00000000 177 #define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_LSB 9 178 #define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MSB 9 179 #define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 180 181 182 /* Description RESERVED_0 183 184 <legal 0> 185 */ 186 187 #define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000 188 #define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 10 189 #define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15 190 #define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x0000fc00 191 192 193 /* Description RECEIVE_DURATION 194 195 The remaining receive duration of this PPDU in the medium 196 (in us). When PHY does not know this duration when this 197 TLV is generated, the field will be set to 0. 198 The timing reference point is the reception by the MAC of 199 this TLV. The value shall be accurate to within 2us. 200 201 In case Phy_enters_nap_state and/or Phy_enters_defer_state 202 is set, there is a possibility that MAC PMM can also decide 203 to go into a low(er) power state. 204 <legal all> 205 */ 206 207 #define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_OFFSET 0x00000000 208 #define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_LSB 16 209 #define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MSB 31 210 #define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MASK 0xffff0000 211 212 213 214 #endif // PHYRX_ABORT_REQUEST_INFO 215